JP2000172573A - Digital integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely obstruct access from the outside for secret data and to easily perform a highly reliable inspection at the time of a test by providing a control means for limiting the access from the outside to a storage means by destroying and disconnecting a control element. SOLUTION: A security circuit controls a specified storage area where the secret data are written in respective circuit parts so as not to be accessed from the outside by making a current more than the rating flow and physically destroying and disconnecting a fuse element 21d to be the control element. That is, after the test is ended and the secret data are written in the respective circuit parts, the control terminal 21b is turned to a ground level and a power supply voltage is applied to a ground terminal 21c. At the time, the current more than the rating of the fuse element 21d flows to a diode D1 and the fuse element 21d and the fuse element 21d is destroyed and disconnected. Then, thereafter, disable signals are fixed at an H level regardless of the voltage level of the control terminal 21b and the ground terminal 21c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a digital integrated circuit which protects digital data to be concealed from external access.

[0002]

2. Description of the Related Art As is well known, for example, in a digital integrated circuit for performing an encryption process on digital data,
Data to be concealed, such as data serving as a key for the encryption processing and program data for executing the encryption processing algorithm, are stored in the internal memory.

In this case, the digital integrated circuit is designed so that the confidential data stored in its internal memory is not illegally read or rewritten from the outside, that is, the confidential data is stored from the outside. Protection measures are in place to make access impossible.

[0004] On the other hand, after a digital integrated circuit of this type is manufactured in a factory, a test is performed to confirm whether various internal circuits including its internal memory operate normally. As this test, a method is used in which predetermined data is actually input to various internal circuits and whether or not an expected output is obtained.

Therefore, as described above, the internal memory is provided with a protection measure so that the data stored therein cannot be accessed from outside.
The ability to easily perform manufacturing tests is a conflicting technique, which makes the design and manufacture of digital integrated circuits difficult.

Usually, LSI (Large Scale Integrated c)
ircuit) Inspection at the time of manufacture is performed using an LSI tester, and it is required to be able to complete the inspection in a short time and to reduce the number of untested circuit portions as much as possible. In particular, RAM (Random Access) inside the LSI
In the inspection of (Memory), it is necessary to check whether writing and reading are performed normally over all the addresses.

To this end, a test mode is set for each circuit portion of the LSI. For example, when a test mode of the RAM is designated, the address terminal and the data terminal of the RAM are connected to the tester via the connection pins of the LSI. The LSI is designed such that when a test mode of a special operation circuit used for the encryption processing is designated, an input / output terminal of the circuit is connected to a tester via a connection pin of the LSI.

On the other hand, with respect to a circuit portion to be protected from external access, fixed data is created by connecting wires connecting elements inside the LSI to a power supply terminal or a ground terminal and making the data public. The test can be performed only in accordance with the cryptographic procedure. Also, in order to prevent data during the inspection from leaking to the outside, it is considered that the output of each circuit portion does not go outside.

As described above, if the intermediate data cannot be taken out of the LSI and can be tested only in accordance with the disclosed cryptographic procedure, a plurality of circuits are required to check a specific circuit. Since the test is performed through the test, the input data pattern for the test becomes long, and it becomes difficult to activate as many circuit elements as possible under test.

[0010] In particular, the confidential data is stored in each LSI.
For example, as described in Japanese Patent Application Laid-Open No. 7-45782, data for writing and reading different data for each LSI or each device is different from each other or for each device equipped with the LSI. Chips and
Processing such as molding a chip for encryption processing on the same substrate is required.

Here, conventionally, for example, Japanese Patent Laid-Open No. 5-75
No. 597, for example, has proposed an encryption LSIC. The cryptographic processing LSIC includes a memory unit that stores secret data, a control unit that controls whether data read from the memory unit can be output to the outside, and a storage unit that stores a write address of the secret data to the memory unit. A comparison unit that compares a write address stored in the storage unit with a read address to the memory unit,
The control unit is controlled to enable output only in the test mode when the comparison result of the comparison unit matches.

However, in this cryptographic processing LSIC, a necessary condition is that when the test mode is set, all the stored contents of the storage unit are reset. For this reason,
In the actual use state, if the test mode is entered for some reason, it is necessary to write the confidential data in the memory unit again and store the write address in the storage unit, so that the user must handle it. There is a problem of inconvenience.

[0013]

As described above, the conventional digital integrated circuit protects confidential data so that it cannot be accessed from the outside and makes it possible to easily perform a test at the time of manufacturing. However, there is a problem that each of them has not yet reached a level that can be practically used.

Therefore, the present invention has been made in view of the above circumstances, and it is possible to reliably prevent external access to confidential data, and to easily perform a highly reliable inspection at the time of a test. It is an object of the present invention to provide a very good digital integrated circuit.

[0015]

SUMMARY OF THE INVENTION A digital integrated circuit according to the present invention is intended for a digital integrated circuit having storage means for writing and reading data by external access, and is capable of physically destructive cutting. An element is provided, and control means for restricting external access to the storage means by breaking and cutting the control element is provided.

According to the above configuration, before the control element is broken and cut, the storage means can be accessed from the outside, so that a highly reliable test can be easily performed. Further, after the control element is broken and cut off, external access to the storage means is restricted, so that external access to confidential data can be reliably prevented.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIG. 1 shows the appearance of a digital LSI 10 described in this embodiment. The digital LSI 10 includes a main body 10a in which a semiconductor chip 11 on which various circuits described below are formed is sealed in a resin package, and a plurality of leads 10b protruding from the main body 10a.

FIG. 2 shows various circuits formed on the semiconductor chip 11. First, the scramble circuit 1
No. 2 performs scramble processing on the input plaintext data, converts it into ciphertext data, and outputs it.

A host I / F (Inter / Face) circuit 1
Reference numeral 3 denotes an interface for communicating with a computer (not shown) provided outside the digital LSI 10. The host I / F circuit 13 stores address data and a chip select signal C sent from the computer.
It has a function of inputting S, a write enable signal WE, a read enable signal RE, and the like, a function of bidirectionally communicating data with a computer, and a function of outputting an interrupt signal INT, a standby signal WAIT, and the like to the computer.

The control circuit 14 is a digital LSI
10 to control the operation of the encryption key decompression program. A ROM (Read Only Memory) 15 stores fixed data such as public key data and programs. The RAM 16 provides an I / F area for performing data communication with an external computer and a calculation work area.

Furthermore, EEP (Electrically Erasable)
The ROM 17 is capable of rewriting different data for each device and has a function of storing data without a battery. ALU (Arithmetic Logical Uni
t) 18 is a special arithmetic unit for performing a special operation for encryption.

Further, the test circuit 19 selectively switches each circuit portion to a state where it can be inspected from outside the digital LSI 10 based on a test mode signal input from the outside. The initialization circuit 20 generates an initialization pulse for initializing each circuit part based on an initialization request signal INIT supplied when the power of the device is turned on.

Although the security circuit 21 will be described in detail later, the fuse element serving as a control element is physically destroyed and cut by passing a current higher than the rated value, so that the secret data of each circuit portion is written. This control is performed so that the specified storage area cannot be accessed from outside. Before the fuse element is broken and cut, each circuit portion can be freely accessed from the outside, so that the test can be easily performed.

FIG. 3 shows details of the security circuit 21. That is, the power supply terminal 21a and the control terminal 2
1b and the ground terminal 21c are digital LSI
It is connected to ten different leads 10b. The power supply terminal 21a is connected to the control terminal 21b via the diode D1 in the reverse direction and then via the fuse element 21d.

The diode D1 and the fuse element 21
The connection point with d is connected to the ground terminal 21c via the resistor R1 and to the input terminal of the buffer circuit 21e. The ground terminal 21c is commonly connected to the ground terminal of each circuit part. The output of the buffer circuit 21e is the output of the security circuit 21 and is a disable signal for controlling whether or not each circuit portion of the digital LSI 10 can be accessed from outside.

Here, the fuse element 21d has a function as a current fuse that cuts by physically destructing the heat by passing a current higher than a predetermined rating, and is formed at the time of manufacturing the semiconductor chip 11. Specifically, for example, those described in JP-A-8-64105 and JP-A-10-261359 are used.

In the configuration shown in FIG. 3, first, at the time of inspection after manufacturing the digital LSI 10, the fuse element 21d
Is not disconnected, the power supply voltage V is applied to the power supply terminal 21a.
When dd is applied and H (High) level is applied to the control terminal 21b, an H level disable signal is output from the buffer circuit 21e. In this state, since each circuit portion can be freely accessed from the outside, the test of each circuit portion can be easily performed.

When an L (Low) level is applied to the control terminal 21b in a state where the power supply voltage Vdd is applied to the power supply terminal 21a, an L level disable signal is output from the buffer circuit 21e. In this state, among the circuit parts of the digital LSI 10, the part where the secret data is written is set so that it cannot be accessed from outside.

That is, by selectively setting the control terminal 21b to the H level and the L level while the power supply voltage Vdd is applied to the power supply terminal 21a, the test of each circuit portion and the secret data cannot be accessed from outside. Test of things.

When the test is completed, for example, the EEPROM 17
After writing the secret data into the control terminal 21b, the power supply voltage Vdd is applied to the control terminal 21b, and the power supply terminal 21a is set to the ground level.
At this time, the fuse element 21d and the diode D1
A current exceeding the rating of the fuse element 21d flows, and the fuse element 21d is broken and cut. Then, regardless of the voltage levels of the power supply terminal 21a and the control terminal 21b, the disable signal is fixed at the L level, and the confidential data is reliably protected.

FIG. 4 shows a modification of the security circuit 21. That is, the power supply terminal 21a is connected to the control terminal 21b via the resistor R1 and the fuse element 21d. The power supply terminal 21a is commonly connected to a power supply terminal of each circuit portion. The connection point between the resistor R1 and the fuse element 21d is connected in the opposite direction to the ground terminal 21c via the diode D1 and to the input terminal of the buffer circuit 21e.

In the configuration shown in FIG. 4, first, at the time of inspection after the manufacture of the digital LSI 10, the fuse element 21d
Is not disconnected, the power supply voltage V is applied to the power supply terminal 21a.
When dd is applied and L level is applied to the control terminal 21b,
An L-level disable signal is output from the buffer circuit 21e. In this state, since each circuit portion can be freely accessed from the outside, the test of each circuit portion can be easily performed.

When an H level is applied to the control terminal 21b in a state where the power supply voltage Vdd is applied to the power supply terminal 21a, an H level disable signal is output from the buffer circuit 21e. In this state, the digital LSI
Of the ten circuit parts, the part where the confidential data is written is set so that it cannot be accessed from outside.

That is, by selectively setting the control terminal 21b to the L level and the H level while the power supply voltage Vdd is applied to the power supply terminal 21a, the test of each circuit portion and the secret data cannot be accessed from outside. Test of things.

After the test is completed and the secret data is written in each circuit portion, the control terminal 21b is set to the ground level, and the power supply voltage Vdd is applied to the ground terminal 21c. At this time, a current higher than the rating of the fuse element 21d flows through the diode D1 and the fuse element 21d, and the fuse element 21d is broken and cut. Then, irrespective of the voltage levels of the control terminal 21b and the ground terminal 21c, the disable signal is fixed at the H level, and the confidential data is reliably protected.

The fuse element 2 is used as a control element.
It is not limited to 1d, but any material that can be physically broken and cut by applying non-kinetic energy (not mechanical energy such as pressure) such as heat, light, or electricity from the outside can be used. it can.

FIG. 5 shows the security circuit 2 shown in FIG.
1 by the disable signal output from
An example is shown in which writing and reading control to and from the EPROM 17 are performed. That is, the write enable signal WE and the read enable signal RE output from the host I / F circuit 13 and the first to third signals generated by the address decoder 13a in the host I / F circuit 13 based on the upper address. Chip select signal C
S1 to CS3 and the disable signal output from the security circuit 21 are supplied to the logic circuit 22.

The logic circuit 22 generates a chip select signal CS, a write enable signal WE, and a read enable signal RE for the EEPROM 17 based on the input signals. Note that this EE
The PROM 17 has a write data input terminal connected to a write data WDATA transmission line, a read data output terminal connected to a read data RDATA transmission line, and an address input terminal connected to a lower address transmission line. .

Here, in the logic circuit 22, CS
Output = CS1 + CS2 + CS3, WE output = (CS1 +
CS2 * disable signal + CS3 * disable signal) * input WE, RE output = (CS1 + CS2 + CS
An operation of 3 * disable signal) * input RE is performed to generate a chip select signal CS, a write enable signal WE, and a read enable signal RE, respectively.

In the configuration shown in FIG. 5, first, at the time of inspection after manufacturing the digital LSI 10, the security circuit 2
Since the first fuse element 21d is not cut, the power supply voltage Vdd is applied to the power supply terminal 21a as described above.
When an H level is applied to the control terminal 21b, the security circuit 21 outputs an H level disable signal.

In this state, in the logic circuit 22, the operation of the above equation is performed by the following equation: CS output = CS1 + CS2 + CS
3, WE output = (CS1 + CS2 + CS3) * input W
E, RE output = (CS1 + CS2 + CS3) * input RE
Becomes That is, the entire address area of the EEPROM 17 can be accessed from the outside, and the writing and reading tests can be easily performed.

In this state, secret data is written to a predetermined address of the EEPROM 17, and as described above, the power supply terminal 21a is set to the ground level, the power supply voltage Vdd is applied to the control terminal 21b, and the fuse element 21d is broken and cut. , The security circuit 21 outputs an L-level disable signal.

In this state, in the logic circuit 22, the operation of the above equation is based on CS output = CS 1 + CS 2 + CS 3, WE
Output = CS1 * input WE, RE output = (CS1 + CS
2) * Input RE. That is, the EEPROM 17
Both writing and reading are enabled for the area specified by the chip select signal CS1, writing is disabled for the area specified by the chip select signal CS2, and reading is enabled for the area specified by the chip select signal CS3. Both are controlled to be disabled.

Then, in an area where writing and reading are impossible in the EEPROM 17, that is, in an inaccessible area, for example, a secret key, a secret parameter of encryption, an execution program of a secret encryption algorithm, and the like are written as secret data. Will be.

As the security circuit 21, FIG.
Is used as the logic circuit 22, CS output = CS1 + CS2 + CS3, W
E output = (CS1 + CS2 * disable signal bar + CS3 * disable signal bar) * input WE, R
By performing the operation of E output = (CS1 + CS2 + CS3 * disable signal bar) * input RE, the same control as described above can be performed on the EEPROM 17.

FIG. 6 explains the test and the protection of secret data in the scramble process. That is, the scramble circuit 12 includes a shuffle circuit 12a for performing scramble processing on input data and a host I / F
An address decoder 12b for decoding addresses from the circuit 13 and the control circuit 14, a register 12c for writing a scramble key, a control register 12d for determining a scramble mode, and a state register 1 indicating the state of the scramble circuit 12 and the state of input data.
2e.

The control circuit 14 includes a general register 14a, an instruction register 14b, and an address generator 14c. Further, the ALU 18, which is a special operation unit for decompressing the encryption key, is provided with an input register 18a.
, An output register 18b, and a calculation unit 18c.

When an instruction is externally written into the instruction register 14b of the control circuit 14, the control circuit 14 controls each circuit of the digital LSI chip 10 according to the instruction. For example, assuming that the scramble key is to be decompressed, after the encryption key data is written from the outside into the RAM 16, the key decompression instruction is issued to the instruction register 1.
4b.

The control circuit 14 writes the encryption key data in the RAM 16 into the input register 18a of the ALU 18. Then, the operation result of the ALU 18 is output to the output register 1
8b. The control circuit 14 reads the data of the output register 18b into the general register 14a,
A series of programs for writing to the register 12c of the scramble circuit 12 is executed. When the execution of the instruction from the outside is completed, the control circuit 14 sets an internal status flag or generates an interrupt to notify the outside.

At the time of manufacturing inspection of the digital LSI 10, test mode data is given to the test circuit 19 so that a test can be performed for each circuit portion. For example, when testing the scramble circuit 12, an internal circuit is controlled so that all registers of the scramble circuit 12 can be accessed from the outside via the host I / F circuit 13.

Thereafter, the temporary scramble key is written into the register 12c, and the temporary prescribed data is supplied to the shuffle circuit 12a as input data. Then, it is determined whether or not predetermined expected value data is obtained as output data. If a part of the scramble circuit 12 is defective, the output data is different from the expected value, so that it can be determined that the product is defective. The ALU 18 can be tested in a similar manner.

Here, the register 12c of the scramble circuit 12 and the general register 14 of the control circuit 14
Since the data to be concealed are latched in the output register 18a and the output register 18b of the ALU 18, it is imperative that the contents of these registers 12c, 14a, and 18b cannot be accessed from outside.

When the disable signal is at the H level, the internal circuits can be freely accessed from the outside by the security circuit 21 shown in FIG. 3, and when the disable signal is at the L level, the registers 12c, 14a, 1
By setting the content of 8b so that it cannot be accessed from outside, the test can be easily performed, and the confidential data can be surely protected.

It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the scope of the invention.

[0055]

As described in detail above, according to the present invention,
It is possible to provide an extremely good digital integrated circuit that can reliably prevent external access to confidential data and can easily perform a highly reliable inspection at the time of testing.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a digital integrated circuit according to the present invention, and is an external view showing a digital LSI.

FIG. 2 is a block diagram showing a semiconductor chip in the digital LSI.

FIG. 3 is a block diagram showing a security circuit formed on the semiconductor substrate.

FIG. 4 is a block diagram showing another example of the security circuit.

FIG. 5 is a block diagram for explaining an example in which writing and reading of an EEPROM are controlled by the security circuit.

FIG. 6 is a block diagram illustrating a scramble operation of the digital LSI chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital LSI, 11 ... Semiconductor chip, 12 ... Scramble circuit, 13 ... Host I / F circuit, 14 ... Control circuit, 15 ... ROM, 16 ... RAM, 17 ... EEPROM, 18 ... ALU, 19 ... Test circuit, 20 ... Initialization circuit, 21 ... Security circuit, 22 ... Logic circuit.

Claims (5)

[Claims] 1. A digital integrated circuit having storage means for writing and reading data by external access, comprising a control element which is physically destructible and severable. A digital integrated circuit comprising control means for restricting external access to said storage means. 2. The control means generates a first output signal permitting external access to the storage means in a state where the control element is not broken and cut, and the control element is broken and cut. 2. The digital integrated circuit according to claim 1, wherein a second output signal for limiting external access to said storage means is generated in said state. 3. The digital integrated circuit according to claim 2, wherein the control element is a fuse element that is physically destructed and cut by flowing a current higher than a rating. 4. The control means includes: a first terminal; a diode having a cathode connected to the first terminal; the fuse element having one end connected to an anode of the diode; A second terminal to which an end is connected; a resistor having one end connected to a connection point between the diode and the fuse element; and a third terminal to which the other end of the resistor is connected. By combining the voltage levels applied to the first to third terminals so that no directional current flows, the first and second output signals can be selectively output from the connection point of the diode and the fuse element. The fuse can be generated by combining voltage levels applied to the first to third terminals so that a forward current flows through the diode. Destroying cutting child, the diode and the digital integrated circuit according to claim 3, characterized in that fixedly generating the second output signal from a connection point of the fuse element. 5. The control means includes: a first terminal; a resistor having one end connected to the first terminal; the fuse element having one end connected to the other end of the resistor; A second terminal connected to the other end of the diode, a diode having a cathode connected to a connection point between the resistor and the fuse element, and a third terminal connected to an anode of the diode. By combining voltage levels applied to the first to third terminals so as to prevent a forward current from flowing, the first and second output signals can be selectively output from a connection point between the resistor and the fuse element. The fuse element is broken by combining the voltage levels applied to the first to third terminals so that a forward current flows through the diode. Cutting to the resistor and the digital integrated circuit according to claim 3, characterized in that fixedly generating the second output signal from a connection point of the fuse element.