JP2000165231A - Frequency dividing circuit and frequency divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a frequency dividing circuit that can divide a frequency of an input clock signal even when a voltage of the clock signal is as low as 1V. SOLUTION: An emitter of one transistor(TR) Q9 of input side differential TR pairs 3 constituting a master stage circuit 27A is connected to a common emitter of output side differential TR pairs 5 constituting the master stage circuit 27A, an emitter of the other TR Q10 of output side differential TR pairs 5 constituting the master stage circuit 27A is connected to a common emitter of output side differential TR pairs 6 constituting the master stage circuit 27A, an emitter of one TR Q11 of input side differential TR pairs 4 constituting slave stage circuit 28A is connected to a common emitter of 3rd output side differential TR pairs 7 constituting the slave stage circuit 28A, and an emitter of the other TR Q12 of the input side differential TR pairs 4 is connected to a common emitter of 4th output side differential TR pairs 8 constituting the slave stage circuit 28A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider using bipolar transistors used in semiconductor devices and the like.

[0002]

2. Description of the Related Art A conventional frequency divider will be described below with reference to FIG.

As shown in FIG. 5, this frequency divider circuit has a bipolar double differential master in which a complementary clock signal is inputted to a differential input terminal from a pair of toggle input terminals 1 and 2. Complementary clock signals are input to the differential input terminal from the stage circuit 27E and the pair of toggle input terminals 1 and 2 to output a differential output to the pair of frequency-divided differential output terminals 23 and 24. Double differential slave stage circuit 2
8E, a first feedback line 29 for feeding back the differential output of the slave stage circuit 28E to the master stage circuit 27E, and a second feedback line for feeding back the differential output of the master stage circuit 27E to the slave stage circuit 28E. 30.

The master stage circuit 27E includes a first input-side differential transistor pair 3, a first output-side differential transistor pair 5, first and second resistors 11, 12,
The second output differential transistor pair 6 and the first current source 2
5 is comprised.

[0005] The first input-side differential transistor pair 3 receives complementary clock signals from one and the other transistors Q
9 and Q10, respectively.

The first output-side differential transistor pair 5 is connected to the collector of one transistor Q9 of the first input-side differential transistor pair 3 by one and the other transistor Q1,
The common emitter of Q4 is connected.

The first and second resistors 11 and 12 are connected to the first
Of the output-side differential transistor pair 5 and the collectors of the other transistors Q1 and Q4 and the first power supply node 21
And are connected between them.

The second output-side differential transistor pair 6 has one and the other transistor Q connected to the collector of the other transistor Q10 of the first input-side differential transistor pair 3.
2 and Q3 are connected to one another and the other transistor Q of the first output-side differential transistor pair 5.
One and the other transistors Q
2 and Q3 are connected to each other, and the bases of one and the other transistors Q2 and Q3 are connected to the other of the first output-side differential transistor pair 5 and the collectors of the transistors Q4 and Q1, respectively.

The first current source 25 includes one and the other transistors Q9 and Q9 of the first input-side differential transistor pair 3.
One end is commonly connected to the emitter of Q10, and the other end is connected to the second power supply node 22.

The slave stage circuit 28E includes a second input-side differential transistor pair 4, a third output-side differential transistor pair 7, third and fourth resistors 17, 18 and a fourth The output side differential transistor pair 8 and the second current source 26
It is composed of

The second input-side differential transistor pair 4 supplies complementary clock signals to one and the other transistors Q
11 and Q12.

The third output-side differential transistor pair 7 has one and the other transistor Q connected to the collector of one transistor Q11 of the second input-side differential transistor pair 4.
5, Q8 common emitters are connected.

The third and fourth resistors 17, 18 are connected to the third
Collectors of one and the other transistors Q5 and Q8 of the output-side differential transistor pair 7 and the first power supply node 21
And are connected between them.

The fourth output-side differential transistor pair 8 has one and the other transistor Q connected to the collector of the other transistor Q12 of the second input-side differential transistor pair 4.
6 and Q7 are connected to one another and the other transistor Q of the third output-side differential transistor pair 7.
5 and Q8 are connected to one and the other transistor Q
6 and Q7 are connected to each other, and the bases of one and the other transistors Q6 and Q7 are connected to the other of the third output-side differential transistor pair 7 and the collectors of the transistors Q8 and Q5, respectively.

The second current source 26 is connected to one and the other transistors Q1 of the second input-side differential transistor pair 4.
One end is commonly connected to the emitters of Q1, Q12, and the other end is connected to the second power supply node 22.

The first feedback wiring 29E connects the collectors of one and the other transistors Q5 and Q8 of the third output-side differential transistor pair 7 to one and the other of the first output-side differential transistor pair 5. Connected to the bases of transistors Q1 and Q4, respectively.

The second feedback line 30E connects the collectors of one and the other transistors Q1 and Q4 of the first output-side differential transistor pair 5 to the other and one of the third output-side differential transistor pair 7. Connected to the bases of transistors Q8 and Q5, respectively.

The operation of the above configuration will be described below. The operation of the frequency divider configured as above will be described. This frequency dividing circuit takes four transition states and changes the voltage values input to the toggle input terminals (T, / T) 1 and 2 to V1, V2 and the transistors Q1 to Q12, respectively.
When a current flows through the transistor Q1 in the first transition state (V1> V2), the transistor Q1 is turned off and the transistor Q2 is turned off.
N, transistor Q3 is OFF, transistor Q4 is O
FF, transistor Q5 is ON, transistor Q6 is O
FF, transistor Q7 is OFF, transistor Q8 is OFF, transistor Q9 is OFF, transistor Q1
0 is ON, transistor Q11 is ON, transistor Q
12 is OFF.

Next, in the second transition state (V1 <V2), the transistor Q1 is OFF and the transistor Q2 is OFF.
FF, transistor Q3 is OFF, transistor Q4 is ON, transistor Q5 is OFF, transistor Q6 is ON, transistor Q7 is OFF, transistor Q8 is OFF, transistor Q9 is ON, transistor Q10
Is OFF, the transistor Q11 is OFF, and the transistor Q12 is ON.

Next, in the third transition state (V1> V2), the transistor Q1 is OFF and the transistor Q2 is OFF.
FF, transistor Q3 is ON, transistor Q4 is O
FF, transistor Q5 is OFF, transistor Q6 is OFF, transistor Q7 is OFF, transistor Q8
Is ON, transistor Q9 is OFF, transistor Q1
0 is ON, transistor Q11 is ON, transistor Q
12 is OFF.

Next, in the fourth transition state (V1 <V2), the transistor Q1 is ON, and the transistor Q2 is OFF.
F, transistor Q3 is OFF, transistor Q4 is O
FF, transistor Q5 is OFF, transistor Q6 is OFF, transistor Q7 is ON, transistor Q8 is OFF, transistor Q9 is ON, transistor Q10
Is OFF, the transistor Q11 is OFF, and the transistor Q12 is ON.

Each time the states of V1 and V2 are inverted, the above transition state is repeated.

At this time, the frequency-divided differential output terminals (Q,
/ Q) Assuming that the voltages of 23 and 24 are V23 and V24, respectively, V23> V24 in the first transition state, V23> V24 in the second transition state, and V23 <V24 in the third transition state, V4 in the fourth transition state
3 <V24.

FIG. 6 shows toggle input terminals (T, / T) 1, 2
Shows the relationship between the voltage values V1 and V2 input to the input terminals and the voltages V23 and V24 of the divided differential output terminals (Q, / Q) 23 and 24.

With the above operation, the frequency dividing circuit divides the frequency of the clock signal input to the toggle input terminals 1 and 2 by 、, and the divided frequency signals from the divided output terminals 23 and 24 are in opposite phases. A pair of divided waveforms will be output.
That is, a frequency divider that divides the clock signal by ク ロ ッ ク can be realized.

[0026]

However, in the conventional frequency divider as described above, the first power supply node 2
There is a problem that the circuit operates only until the potential difference between the first and second power supply nodes 22 is about 1.8 V (lower limit), and it is not possible to reduce the voltage and power consumption of the circuit.

Here, the reason why the potential difference between the first power supply node 21 and the second power supply node 22 operates only up to about 1.8 V, and it is not possible to reduce the voltage and power consumption of the circuit will be described. In a frequency divider circuit using ECL (emitter-coupled logic), the operation speed is deteriorated when the transistor is used with saturation. Therefore, the collector-emitter voltage of the transistor performing the switching operation is set to 0.5
It is necessary to secure about V or more. Each resistor 11, 12, 1
Assuming that the voltage between both ends of the transistors 7 and 18 is 0.1 V, the voltage between the base and the emitter of the transistor is 0.9 V, and the potential difference between the bias voltage of the input terminal and the power supply node 22 is 1.2 V, the collectors of the transistors Q1 to Q8 The voltage between the emitters becomes 0.8V, and the voltage between the collector and the emitter of the transistors Q9 to Q12 becomes 0.5V. Current sources 25, 26
Should be about 0.3V. Therefore, if the potential difference is further reduced, the voltage between the collector and the emitter of the transistors Q9 to Q12 is reduced, and the operating speed is reduced.

The present invention has been made in view of such conventional problems, and a frequency divider circuit capable of dividing an input clock signal even at a low voltage and achieving low power consumption. And a frequency divider.

[0029]

In order to achieve the above object, a frequency divider according to a first aspect of the present invention is configured such that a complementary clock signal is input to a differential input terminal from a pair of toggle input terminals. Complementary clock signal is input to a differential input terminal from a pair of toggle input terminals and a differential output is output to a pair of divided differential output terminals. Bipolar double differential type slave stage circuit, first feedback wiring for feeding back the differential output of the slave stage circuit to the master stage circuit, and feeding back the differential output of the master stage circuit to the slave stage circuit And a second return wiring.

The emitter of one transistor of the first input-side differential transistor pair forming the master stage circuit is connected to one of the first and second transistors of the first output-side differential transistor pair forming the master stage circuit. An emitter of the other input side differential transistor pair forming the master stage circuit is connected to the emitter, and the emitter of the other transistor of the first input side differential transistor pair forming the master stage circuit is shared by one and the other transistors of the second output side differential transistor pair forming the master stage circuit. The emitter of one of the second input-side differential transistor pair forming the slave stage circuit is connected to the emitter, and the emitter of one of the third output-side differential transistor pair forming the slave stage circuit is shared by the other transistor. The other transistor of the second input-side differential transistor pair connected to the emitter and forming the slave stage circuit. The emitter of Njisuta connected to the common emitter of the one and the other transistor of the fourth output-side differential transistor pair constituting the slave stage circuit.

According to this configuration, the frequency of the input clock signal can be divided even at a low voltage. The reason is as follows. That is, as compared with the conventional example, the respective transistors of the first and second input-side differential transistor pairs for inputting a clock signal are replaced with the first, second, third and fourth output-side differential transistor pairs. Since the circuit is changed from the vertical stack to the horizontal stack, the collector-emitter voltage of each transistor of the first and second input-side differential transistor pairs can be secured higher than in the conventional example.

Therefore, when the same collector-emitter voltage is used, the potential difference between the first and second power supply nodes can be set smaller than in the conventional example. As an operation, in the conventional example, the magnitude of the current flowing through the transistor of the first input-side differential transistor pair or the transistor of the second input-side differential transistor pair in response to the complementary clock signal from the pair of toggle input terminals. In contrast, according to the present invention, a current flowing through a pair of first and second output differential transistors of each master stage circuit in response to a complementary clock signal from a pair of toggle input terminals and a slave The magnitude of the current flowing through the third and fourth output-side differential transistor pairs of the stage circuit is controlled.

According to a second aspect of the present invention, in the frequency divider according to the first aspect, the master stage circuit includes a first input-side differential transistor pair, a first input side differential transistor pair, and a second input side differential transistor pair. A resistor, a first output-side differential transistor pair, third and fourth resistors, a second output-side differential transistor pair, and fifth and sixth resistors.

In the first input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

One end of each of the first and second resistors is connected to the emitters of one and the other of the first input-side differential transistor pair.

The first output-side differential transistor pair includes a first output-side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistor.

The third and fourth resistors are connected between the collectors of one and the other transistors of the first output differential transistor pair and the first power supply node, respectively.

The second output-side differential transistor pair includes a second
The other end of the resistor is connected to the common emitter of one and the other transistors, the collector of one and the other transistors of the first pair of differential transistors on the output side is connected to the collector of the one and the other transistors, respectively. And the bases of one and the other transistors are respectively connected to the collectors of the other and one transistors of the output-side differential transistor pair.

One end of each of the fifth and sixth resistors is connected to the emitter of one and the other of the first input-side differential transistor pair, and the other end is connected to the second power supply node. .

The slave stage circuit includes a second input-side differential transistor pair, seventh and eighth resistors, a third output-side differential transistor pair, ninth and tenth resistors, It comprises a fourth output-side differential transistor pair and eleventh and twelfth resistors.

In the second input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

One end of each of the seventh and eighth resistors is connected to the emitters of one and the other of the second input-side differential transistor pair.

The third output side differential transistor pair includes a seventh output side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistor.

The ninth and tenth resistors are respectively connected between the collectors of one and the other transistors of the third output differential transistor pair and the first power supply node.

The fourth output-side differential transistor pair includes an eighth output-side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistors, the collector of one and the other transistors of the third pair of differential transistors on the output side is connected to the collector of the one and the other transistors, respectively. And the bases of one and the other transistors are respectively connected to the collectors of the other and one transistors of the output-side differential transistor pair.

One end of each of the eleventh and twelfth resistors is connected to the emitter of one and the other of the second input-side differential transistor pair, and the other end is connected to the second power supply node. .

The first feedback wiring connects the collectors of one and the other transistors of the third output-side differential transistor pair to the bases of one and the other transistors of the first output-side differential transistor pair, respectively. I do.

Further, the second feedback wiring connects the collectors of one and the other transistors of the first output-side differential transistor pair to the bases of the other and one of the third output-side differential transistor pairs, respectively. I do.

According to this configuration, when the potential difference between the first and second power supply nodes is, for example, 1 V, the potential difference between the fifth, sixth, eleventh, and twelfth resistors is about 0.2 V,
1st, 2nd, 3rd, 4th, 7th, 8th, 9th and 1st
When the potential difference of the resistor 0 is about 0.1 V, it is possible to secure about 0.8 V as the collector-emitter voltage of each transistor of the first and second input-side differential transistor pairs. Further, about 0.6 V can be secured as the collector-emitter voltage of each transistor of the first, second, third and fourth output-side differential transistor pairs, and operation at a low voltage is possible.

According to a third aspect of the present invention, in the frequency divider according to the first aspect, the master stage circuit comprises a first input-side differential transistor pair and a first output-side differential transistor. It comprises a moving transistor pair, first and second resistors, a second output-side differential transistor pair, and third and fourth resistors.

In the first input-side differential transistor pair, a complementary clock signal is input to the bases of one and the other transistors, respectively.

The first output-side differential transistor pair includes a first output-side differential transistor pair.
The common emitter of one and the other transistor is connected to the emitter of one of the pair of input-side differential transistors.

The first and second resistors are respectively connected between the collectors of one and the other transistors of the first output differential transistor pair and the first power supply node.

The second output-side differential transistor pair includes the first output-side differential transistor pair.
The common emitters of one and the other transistors are connected to the emitters of the other transistors of the pair of input side differential transistors, and the collectors of the one and the other transistors are connected to the collectors of the one and other transistors of the first pair of output side differential transistors. Collectors are respectively connected, and the bases of the one and the other transistors are respectively connected to the collectors of the other and the one transistors of the first output-side differential transistor pair.

One end of each of the third and fourth resistors is connected to the emitter of one and the other transistor of the first input-side differential transistor pair, and the other end is connected to the second power supply node. .

Further, the slave stage circuit comprises a second input-side differential transistor pair, a third output-side differential transistor pair, fifth and sixth resistors, and a fourth output-side differential transistor pair. And the seventh and eighth resistors.

In the second input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

The third output-side differential transistor pair includes the second output-side differential transistor pair.
The common emitter of one and the other transistor is connected to the emitter of one of the pair of input-side differential transistors.

The fifth and sixth resistors are respectively connected between the collectors of one and the other transistors of the third output differential transistor pair and the first power supply node.

The fourth output-side differential transistor pair includes the second output-side differential transistor pair.
The common emitter of one and the other transistors is connected to the emitter of the other transistor of the input-side differential transistor pair, and the collectors of the one and the other transistors are connected to the collectors of the one and the other transistors of the third output-side differential transistor pair. The collectors are respectively connected, and the bases of the one and the other transistors are respectively connected to the collectors of the other and the one transistors of the third output-side differential transistor pair.

One end of each of the seventh and eighth resistors is connected to the emitters of one and the other of the second input-side differential transistor pair, and the other end is connected to the second power supply node. .

The first feedback wiring connects the collectors of one and the other transistors of the third output-side differential transistor pair to the bases of one and the other transistors of the first output-side differential transistor pair, respectively. I do.

Further, the second feedback wiring connects the collectors of one and the other transistors of the first output differential transistor pair to the base of the other and one transistor of the third output differential transistor pair, respectively. I do.

According to this structure, when the potential difference between the first and second power supply nodes is, for example, 1 V, the potential difference between both ends of the third, fourth, seventh, and eighth resistors can be obtained. Is about 0.2 V, it is possible to secure about 0.8 V as a collector-emitter voltage of each transistor of the first and second input-side differential transistor pairs. Further, assuming that the potential difference between the first, second, fifth and sixth resistors is 0.1 V, the potential difference between the collector and the emitter of each of the first, second, third and fourth output side differential transistor pairs is assumed. A voltage of about 0.7 V can be secured. Therefore, 1V
Operation at a low voltage is possible.

According to a fourth aspect of the present invention, in the frequency divider according to the first aspect, the master stage circuit includes a first input-side differential transistor pair and a first and a second input-side differential transistor pair. It comprises a resistor, a first output-side differential transistor pair, third and fourth resistors, a second output-side differential transistor pair, and first and second current sources.

In the first input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

One end of each of the first and second resistors is connected to the emitter of one and the other of the first input-side differential transistor pair.

The first output-side differential transistor pair includes a first
The other end of the resistor is connected to the common emitter of one and the other transistor.

The third and fourth resistors are respectively connected between the collectors of one and the other transistors of the first output-side differential transistor pair and the first power supply node.

The second output-side differential transistor pair includes a second output-side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistors, the collector of one and the other transistors of the first pair of differential transistors on the output side is connected to the collector of the one and the other transistors, respectively. And the bases of one and the other transistors are respectively connected to the collectors of the other and one transistors of the output-side differential transistor pair.

Each of the first and second current sources has one end connected to the emitter of one and the other transistor of the first input-side differential transistor pair, and the other end commonly connected to the second power supply node. I have.

Further, the slave stage circuit comprises a second input-side differential transistor pair, fifth and sixth resistors, a third output-side differential transistor pair, seventh and eighth resistors, It comprises a fourth output-side differential transistor pair, and third and fourth current sources.

In the second input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

One end of each of the fifth and sixth resistors is connected to the emitter of one and the other of the second input-side differential transistor pair.

The third output-side differential transistor pair includes the fifth output-side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistor.

The seventh and eighth resistors are respectively connected between the collectors of one and the other transistors of the third output differential transistor pair and the first power supply node.

The fourth output side differential transistor pair is the sixth output side differential transistor pair.
The other end of the resistor is connected to the common emitter of one and the other transistors, the collector of one and the other transistors of the third pair of differential transistors on the output side is connected to the collector of the one and the other transistors, respectively. And the bases of one and the other transistors are respectively connected to the collectors of the other and one transistors of the output-side differential transistor pair.

The third and fourth current sources have one ends connected to the emitters of one and the other transistors of the second input-side differential transistor pair, respectively, and the other ends commonly connected to the second power supply node. I have.

The first feedback wiring connects the collectors of one and the other transistors of the third output-side differential transistor pair to the bases of one and the other transistors of the first output-side differential transistor pair, respectively. I do.

Further, the second feedback wiring connects the collectors of one and the other transistors of the first output-side differential transistor pair to the bases of the other and one of the third output-side differential transistor pairs, respectively. I do.

According to this configuration, the potential difference between the third, fourth, seventh, and eighth resistors is set to 0.
Assuming that the potential difference between the first, second, third and fourth current sources is about 0.3 V which is the same as that of the conventional example, that is, about 1 V, between the collector and emitter of each transistor of the first and second input-side differential transistor pairs. 0.7V can be secured as the voltage. Also,
The potential difference between the first, second, fifth and sixth resistors is set to 0.1 V
Then, 0.5 V can be secured as the collector-emitter voltage of each transistor of the first, second, third, and fourth output-side differential transistor pairs, so that the potential difference between the first and second power supply nodes is 1 V Operation is possible with as little as possible.

According to a fifth aspect of the present invention, in the frequency divider according to the first aspect, the master stage circuit comprises a first input side differential transistor pair and a first output side differential transistor. An active transistor pair, first and second resistors, a second output-side differential transistor pair, and first and second current sources.

In the first input-side differential transistor pair, complementary clock signals are input to the bases of one and the other transistors, respectively.

The first output-side differential transistor pair includes a first output-side differential transistor pair.
The common emitter of one and the other transistor is connected to the emitter of one of the pair of input-side differential transistors.

The first and second resistors are respectively connected between the collectors of one and the other transistors of the first output-side differential transistor pair and the first power supply node.

The second output-side differential transistor pair includes the first
The common emitters of one and the other transistors are connected to the emitters of the other transistors of the pair of input side differential transistors, and the collectors of the one and the other transistors are connected to the collectors of the one and other transistors of the first pair of output side differential transistors. Collectors are respectively connected, and the bases of the one and the other transistors are respectively connected to the collectors of the other and the one transistors of the first output-side differential transistor pair.

Each of the first and second current sources has one end connected to the emitter of one and the other transistor of the first input-side differential transistor pair, and the other end commonly connected to the second power supply node. I have.

Further, the slave stage circuit includes a second input-side differential transistor pair, a third output-side differential transistor pair, third and fourth resistors, and a fourth output-side differential transistor pair. And third and fourth current sources.

The second input-side differential transistor pair receives complementary clock signals input to the bases of one and the other transistors, respectively.

The third output-side differential transistor pair includes the second output-side differential transistor pair.
The common emitter of one and the other transistor is connected to the emitter of one of the pair of input-side differential transistors.

The third and fourth resistors are respectively connected between the collectors of one and the other transistors of the third output-side differential transistor pair and the first power supply node.

The fourth output-side differential transistor pair includes the second output-side differential transistor pair.
The common emitter of one and the other transistors is connected to the emitter of the other transistor of the input-side differential transistor pair, and the collectors of the one and the other transistors are connected to the collectors of the one and the other transistors of the third output-side differential transistor pair. The collectors are respectively connected, and the bases of the one and the other transistors are respectively connected to the collectors of the other and the one transistors of the third output-side differential transistor pair.

The third and fourth current sources have one ends connected to the emitters of one and the other transistors of the second input-side differential transistor pair, respectively, and the other ends commonly connected to the second power supply node. I have.

The first feedback wiring connects the collectors of one and the other transistors of the third output-side differential transistor pair to the bases of one and the other transistors of the first output-side differential transistor pair, respectively. I do.

The second feedback wiring connects the collectors of one and the other transistors of the first output-side differential transistor pair to the bases of the other and one of the third output-side differential transistor pairs, respectively. I do.

According to this configuration, when the potential difference between the first and second power supply nodes is set to 1 V, the potential difference between the first, second, third, and fourth current sources is set. Is 0.3 V, which is the same as that of the conventional example, about 0.7 V can be secured as the collector-emitter voltage of each of the first and second input-side differential transistor pairs. Also,
The potential difference between the first, second, third and fourth resistors is set to 0.1 V
Then, about 0.6 V can be secured as the collector-emitter voltage of each transistor of the first, second, third and fourth output-side differential transistor pairs. Therefore, 1V
Operation is possible with a potential difference as low as possible.

The frequency divider according to the present invention comprises a plurality of cascade-connected frequency dividers, and the frequency divider comprises a pair of toggle input terminals which supply a complementary clock signal to a differential input terminal. And a complementary clock signal from a pair of toggle input terminals to a differential input terminal, and a differential output to a pair of divided differential output terminals Bipolar double-differential slave stage circuit that outputs the differential output of the master stage circuit to the master stage circuit, and a slave stage circuit that outputs the differential output of the master stage circuit to the master stage circuit. And a second feedback wiring for supplying the feedback to the second feedback line.

Then, the emitter of one transistor of the first input-side differential transistor pair forming the master stage circuit is connected to one of the first and second transistors on the first output side differential transistor pair forming the master stage circuit. An emitter of the other input side differential transistor pair forming the master stage circuit is connected to the emitter, and the emitter of the other transistor of the first input side differential transistor pair forming the master stage circuit is shared by one and the other transistors of the second output side differential transistor pair forming the master stage circuit The emitter of one of the second input-side differential transistor pair forming the slave stage circuit is connected to the emitter, and the emitter of one of the third output-side differential transistor pair forming the slave stage circuit is shared by the other transistor. The other transistor of the second input-side differential transistor pair connected to the emitter and forming the slave stage circuit. The emitter of Njisuta connected to the common emitter of the one and the other transistor of the fourth output-side differential transistor pair constituting the slave stage circuit.

According to this configuration, in addition to the function of the frequency dividing circuit according to the first aspect, there is an effect that the frequency dividing ratio can be set according to the number of cascade connection stages of the frequency dividing circuit.

[0100]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram showing a frequency divider according to a first embodiment. As shown in FIG. 1, this frequency divider circuit is a bipolar double differential master stage circuit 27A in which complementary clock signals are input to a differential input terminal from a pair of toggle input terminals 1 and 2. , A complementary clock signal is input from the pair of toggle input terminals 1 and 2 to the differential input terminal, and the differential output is output to the pair of frequency-divided differential output terminals 23 and 24. -Type slave stage circuit 28A, a first feedback line 29 for feeding back the differential output of the slave stage circuit 28A to the master stage circuit 27A, and feeding back the differential output of the master stage circuit 27A to the slave stage circuit 28A. And a second return line 30.

The emitter of one transistor Q9 of the first input side differential transistor pair 3 constituting the master stage circuit 27A is connected to one of the first output side differential transistor pair 5 constituting the master stage circuit 27A. The emitter of the other transistor Q10 of the first input-side differential transistor pair 3 forming the master stage circuit 27A is connected to the common emitter of the other transistors Q1 and Q4, and the second output side forming the master stage circuit 27A. The emitter of one transistor Q11 of the second input-side differential transistor pair 4 forming the slave stage circuit 28A is connected to the common emitter of one and the other transistors Q2 and Q3 of the differential transistor pair 6 and the slave stage circuit 28A. And the other transistor Q5 of the third output-side differential transistor pair 7 The emitter of the other transistor Q12 of the second input-side differential transistor pair 4 forming the slave stage circuit 28A is connected to the common emitter of Q8 and the fourth output-side differential transistor pair 8 forming the slave stage circuit 28A. And the common emitter of the other transistors Q6 and Q7.

In this case, the master stage circuit 27A
, An input-side differential transistor pair 3, first and second resistors 9 and 10, a first output-side differential transistor pair 5,
Third and fourth resistors 11 and 12, second output differential transistor pair 6, fifth and sixth resistors 13, 14
It is composed of

The first input-side differential transistor pair 3 supplies complementary clock signals to one transistor Q and the other transistor Q.
9 and Q10, respectively.

One end of each of the first and second resistors 9 and 10 is connected to the emitters of one and the other transistors Q9 and Q10 of the first input-side differential transistor pair 3, respectively.

The first output-side differential transistor pair 5 includes one and the other transistors Q connected to the other end of the first resistor 9.
The common emitters of 1 and Q4 are connected.

The third and fourth resistors 11 and 12 are connected to the first
Of the output-side differential transistor pair 5 and the collectors of the other transistors Q1 and Q4 and the first power supply node 21
And are connected between them.

The second output-side differential transistor pair 6 includes one and the other transistors Q connected to the other end of the second resistor 10.
2 and Q3 are connected to one another and the other transistor Q of the first output-side differential transistor pair 5.
One and the other transistors Q
2 and Q3 are connected to each other, and the base of one and the other transistors Q2 and Q3 is connected to the other of the first output side differential transistor pair 5 and the collector of one of the transistors Q4 and Q1, respectively.

The fifth and sixth resistors 13 and 14 are connected to the first
One end of each of the input-side differential transistor pair 3 and the emitter of the other transistor Q9, Q10 is connected to one end, and the other end is connected to the second power supply node 22.

Further, the slave stage circuit 28A includes the second input-side differential transistor pair 4 and the seventh and eighth resistors 1
5, 16, a third output-side differential transistor pair 7, ninth and tenth resistors 17, 18, a fourth output-side differential transistor pair 8, and eleventh and twelfth resistors 19,
20.

The second input-side differential transistor pair 4 supplies complementary clock signals to one transistor Q and the other transistor Q.
11 and Q12.

The seventh and eighth resistors 15, 16 are connected to the second
One end of each of the input-side differential transistor pair 4 and the emitters of the other transistors Q11 and Q12 are connected.

The third output-side differential transistor pair 7 includes one and the other transistor Q connected to the other end of the seventh resistor 15.
5, Q8 common emitters are connected.

The ninth and tenth resistors 17 and 18 are connected to the collectors of one and the other transistors Q5 and Q8 of the third output-side differential transistor pair 7 and the first power supply node 2 respectively.
1 respectively.

The fourth output-side differential transistor pair 8 includes one and the other transistor Q connected to the other end of the eighth resistor 16.
6 and Q7 are connected to one another and the other transistor Q of the third output-side differential transistor pair 7.
5 and Q8 are connected to one and the other transistor Q
6 and Q7 are connected to each other, and the bases of one and the other transistors Q6 and Q7 are connected to the other of the third output-side differential transistor pair 7 and the collectors of the transistors Q8 and Q5, respectively.

The eleventh and twelfth resistors 19 and 20 are:
One end of each of the transistors Q11 and Q12 of the second input-side differential transistor pair 4 is connected to the emitter of the other transistor Q11, and the other end is connected to the second power supply node 22.

The first feedback wiring 29 connects the collectors of one and the other transistors Q5 and Q8 of the third output-side differential transistor pair 7 to one and the other of the first output-side differential transistor pair 5. Connected to the bases of transistors Q1 and Q4, respectively.

The second feedback wiring 30 connects the collectors of one and the other transistors Q1 and Q4 of the first output-side differential transistor pair 5 to the other and one of the third output-side differential transistor pair 7. Connected to the bases of transistors Q8 and Q5, respectively.

In the circuit configuration of FIG. 1, the first resistor 9, the second resistor 10, the seventh resistor 15, and the eighth resistor 16
Have the same resistance value, and the third resistor 11 and the fourth resistor 12
, The ninth resistor 17 and the tenth resistor 18 have the same resistance value, and the fifth resistor 13, the sixth resistor 14, and the eleventh resistor 1
The ninth and twelfth resistors 20 have the same resistance value.

The operation of the above configuration will be described below. The operation of the frequency divider configured as above will be described. This frequency divider circuit has four transition states, the voltage values input to the toggle input terminals (T, / T) 1 and 2 are V1 and V2, respectively, and the transistors Q1 to Q2
In 12, a first output-side differential transistor pair formed of a transistor Q1 and a transistor Q4, a second output-side differential transistor pair formed of a transistor Q2 and a transistor Q3, a transistor Q5 and a transistor Q8 are formed. Third output-side differential transistor pair 7, transistor Q6 and transistor Q7, fourth output-side differential transistor pair 8, and transistor Q9
Input-side differential transistor pair 3, transistor Q11 and transistor Q
12 of the second input-side differential transistor pair 4 composed of 12 is turned on,
Assuming that a transistor having a smaller current is represented as OFF, first, in a first transition state (V1> V2), the transistor Q1 is OFF, the transistor Q2 is ON, the transistor Q3 is OFF, the transistor Q4 is OFF, and the transistor Q5 is ON, transistor Q6 is OFF, transistor Q7 is OFF, transistor Q8 is OFF, transistor Q9 is OFF, transistor Q10 is ON,
Transistor Q11 is ON, transistor Q12 is OF
It becomes F.

Next, in the second transition state (V1 <V2), the transistor Q1 is off and the transistor Q2 is off.
FF, transistor Q3 is OFF, transistor Q4 is ON, transistor Q5 is OFF, transistor Q6 is ON, transistor Q7 is OFF, transistor Q8 is OFF, transistor Q9 is ON, transistor Q10
Is OFF, the transistor Q11 is OFF, and the transistor Q12 is ON.

Next, in the third transition state (V1> V2), the transistor Q1 is OFF and the transistor Q2 is OFF.
FF, transistor Q3 is ON, transistor Q4 is O
FF, transistor Q5 is OFF, transistor Q6 is OFF, transistor Q7 is OFF, transistor Q8
Is ON, transistor Q9 is OFF, transistor Q1
0 is ON, transistor Q11 is ON, transistor Q
12 is OFF.

Next, in the fourth transition state (V1 <V2), the transistor Q1 is ON and the transistor Q2 is OFF.
F, transistor Q3 is OFF, transistor Q4 is O
FF, transistor Q5 is OFF, transistor Q6 is OFF, transistor Q7 is ON, transistor Q8 is OFF, transistor Q9 is ON, transistor Q10
Is OFF, the transistor Q11 is OFF, and the transistor Q12 is ON.

Each time the states of V1 and V2 are inverted, the above transition state is repeated.

The frequency-divided differential output terminals (Q,
/ Q) Assuming that the voltages of 23 and 24 are V23 and V24, respectively, V23> V24 in the first transition state, V23> V24 in the second transition state, and V23 <V24 in the third transition state, V4 in the fourth transition state
3 <V24.

The voltage values V1, V2 input to the toggle input terminals (T, / T) 1, 2 and the divided differential output terminals (Q, / T)
Q) The relationship between the voltages V23 and V24 of 23 and 24 is the same as that shown in FIG.

By the above operation, the frequency dividing circuit divides the frequency of the clock signal input to the toggle input terminals 1 and 2 by 、, and the divided frequency signals from the divided output terminals 23 and 24 are in opposite phase relation to each other. A pair of divided waveforms will be output.
That is, a frequency divider that divides the clock signal by ク ロ ッ ク can be realized. In this embodiment, the frequency dividing operation is possible in a range up to about 1V.

Here, the reason why the frequency dividing operation is possible in a range up to about 1 V will be described. Transistors Q1-
This is because about 1 V can be used to secure the collector-emitter voltage of Q8 and the transistors Q9 to Q12 at 0.5V or more. Since the voltage between the base and the emitter is different depending on the process, there is a process that can be performed at 0.9 V, a process at 1.1 V, and the process is not limited to 1 V.

According to the frequency divider of this embodiment, it is possible to divide the input clock signal even at a low voltage. The reason is as follows. That is, as compared with the conventional example, each of the transistors Q9 to Q9 of the first and second input-side differential transistor pairs 3 and 4 for inputting a clock signal is used.
12 is changed from a vertical stack to a horizontal stack for the first, second, third and fourth output-side differential transistor pairs 5, 6, 7, and 8, so that the first and second input sides are changed. The collector-emitter voltage of each of the transistors Q9 to Q12 of the differential transistor pairs 3 and 4 can be secured higher than in the conventional example.

Therefore, when the same collector-emitter voltage is used, the potential difference between the first and second power supply nodes 21 and 22 can be set smaller than in the conventional example. In operation, in the conventional example, the transistors Q9 and Q10 of the first input-side differential transistor pair 3 or the second transistors Q9 and Q10 according to the voltages V1 and V2 applied as complementary clock signals from the pair of toggle input terminals 1 and 2 respectively. Control the magnitude of the current flowing through the transistors Q11 and Q12 of the input-side differential transistor pair 4 of the present invention, whereas in the present invention, the voltage V1 applied as a complementary clock signal from the pair of toggle input terminals 1 and 2 is controlled. , V2, each master stage circuit 27A-27.
D first and second output-side differential transistor pairs 5, 6
To the third stage of the slave stage circuits 28A to 28D.
And the magnitude of the current flowing through the fourth output-side differential transistor pair 7, 8 is controlled.

Further, according to this configuration, the first and second
If the potential difference between the power supply nodes 21 and 22 is 1 V, the fifth, sixth, eleventh, and twelfth resistors 13, 14, 1
The potential difference between the first and second resistors 9 and 20 is about 0.2 V, and the first, second, third, fourth, seventh, eighth, ninth, and tenth resistors 9.1
When the potential difference between 0, 11, 12, 15, 16, 17, and 18 is about 0.1 V, the collector-emitter voltage of each of the transistors Q9 to Q12 of the first and second input-side differential transistor pairs 3 and 4 is set. 0.8V as the first and
Second, third and fourth output-side differential transistor pairs 5,
About 0.6 V can be secured as the collector-emitter voltage of each of the transistors Q1 to Q8 of 6, 7, and 8, respectively.
Operation at low voltage becomes possible.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. In this embodiment,
From the master stage circuit 27A and the slave stage circuit 28A in the frequency divider circuit of FIG.
16 is omitted, or a master stage circuit 27B and a slave stage circuit 28B in which the resistance values of the resistors 9, 10, 15, and 16 are replaced with 0 ohms are used, and other configurations are the same as those in FIG. .

The operation of this embodiment is basically the first operation.
This is the same as the embodiment. The difference is the resistance 9,10,1
By deleting the transistors 5 and 16, the transistors Q1 to Q
8 is that a large collector-emitter voltage can be obtained. Further, the resistors corresponding to the deleted portions are replaced with the resistors 11, 12, 1
7 and 18, the resistances 11, 12, 17, and 17 are set at the same collector-emitter voltage as in the first embodiment.
The potential difference between both ends of the 18 becomes large, and as a result, the sensitivity of frequency division is improved.

According to this configuration, as in the first embodiment, when the potential difference between the first and second power supply nodes 21 and 22 is 1 V, the potential difference between both ends of the resistors 13, 14, 19 and 20 is set. Is about 0.2 V, the transistors Q9 to Q4 of the first and second input-side differential transistor pairs 3 and 4
About 0.8 V can be secured as the collector-emitter voltage of Q12. If the potential difference between the resistors 11, 12, 17, and 18 is 0.1 V, the first, second, third, and fourth
About 0.7 V as the collector-emitter voltage of each of the transistors Q1 to Q8 of the output-side differential transistor pair 5, 6, 7, and 8. Therefore, operation at a low voltage of about 1 V is possible.

[Third Embodiment] A third embodiment of the present invention will be described with reference to FIG. In this embodiment,
The resistors 13 and 14 of the master stage circuit 27A in the frequency divider of FIG. 1 are connected to the first and second current sources 25A and 25A.
B and the resistors 19 and 20 of the slave stage circuit 28A and the third and fourth current sources 2C and 27C, respectively.
6A and 26B, and the other configuration is the same as that of the frequency dividing circuit of FIG.

The operation of this embodiment is basically the first operation.
This embodiment is the same as the above-described embodiment, except that the method of determining the current of the circuit is different. In the first embodiment, the current of the entire circuit is determined by the base-emitter voltages of the transistors Q1 to Q8 and Q9 and Q10, but in the third embodiment, it becomes a fixed current. However, transistors Q1-
The value of the current flowing to the Q8 side and the value of the current flowing to the transistors Q9 to Q12 can be changed by the resistance values of the resistors 11 and 12.

According to this configuration, similarly to the first and second embodiments, the potential difference between the resistors 9, 10, 15, and 16 is set to about 0.1 V, and the first, second, third, and fourth Current source 2
Assuming that the potential difference between 5A, 25B, 26A, and 26B is 0.3 V, which is the same as that of the conventional example, the collector-emitter voltage of each of the transistors Q9 to Q12 of the first and second input-side differential transistor pairs 3 and 4 is 0. 7V can be secured. Further, assuming that the potential difference between the resistors 11, 12, 17, and 18 is 0.1 V, each of the transistors Q1 to Q8 of the first, second, third, and fourth output-side differential transistor pairs 5, 6, 7, and 8
Can be secured even if the potential difference between the first and second power supply nodes 21 and 22 is as small as about 1 V.

[Fourth Embodiment] A fourth embodiment of the present invention will be described with reference to FIG. In this embodiment,
The resistors 13 and 14 of the master stage circuit 27B in the frequency divider of FIG. 2 are connected to the first and second current sources 25A and 25A.
B and the resistors 19 and 20 of the slave stage circuit 28B and the third and fourth current sources 2
6A and 26B, and the other configuration is the same as that of the frequency divider circuit of FIG.

The operation of this embodiment is basically the first
This is the same as the third to third embodiments. Compared to the third embodiment, only the resistors 9 and 10 and the resistors 15 and 16 are omitted.
The operation is the same as the difference between the first and second embodiments. Also, the method of determining the current is different.
The difference is the same as that of the third embodiment.

According to this configuration, similarly to the first, second, and third embodiments, the first and second power supply nodes 21,
When the potential difference between the first and second current sources 25A, 25B, 26A, and 26B is 0.3 V, which is the same as that of the conventional example, when the potential difference of the second input terminal 22 is 1 V, the first and second inputs are provided. Each transistor Q9 of the pair of side differential transistors 3, 4
0.7V can be secured as the collector-emitter voltage of Q12. Further, assuming that the potential difference between the resistors 11, 12, 17, and 18 is 0.1 V, each of the transistors Q1 to Q8 of the first, second, third, and fourth output-side differential transistor pairs 5, 6, 7, and 8 0.6 as collector-emitter voltage of
V can be secured. Therefore, operation is possible even with a potential difference as low as about 1 V.

[Fifth Embodiment] In a frequency dividing apparatus constructed by cascade-connecting the frequency dividing circuits shown in FIGS. 1 to 4 to, for example, n stages (n is an integer of 2 or more), A waveform whose frequency is divided by 1/2 to the power of n is obtained from the output terminal.

According to the frequency dividing device of this embodiment, in addition to the effects of the frequency dividing circuits of the first to fourth embodiments, the dividing ratio can be adjusted according to the number of cascade-connected stages of the frequency dividing circuit. The effect of being able to set is produced.

[0143]

According to the frequency divider of the present invention, the emitter of one transistor of the first pair of differential transistors on the input side constituting the master stage circuit is connected to the first output side difference constituting the master stage circuit. Connected to the common emitter of the active transistor pair, and the emitter of the other transistor of the first input side differential transistor pair forming the master stage circuit is connected to the common emitter of the second output side differential transistor pair forming the master stage circuit. Connected to the common emitter of the third output differential transistor pair forming the slave stage circuit, and connecting the emitter of one transistor of the second input side differential transistor pair forming the slave stage circuit to the slave stage. The emitter of the other transistor of the second input side differential transistor pair forming the circuit is connected to the fourth output side differential transistor forming the slave stage circuit. Having connected to the common emitter of Njisuta pairs, it is possible to divide the input clock signal inputted at a low voltage to the toggle input terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a frequency divider according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a frequency divider according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a frequency divider according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a frequency divider according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional frequency divider.

FIG. 6 is an operation waveform diagram according to the embodiment of the present invention and a conventional example.

[Explanation of symbols]

Reference Signs List 1 toggle input terminal 2 toggle input terminal 3 first input side differential transistor pair 4 second input side differential transistor pair 5 first output side differential transistor pair 6 second output side differential transistor pair 7th 3 output side differential transistor pair 8 4th output side differential transistor pair 9 1st resistance 10 2nd resistance 11 3rd resistance 12 4th resistance 13 5th resistance 14 6th resistance 15th 7 resistor 16 8th resistor 17 9th resistor 18 10th resistor 19 11th resistor 20 12th resistor 21 1st power supply node 22 2nd power supply node 23 differential frequency division output terminal 24 differential Frequency dividing output terminal 25, 25A, 25B First constant current source 26, 26A, 26B Second constant current source 27A, 27B, 27C, 27D, 27E Master stage circuit 28A, 28B, 28C, 28D, 2 E slave stage circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Kurashina 1006 Kazuma Kadoma, Osaka Pref.Matsushita Electric Industrial Co., Ltd.

Claims (6)

[Claims] A bipolar double differential master stage circuit (27A to 27A) in which a complementary clock signal is input to a differential input terminal from a pair of toggle input terminals (1, 2).
D), the complementary clock signal is input to the differential input terminal from the pair of toggle input terminals (1, 2), and the differential output is output to the pair of frequency-divided differential output terminals (23, 24). Bipolar double differential slave stage circuit (28A
To 28D) and the slave stage circuit (28A to 28D)
A first feedback wiring (29) for feeding the differential output of the master stage circuit (27A to 27D) back to the master stage circuit (27A to 27D), and the differential output of the master stage circuit (27A to 27D) to the slave stage circuit (28A to 28D). ) And a second feedback wiring (30) for feeding back to the master stage circuit (27A to 27D).
The emitter of one transistor (Q9) of the input-side differential transistor pair (3) is connected to the master stage circuit (27A to
27D) One and the other transistors (Q1, Q4) of the first output differential transistor pair (5) constituting
Of the master stage circuit (27A
27D), the emitter of the other transistor (Q10) of the first pair of input-side differential transistors (3) is connected to the second pair of output-side differential transistors (27A to 27D) of the master stage circuit (27A to 27D). 6) is connected to the common emitter of one and the other transistors (Q2, Q3) and constitutes the slave stage circuit (28A to 28D). ) Is connected to the slave stage circuit (28A to 28A).
28D), one and the other transistors (Q5, Q8) of the third output differential transistor pair (7)
Of the slave stage circuit (28A
To the second input-side differential transistor pair (4) constituting the slave stage circuit (28A to 28D). 8) A frequency divider circuit connected to a common emitter of one and the other transistors (Q6, Q7). 2. The master stage circuit (27A) supplies complementary clock signals to one and the other transistors (Q9, Q9).
A first input-side differential transistor pair (3) input to the base of Q10), and an emitter of one and the other transistors (Q9, Q10) of the first input-side differential transistor pair (3). First and second resistors (9, 1
0), and the other end of the first resistor (9) is connected to a common emitter of one and the other transistors (Q1, Q4).
And the collectors of one and the other transistors (Q1, Q4) of the first output-side differential transistor pair (5) and the first differential transistor pair (5).
Connected to the power supply node (21) of the
A common emitter of one and the other transistor (Q2, Q3) is connected to the other end of the second resistor (10), and the first output differential transistor is connected to the other end of the second resistor (10). The collectors of one and the other transistors (Q2, Q3) are respectively connected to the collectors of the one and the other transistors (Q1, Q4) of the pair (5), and the other of the first output-side differential transistor pair (5). And one of the transistors (Q4, Q1)
And the other transistor (Q2, Q2)
3) a second output-side differential transistor pair (6) to which the bases are respectively connected, and an emitter of one and the other transistors (Q9, Q10) of the first input-side differential transistor pair (3). Fifth and sixth resistors (13, 13) each having one end connected thereto and the other end connected to the second power supply node (22), respectively.
14), wherein the slave stage circuit (28A) outputs the complementary clock signal to one and the other transistor (Q11, Q12).
A second input-side differential transistor pair (4) respectively input to the bases of the first and second input-side differential transistor pairs (4); Are connected to the seventh and eighth resistors (1
A third output differential transistor pair (7) in which the other end of the seventh resistor (15) is connected to a common emitter of one and the other transistor (Q5, Q8); Ninth and tenth resistors connected between the collectors of one and the other transistors (Q5, Q8) of the third output-side differential transistor pair (7) and the first power supply node (21), respectively. (17, 18), the other end of the eighth resistor (16) is connected to the common emitter of one and the other transistor (Q6, Q7), and the third output differential transistor pair (7) The collectors of one and the other transistors (Q6, Q7) are connected to the collectors of the one and the other transistors (Q5, Q8), respectively, and the other and one of the third output-side differential transistor pair (7) are connected. Transistor (Q8, Q5)
And the other transistor (Q6, Q6)
7) to the fourth output-side differential transistor pair (8) to which the bases are respectively connected, and to the emitters of one and the other transistors (Q11, Q12) of the second input-side differential transistor pair (4). One end is connected to each of the second power supply nodes (2
The second output transistor (29) is composed of eleventh and twelfth resistors (19, 20), the other ends of which are connected to the second differential transistor pair (7), respectively. One and the other transistors (Q
, Q8) is connected to one and the other transistors (Q1, Q1) of the first output differential transistor pair (5).
Q4) and the second feedback wiring (3
0) connects the collectors of one and the other transistors (Q1, Q4) of the first output side differential transistor pair (5) to the other and one transistor of the third output side differential transistor pair (7). 2. The frequency divider according to claim 1, wherein the frequency divider is connected to the bases of (Q8, Q5). 3. The master stage circuit (27B) supplies a complementary clock signal to one and the other transistor (Q9,
A first input-side differential transistor pair (3) input to the base of the first input-side differential transistor pair (3), and an emitter of one transistor (Q9) of the first input-side differential transistor pair (3). A first output differential transistor pair (5) to which a common emitter of the transistors (Q1, Q4) is connected; one and the other transistor (Q1, Q4) of the first output differential transistor pair (5); ) Collector and 1st
Connected to the power supply node (21) of the
And the second resistor (11, 12), and the common emitter of one and the other transistors (Q2, Q3) is connected to the emitter of the other transistor (Q10) of the first input-side differential transistor pair (3). And
The collectors of one and the other transistors (Q2, Q3) are respectively connected to the collectors of one and the other transistors (Q1, Q4) of the first output-side differential transistor pair (5), and the first output side The other and one transistors (Q4, Q4) of the differential transistor pair (5)
1) and the other transistor (Q
2, Q3) to which the bases are respectively connected, a second output-side differential transistor pair (6), and one of the first input-side differential transistor pair (3) and the other transistor (Q9, Q10). A third resistor (13, 4) having one end connected to the emitter and the other end connected to the second power supply node (22), respectively.
14), wherein the slave stage circuit (28B) outputs the complementary clock signal to one and the other transistor (Q11, Q12).
And a second input-side differential transistor pair (4) respectively input to the bases of the first and second transistors (Q11) of the second input-side differential transistor pair (4). A third output-side differential transistor pair (7) to which a common emitter of the third output-side differential transistor pair (7) is connected, and one of the third output-side differential transistor pair (7) and the other transistor (Q5, Q8). Fifth and sixth resistors (17, 18) respectively connected between a collector and the first power supply node (21), and the other transistor of the second input-side differential transistor pair (4) The common emitter of one and the other transistors (Q6, Q7) is connected to the emitter of (Q12),
The collectors of one and the other transistors (Q6, Q7) are respectively connected to the collectors of one and the other transistors (Q5, Q8) of the third output-side differential transistor pair (7), and the third output side The other and one transistors (Q8, Q8) of the differential transistor pair (7)
5) to the collector of one and the other transistor (Q
6, Q7) and a fourth output-side differential transistor pair (8) to which the bases are respectively connected, and one and the other transistors (Q11, Q12) of the second input-side differential transistor pair (4). One end is connected to each of the emitters, and the second power supply node (2
And a seventh feedback resistor (19, 20) having the other end connected to 2), and a first feedback wiring (29) is connected to the third output differential transistor pair (7). One and the other transistors (Q
, Q8) is connected to one and the other transistor (Q1, Q1) of the first output differential transistor pair (5).
Q4) and the second feedback wiring (3
0) connects the collectors of one and the other transistors (Q1, Q4) of the first output differential transistor pair (5) to the other and one transistor of the third output differential transistor pair (7). 2. The frequency divider according to claim 1, wherein the frequency divider is connected to the bases of (Q8, Q5). 4. The master stage circuit (27C) supplies complementary clock signals to one and the other transistors (Q9, Q9).
A first input-side differential transistor pair (3) input to the base of Q10), and an emitter of one and the other transistors (Q9, Q10) of the first input-side differential transistor pair (3). First and second resistors (9, 1
0), and the other end of the first resistor (9) is connected to a common emitter of one and the other transistors (Q1, Q4).
And the collectors of one and the other transistors (Q1, Q4) of the first output-side differential transistor pair (5) and the first differential transistor pair (5).
Connected to the power supply node (21) of the
A common emitter of one and the other transistor (Q2, Q3) is connected to the other end of the second resistor (10), and the first output differential transistor is connected to the other end of the second resistor (10). The collectors of one and the other transistors (Q2, Q3) are respectively connected to the collectors of the one and the other transistors (Q1, Q4) of the pair (5), and the other of the first output-side differential transistor pair (5). And one of the transistors (Q4, Q1)
And the other transistor (Q2, Q2)
3) a second output-side differential transistor pair (6) to which the bases are respectively connected, and an emitter of one and the other transistors (Q9, Q10) of the first input-side differential transistor pair (3). First and second current sources (25A, 25A, one end of which are connected to each other and the other end of which is commonly connected to a second power supply node (22)).
25B), and the slave stage circuit (28C) outputs the complementary clock signal to one and the other transistors (Q11, Q12).
A second input-side differential transistor pair (4) respectively input to the bases of the first and second input-side differential transistor pairs (4); Connected to the fifth and sixth resistors (1
A third output-side differential transistor pair (7) in which the common emitters of one and the other transistors (Q5, Q8) are connected to the other end of the fifth resistor (15); Seventh and eighth resistors connected between the collectors of one and the other transistors (Q5, Q8) of the third output-side differential transistor pair (7) and the first power supply node (21), respectively. (17, 18), the other end of the sixth resistor (16) is connected to the common emitter of one and the other transistors (Q6, Q7), and the third output differential transistor pair (7) The collectors of one and the other transistors (Q6, Q7) are connected to the collectors of the one and the other transistors (Q5, Q8), respectively, and the other and one of the third output differential transistor pair (7) are connected. Transistors (Q8, Q5)
And the other transistor (Q6, Q6)
7) to the fourth output-side differential transistor pair (8) to which the bases are respectively connected, and to the emitters of one and the other transistors (Q11, Q12) of the second input-side differential transistor pair (4). One end is connected to each of the second power supply nodes (2
2) and third and fourth current sources (26A, 26B) whose other ends are connected in common. The first feedback wiring (29) is connected to the third output differential transistor pair (7). ) And the other transistor (Q
, Q8) is connected to one and the other transistor (Q1, Q1) of the first output differential transistor pair (5).
Q4) and the second feedback wiring (3
0) connects the collectors of one and the other transistors (Q1, Q4) of the first output differential transistor pair (5) to the other and one transistor of the third output differential transistor pair (7). 2. The frequency divider according to claim 1, wherein the frequency divider is connected to the bases of (Q8, Q5). 5. The master stage circuit (27D) supplies complementary clock signals to one and the other transistors (Q9, Q9).
A first input-side differential transistor pair (3) input to the base of the first input-side differential transistor pair (3), and an emitter of one transistor (Q9) of the first input-side differential transistor pair (3). A first output differential transistor pair (5) to which a common emitter of the transistors (Q1, Q4) is connected; one and the other transistor (Q1, Q4) of the first output differential transistor pair (5); ) Collector and 1st
Connected to the power supply node (21) of the
And the second resistor (11, 12), and the common emitter of one and the other transistors (Q2, Q3) is connected to the emitter of the other transistor (Q10) of the first input-side differential transistor pair (3). And
The collectors of one and the other transistors (Q2, Q3) are respectively connected to the collectors of one and the other transistors (Q1, Q4) of the first output-side differential transistor pair (5), and the first output side The other and one transistors (Q4, Q4) of the differential transistor pair (5)
1) and the other transistor (Q
2, Q3) to which the bases are respectively connected, a second output-side differential transistor pair (6), and one of the first input-side differential transistor pair (3) and the other transistor (Q9, Q10). The first and second current sources (25A, 25A, one end of which are respectively connected to the emitter and the other end of which is commonly connected to the second power supply node (22)).
25B), and the slave stage circuit (28D) outputs the complementary clock signal to one and the other transistor (Q11, Q12).
And a second input-side differential transistor pair (4) respectively input to the bases of the first and second transistors (Q11) of the second input-side differential transistor pair (4). A third output-side differential transistor pair (7) to which a common emitter of the third output-side differential transistor pair (7) is connected, and one of the third output-side differential transistor pair (7) and the other transistor (Q5, Q8). Third and fourth resistors (17, 18) respectively connected between a collector and the first power supply node (21), and the other transistor of the second input-side differential transistor pair (4) The common emitter of one and the other transistors (Q6, Q7) is connected to the emitter of (Q12),
The collectors of one and the other transistors (Q6, Q7) are respectively connected to the collectors of one and the other transistors (Q5, Q8) of the third output-side differential transistor pair (7), and the third output side The other and one transistors (Q8, Q8) of the differential transistor pair (7)
5) to the collector of one and the other transistor (Q
6, Q7) and a fourth output-side differential transistor pair (8) to which the bases are respectively connected, and one and the other transistors (Q11, Q12) of the second input-side differential transistor pair (4). One end is connected to each of the emitters, and the second power supply node (2
2) and third and fourth current sources (26A, 26B) whose other ends are connected in common. The first feedback wiring (29) is connected to the third output differential transistor pair (7). ) And the other transistor (Q
, Q8) is connected to one and the other transistor (Q1, Q1) of the first output differential transistor pair (5).
Q4) and the second feedback wiring (3
0) connects the collectors of one and the other transistors (Q1, Q4) of the first output side differential transistor pair (5) to the other and one transistor of the third output side differential transistor pair (7). 2. The frequency divider according to claim 1, wherein the frequency divider is connected to the bases of (Q8, Q5). 6. A frequency divider comprising a plurality of frequency dividers connected in cascade, wherein said frequency divider comprises a pair of toggle input terminals (1, 2).
Bipolar double differential master stage circuit (27) in which a complementary clock signal is input to the differential input terminal from 2)
A to 27D) and the pair of toggle input terminals (1, 2)
And the complementary clock signal is input to a differential input terminal, and the differential output is supplied to a pair of divided differential output terminals (23, 24).
Bipolar double differential type slave stage circuits (28A to 28D) for outputting to the slave stage circuits (28A to 28D).
28D) is output to the master stage circuit (27A to 2D).
7D) and a second feedback line (30) for feeding the differential outputs of the master stage circuits (27A to 27D) back to the slave stage circuits (28A to 28D). ), And the first of the master stage circuits (27A to 27D).
The emitter of one transistor (Q9) of the input-side differential transistor pair (3) is connected to the master stage circuit (27A to 27A).
27D) One and the other transistors (Q1, Q4) of the first output differential transistor pair (5) constituting
Of the master stage circuit (27A
27D), the emitter of the other transistor (Q10) of the first pair of input-side differential transistors (3) is connected to the second pair of output-side differential transistors (27A to 27D) of the master stage circuit (27A to 27D). 6) is connected to the common emitter of one and the other transistors (Q2, Q3) and constitutes the slave stage circuit (28A to 28D). ) Is connected to the slave stage circuit (28A to 28A).
28D), one and the other transistors (Q5, Q8) of the third output differential transistor pair (7)
Of the slave stage circuit (28A
To the second input-side differential transistor pair (4) constituting the slave stage circuit (28A to 28D). 8) A frequency divider connected to a common emitter of one and the other transistors (Q6, Q7).