JP2000164866A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a silicide layer from being formed deeper than a diffusion layer, even if a second silicide layer is formed on the bottom surface of a contact hole connected to a first silicide layer on the diffused layer. SOLUTION: A process, in which a diffused layer 12 is formed on the surface of a silicon substrate 11, a process where a first silicide layer 17 is selectively formed on the diffusion layer 12, a process where an undoped silicon layer 18 is formed on the first silicide layer 17, a process where insulating films 19 and 20 are formed on the first silicide layer 17, a process where the insulating films 19 and 20 are etched under such etching condition with high selective ratio against the silicon layer 18 to form a contact hole 22 connected to the silicon layer 18, a process where a barrier metal 23 is formed along the bottom and side surfaces of the contact hole 22, and a process where a second silicide layer 24 connected to the first silicide layer 17 is formed on the bottom surface of the contact hole 22, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device in which a contact hole is formed in an insulating film on a silicide on a surface of a diffusion layer.

[0002]

2. Description of the Related Art FIGS. 13 and 14 show a conventional step of forming an interlayer insulating film in a method of manufacturing a transistor having a silicide layer on a source / drain and a gate electrode in a semiconductor integrated circuit.

[0003] That is, as shown in FIG. 13 (a), an element isolation insulating film 12, a gate electrode 13,
After the formation of the gate sidewall insulating film 14 and the source / drain regions 15, salicide (Salicide: Self Align) is formed.
A first silicide (silicon-metal compound) layer 17 is formed on the surfaces of the gate electrode 13 and the source / drain regions 15 by using a silicidation technique.

[0004] Next, as shown in FIG.
Of the first interlayer insulating film 19 and the second interlayer insulating film 20 are sequentially deposited. Then, as shown in FIG. 13C, after the surface of the second interlayer insulating film 20 is flattened using a flattening technique, a region where a contact hole is formed on the second interlayer insulating film 20 is formed. Then, a resist film 21 having an opening is formed.

[0005] Next, as shown in FIG.
Then, the contact holes 22 are formed by etching the first interlayer insulating films 20 and 19 using the RIE technique.

[0006] Next, as shown in FIG. 14 (e), after removing the resist film 21, a thin barrier metal 23 is formed on the entire surface, and then heat treatment is applied to the contact hole 2.
The second bottom barrier metal 23 is silicided to form a second silicide layer 24. Next, as shown in FIG. 14F, after a tungsten plug 25 is buried in the contact hole 22, a metal wiring 26 is formed by a normal process.

In the above-described manufacturing process, when forming the contact hole 22, the first silicide layer 17 on the source / drain region 15 is etched away. Further, when the barrier metal 23 is formed and heat-treated, the barrier metal 23 reacts with silicon and
Is formed deeper than the first silicide layer 17. At this time, the second silicide layer 24 causes a junction leak by overtaking the depth of the source / drain region 15.

In addition, misalignment occurs in the patterning of the contact hole 22, and the source / drain region 1
Contact hole 22 at the boundary between
Is formed on the bottom surface of the contact hole 22 due to the etching selectivity, and peels off at the interface between the plug electrode (tungsten plug 25) and the barrier metal 23 due to poor coverage when the barrier metal 23 is formed. May occur and a contact failure may occur.

[0009]

SUMMARY OF THE INVENTION As described above, the first
Forming a contact hole connected to the silicide layer in the interlayer insulating film and then forming a barrier metal along the surface of the contact hole, the first silicide layer is cut off,
Due to the formation of the second silicide layer, the silicide layer becomes M
There is a problem that a junction leak is caused by overtaking the depth of the source / drain region of the IS transistor.

[0010] Further, when the misalignment occurs and the contact hole runs over the element isolation insulating film, a contact failure may occur due to the separation between the barrier metal and the plug electrode due to the step formed on the bottom surface of the contact hole. Was.

An object of the present invention is to form a second silicide layer containing a metal element constituting a barrier metal formed on a surface of a contact hole connected to a first silicide layer on a diffusion layer on a bottom surface of the contact hole. However, the formation of the silicide layer deeper than the diffusion layer is suppressed, and furthermore, even when the misalignment occurs and the contact hole runs over the element isolation insulating film and a step occurs, occurrence of a contact failure can be avoided. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0012]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) A method for manufacturing a semiconductor device according to the present invention (claim 1) includes a step of forming a diffusion layer on a surface of a silicon substrate, and a step of selectively forming a first silicide layer on the diffusion layer. Forming an undoped silicon layer on the silicon substrate so as to cover the first silicide layer;
Forming an insulating film on the silicide layer; and selectively contacting the insulating film with the silicon layer by selectively etching a part of the insulating film under etching conditions having a high selectivity to the silicon layer. Forming a hole;
A step of forming a barrier metal on at least the bottom surface of the contact hole; and performing a heat treatment to cause the barrier metal and the silicon layer to react with each other and to connect a first silicide layer on the bottom surface of the contact hole to the first silicide layer. Forming a layer and burying a plug electrode in the contact hole. (2) A method of manufacturing a semiconductor device according to the present invention (claim 2) includes a step of forming a diffusion layer on a surface of a silicon substrate, and a step of selectively forming a first silicide layer on the diffusion layer. Forming an insulating film on the first silicide layer; selectively etching a part of the insulating film to form a contact hole in the insulating film connected to the first silicide layer; A step of forming a silicon layer on at least the bottom surface of the hole, a step of forming a barrier metal on the silicon layer, and performing a heat treatment so that the barrier metal and the silicon layer react with each other. Forming a second silicide layer connected to the first silicide layer; and burying a plug electrode in the contact hole. (3) In the method of manufacturing a semiconductor device according to the present invention (claim 3), a step of forming a first silicide layer on at least a source / drain region of a MIS transistor formed on a silicon substrate; , The MIS
Forming an undoped silicon layer so as to cover the transistor and the first silicide layer; forming an interlayer insulating film on the silicon substrate so as to cover the MIS transistor and the silicon layer; Selectively etching a part of the interlayer insulating film under an etching condition having a high selectivity to form a contact hole connected to the silicon layer on the first silicide layer; Forming a barrier metal along the side surface and performing a heat treatment to cause the barrier metal and the silicon layer to react with each other to form a second silicide layer connected to a first silicide layer on the bottom surface of the contact hole And forming a plug electrode in the contact hole. (4) A method of manufacturing a semiconductor device according to the present invention (claim 4) includes a step of forming a first silicide layer at least on a source / drain region of a MIS transistor formed on a silicon substrate; , The MIS
Forming an undoped silicon layer at least excluding at least the gate electrode of the transistor and covering at least a portion of the first silicide layer;
Forming an interlayer insulating film so as to cover the MIS transistor and the silicon layer; and selectively etching a part of the interlayer insulating film under etching conditions having a high selectivity with respect to the silicon layer; Forming a contact hole that connects to the silicon layer on the layer;
A step of forming a barrier metal along the bottom and side surfaces of the contact hole; and performing a heat treatment to cause the barrier metal and the silicon layer to react with each other and connect the first silicide layer to the bottom surface of the contact hole. 2) forming a silicide layer, and burying a plug electrode in the contact hole. (5) In the method of manufacturing a semiconductor device according to the present invention (claim 5), a step of forming a first silicide layer on at least a source / drain region of a MIS transistor formed on a silicon substrate; , The MIS
A step of forming an interlayer insulating film so as to cover the transistor and the first silicide layer; a step of selectively etching a part of the interlayer insulating film to form a contact hole connected to the first silicide layer; Forming a silicon layer along the bottom and side surfaces of the contact hole, forming a barrier metal along the surface of the silicon layer, and reacting the barrier metal with the silicon layer by performing a heat treatment. Forming a second silicide layer connected to a first silicide layer on the bottom surface of the contact hole; and burying a plug electrode in the contact hole.

As a material of the first silicide layer, a metal compound of titanium, nickel, cobalt, palladium and the like and silicon can be used.

[Function] The present invention has the following functions and effects by the above configuration.

According to the present invention, the formation position of the second silicide layer formed by the reaction between the barrier metal and the silicon layer is determined by the fact that the silicon in the first silicide layer reacts with the barrier metal as in the prior art. Since the second silicide layer is formed to be substantially shallower than the second silicide layer formed as described above, a margin for junction leakage caused by forming the silicide layer deeper than the diffusion layer is improved.

Further, when etching for forming a contact hole in the interlayer insulating film, the etching is stopped within the thickness of the silicon layer by using a condition having a high selectivity with respect to silicon. Even when the contact hole runs over the boundary between the element isolation region and the source / drain region, since the material at the bottom of the contact hole is all a single material of silicon, the etching is uniform and no complicated steps are formed. Therefore, at the time of forming the barrier metal, peeling does not occur at the interface between the plug electrode and the barrier metal due to poor coverage at the step.

Further, by patterning silicon and selectively forming a silicon layer, a small leak does not occur between the gate electrode and the source / drain region and between the elements in the same element.

Further, by depositing silicon after the formation of the contact hole, the silicide layer at the bottom of the contact hole formed on the source / drain region is added to the bottom of the contact even if it is etched away. The second silicide layer generated by the reaction between the silicon layer and the barrier metal, which is less likely to overtake the depth of the diffusion layer, can effectively prevent the occurrence of junction leak.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIGS. 1 to 5 show a process of manufacturing a semiconductor integrated circuit having a MIS transistor having a silicide layer formed on a source / drain region and a gate electrode according to a first embodiment of the present invention. FIG.

First, as shown in FIG.
After the element isolation insulating film 12 is formed on the silicon substrate 11 of the mold type, the gate electrode 13, the gate sidewall insulating film 14, and the source / drain regions 15 of, for example, n-type are formed by using a known method. Next, as shown in FIG. 1B, a metal film 16 such as a refractory metal is deposited on the entire surface of the silicon substrate 11. Next, as shown in FIG. 1C, a thin first silicide layer 17 having a thickness of about several nm to several tens nm is selectively formed only on the surfaces of the gate electrode 13 and the source / drain regions 15 by using the salicide technique. Form.

Next, as shown in FIG. 2 (d), a thin undoped silicon layer 18
VD (Chemical Vapor Deposition),
Alternatively, deposition is performed using a sputtering method. Note that the silicon layer 18 may be in any form of polysilicon or amorphous silicon. That is, when polysilicon or amorphous silicon is used, film formation can be performed at a low temperature, so that a problem such as condensation of a silicide layer does not occur during film formation.

Next, as shown in FIG. 2E, a first interlayer insulating film 19 and a second interlayer insulating film 20 are sequentially deposited on the entire surface. Next, as shown in FIG.
The surface of the second interlayer insulating film 20 is flattened by using a flattening technique such as an emical mechanical polishing (chemical mechanical polishing) technique.

Next, as shown in FIG. 3G, a resist film 21 is applied, and the resist film 21 is patterned using a photolithography technique. Then, FIG.
As shown in (h), the second interlayer insulating film 20 and the first interlayer insulating film 19 are sequentially etched by using RIE (Reactive Ion Etching) technology using the resist film 21 as a mask material. The etching at this time uses a condition having a high selectivity with respect to the silicon layer 18.
The etching is stopped at the silicon layer 18. Further, the etching of the second interlayer insulating film 20 and the etching of the first interlayer insulating film 19 can be performed separately. Then, FIG.
As shown in (i), the resist film 21 is removed, and a contact hole 22 connected to the silicon layer 18 on the first silicide layer 17 is formed.

Next, as shown in FIG. 4J, a barrier metal 23 is deposited on the entire surface by sputtering to suppress the diffusion of tungsten buried in the contact hole 22. Next, as shown in FIG.
The second silicide layer 24 is formed by reacting the bottom silicon layer 18 with the barrier metal 23. Since the silicon layer 18 at the bottom of the contact hole 22 is thin enough to completely silicide, the second silicide layer 24 comes into contact with the first silicide layer 17 and the second silicide layer 24 and the first silicide layer 17 Continuity is obtained.

Next, as shown in FIG.
After a tungsten film serving as a plug is deposited on the entire surface by using a method, the barrier metal 23 and the tungsten film on the second interlayer insulating film 20 are removed by using a CMP method or the like, and a tungsten plug 25 is formed in the contact hole 22. Buried formation. The tungsten plug 25 may be formed by forming a selective tungsten film only on the bottom of the contact hole 22. Next, as shown in FIG. 5 (m), a wiring metal film is deposited on the entire surface and patterned to form a metal wiring 26.

According to the above embodiment, as shown in FIG. 3 (h), the thickness of the silicon layer 18 is increased by using a condition that the selectivity with the silicon layer 18 is high at the time of etching when forming the contact hole 22. Even if the contact hole 22 runs over the boundary between the element isolation insulating film 12 and the source / drain region 15 due to misalignment caused by stopping the etching in the inside, the shape of the bottom of the contact hole 22 can be obtained through a conventional process. Since the material at the bottom of the contact hole 22 is all a single material of the silicon layer 18 as compared with the one formed, the etching is made uniform and no complicated steps are formed.

Therefore, peeling does not occur at the interface between the tungsten and the barrier metal due to poor coverage at the step in the sputtering of the barrier metal. Further, the second silicide layer formed by the reaction between the barrier metal and silicon is substantially shallower than the second silicide layer formed through the conventional process, so that the silicide layer is deeper than the diffusion layer. Thus, the margin for the junction leak generated by the above is improved.

[Second Embodiment] In the first embodiment, a thin undoped polysilicon of about several tens of nm or amorphous silicon is deposited on the entire surface. This figure 5
In the structure shown in (m), a leak current may be generated between the gate electrode and the source / drain region in the same device or between different devices separated by the device isolation region. Therefore, an embodiment for preventing this will be described in detail with reference to the drawings.

FIGS. 6 to 9 are sectional views showing the steps of manufacturing a semiconductor integrated circuit having a MIS transistor having a silicide layer formed on a source / drain region and a gate electrode according to a second embodiment of the present invention. is there.

First, through the same steps as those described in the first embodiment with reference to FIGS. 1A to 2D,
Element isolation insulating film 12 and gate electrode 1 on silicon substrate 11
3, gate sidewall insulating film 14, source / drain region 15
Is formed, and then a metal film is deposited on the entire surface of the silicon substrate 11, and the gate electrode 1 is formed using salicide technology.
3 and a thin first silicide layer 17 having a thickness of about several nm to several tens of nm is selectively formed only on the source / drain regions 15. Further, a thin undoped silicon layer 18 of about several tens nm is formed thereon.

Then, as shown in FIG. 6A, a resist film 31 is applied on the silicon layer 18, and the resist film 31 is patterned by using a lithography technique. The exposed portion of the silicon layer 18 is exposed.

Next, as shown in FIG. 6B, the silicon layer 18 is subjected to RIE by using the resist film 31 as a mask material.
Alternatively, the first silicide layer 17 in a region adjacent to the gate electrode 13 is exposed by etching using CDE (Chemical Dry Etching) technology. Next, as shown in FIG. 6C, the resist film 31 is removed. At this time, the silicon layer 18 is selectively left only in a range in which misalignment of the contact holes is considered in addition to a region of a contact hole to be formed later.

Thereafter, as in the first embodiment, the first and second interlayer insulating films 19 and 20 are deposited (FIG. 7D), and the second interlayer insulating film 20 is planarized (FIG. 7E). )), Patterning of the resist film 21 (FIG. 7 (f)), formation of the contact hole 22 (FIG. 8 (g)), (FIG. 8 (h)), accumulation of the barrier metal 23 (FIG. 8 (i)) , The formation of the second silicide layer 24 (FIG. 9 (j)), the formation of the tungsten plug 25 (FIG. 9 (k)), and the formation of the metal wiring 26 (FIG. 9).
The semiconductor device is completed through the step (l)).

According to the above embodiment, since the silicon layer 18 is selectively formed by patterning after the deposition of the silicon layer 18, the gate electrode in the same element as in the first embodiment described above is formed. -No minute leakage occurs between the source / drain regions and between the elements.

Third Embodiment FIGS. 10 to 12 show a process of manufacturing a semiconductor integrated circuit having a MIS transistor having a silicide layer formed on a source / drain region and a gate electrode according to a third embodiment of the present invention. FIG.

First, as shown in FIG. 10A, through the same steps as those described in the first embodiment, an element isolation insulating film 12, a gate electrode 13, and a gate side wall insulating film 14 are formed on the surface of a silicon substrate 11. , Source / drain regions 15 are formed. Then, a thin first silicide layer 17 having a thickness of several nm to several tens nm is selectively formed only on the gate electrode 13 and the source / drain regions 15. Next, after a first interlayer insulating film 19 and a second interlayer insulating film 20 are sequentially deposited,
The second interlayer insulating film 20 is formed by using a planarization technique such as a CMP method.
The surface of is flattened. Next, a contact hole 22 is formed by forming a resist pattern on the second interlayer insulating film 20, etching the first interlayer insulating film 19 and the second interlayer insulating film 20 by RIE, and removing the resist pattern. I do.

Next, as shown in FIG. 10B, a thin silicon layer 18 of several tens of nm is deposited on the entire surface. Note that the silicon layer 18 may be in any form of amorphous silicon or polysilicon. Next, as shown in FIG. 10C, the second interlayer insulating film 2 is formed by using a CMP technique or the like.
The silicon layer 18 on the surface of the contact hole 22 is removed so that the silicon layer 18 remains at least at the bottom of the contact hole 22.

Next, as shown in FIG. 11D, a barrier metal 23 is deposited on the entire surface of the contact hole 22 by using a sputtering method. Next, as shown in FIG. 11E, the silicon layer 18 reacts with the barrier metal 23 by applying a heat treatment to form a second silicide layer 24. Since the silicon layer 18 at the bottom of the contact hole 22 is thin enough to be completely silicided, the second silicide layer 24 and the first silicide layer 17 are in contact with each other, and conduction is obtained.

Next, as shown in FIG.
The barrier metal 23 on the interlayer insulating film 20 is removed, and a tungsten plug 25 is buried in the contact hole 22. Next, as shown in FIG. 12G, a wiring metal film is deposited on the entire surface and patterned to form a metal wiring 26.

According to the above embodiment, the first contact hole 22 formed on the source / drain region 15 is formed at the bottom of the contact hole 22.
Even if the silicide layer 17 is etched away, a polysilicon or amorphous silicon layer is added to the bottom of the contact, so that the second silicide layer generated by the reaction with the barrier metal overtakes the search for the diffusion layer. And junction leakage can be prevented.

Further, when a contact hole is formed so as to run over the element isolation region due to misalignment,
Since the contact hole is formed over the silicide region of the source / drain region and the SiO ₂ region of the element isolation region, the bottom surface of the contact is etched at different etching rates, and a step is generated at the bottom of the contact hole. In addition, it has a salicide structure, and has a source / drain,
And when there is a silicide layer on the gate electrode, the silicide layer tends to be thinner at the end of the source / drain region near the boundary of the element isolation region, and the thinner portion of this silicide layer is easily dug at the time of etching the contact hole.
A step occurs.

For this reason, if a barrier metal is deposited directly on the bottom surface of the contact by a sputtering method having poor coverage at the stepped portion, a region not covered with the barrier metal is formed, and the barrier property against the tungsten plug is lost and the interface with the barrier metal is lost. There is a problem that the tungsten is peeled off.

However, according to the present embodiment, patterning is performed so that misalignment occurs and the contact hole runs over the element isolation region, or the first silicide layer at the end of the source / drain region is thin, and that portion is contacted. Even if there is a step at the bottom of the contact hole due to digging intensively during etching of the hole, since the silicon layer is deposited on the inner wall of the contact hole, the part dug by etching such as the element isolation region is filled, The step due to the excavation is reduced, the sputtered shape of the barrier metal is improved, and contact failure due to peeling at the interface between the tungsten plug and the barrier metal can be suppressed. Also, by using this method, a silicon layer remains on the side surface of the contact hole, but there is no particular problem in terms of electrical. Note that the present invention is not limited to the above embodiment. For example, the invention can be applied not only to the source / drain regions of the MIS transistor but also to a diffusion layer forming another semiconductor element. Further, a silicide layer may not be formed on the gate electrode of the MIS transistor.

In addition, the present invention can be implemented in various modifications without departing from the scope of the invention.

[0046]

As described above, according to the present invention, a contact hole is opened on a first silicide layer formed on a diffusion layer, and a metal constituting a barrier metal formed on the surface of the contact hole is formed. Even when the second silicide layer containing the element is formed on the bottom surface of the contact hole, formation of the silicide layer deeper than the diffusion layer is suppressed.

Further, even if the misalignment occurs and the contact hole runs over the element isolation insulating film, it is possible to avoid the occurrence of a contact failure due to a step at the bottom surface of the contact hole.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 6 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 8 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 9 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 10 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 11 is a process sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment;

FIG. 12 is a process sectional view illustrating the manufacturing process of the semiconductor device according to the third embodiment;

FIG. 13 is a process sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 14 is a process sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 12 ... Element isolation insulating film 13 ... Gate electrode 14 ... Gate side wall insulating film 15 ... Source / drain region 16 ... Metal film 17 ... First silicide layer 18 ... Silicon layer 19 ... First interlayer insulating film 20 ... second interlayer insulating film 21 ... resist film 22 ... contact hole 23 ... barrier metal 24 ... second silicide layer 25 ... tungsten plug 26 ... metal wiring 31 ... resist film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shimichi Matsuoka 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama office (reference) 4M104 AA01 BB01 CC01 CC05 DD04 DD84 DD99 FF14 GG09 HH04 HH08 5F040 DA00 DA20 DC01 EC01 EC07 EC13 EH02 EH07 EH08 EJ02 EJ03 FC00 FC19

Claims (5)

[Claims] A step of forming a diffusion layer on a surface of a silicon substrate; a step of selectively forming a first silicide layer on the diffusion layer; and a step of covering the first silicide layer on the silicon substrate. Forming an undoped silicon layer, forming an insulating film on the first silicide layer, and selectively etching a part of the insulating film under etching conditions having a high selectivity to the silicon layer. Forming a contact hole connected to the silicon layer in the insulating film; forming a barrier metal on at least a bottom surface of the contact hole; performing a heat treatment to react the barrier metal with the silicon layer. Forming a second silicide layer connected to a first silicide layer on a bottom surface of the contact hole; and forming a plug in the contact hole. Forming a buried electrode. 2. A step of forming a diffusion layer on a surface of a silicon substrate, a step of selectively forming a first silicide layer on the diffusion layer, and a step of forming an insulating film on the first silicide layer. A step of selectively etching a part of the insulating film to form a contact hole connected to a first silicide layer in the insulating film; and a step of forming a silicon layer on at least a bottom surface of the contact hole. Forming a barrier metal on the silicon layer; and performing heat treatment to cause the barrier metal and the silicon layer to react with each other, thereby forming a second silicide layer connected to a first silicide layer on the bottom surface of the contact hole. Forming a plug electrode in the contact hole, and forming the plug electrode in the contact hole. 3. A step of forming a first silicide layer at least on a source / drain region of a MIS transistor formed on a silicon substrate, and covering the MIS transistor and the first silicide layer on the silicon substrate. Forming an undoped silicon layer on the silicon substrate; forming an interlayer insulating film on the silicon substrate so as to cover the MIS transistor and the silicon layer; Selectively etching a part of the interlayer insulating film to form a contact hole connected to the silicon layer on the first silicide layer; and forming a barrier metal along the bottom and side surfaces of the contact hole. Reacting the barrier metal and the silicon layer by performing a heat treatment, Forming a second silicide layer connected to the first silicide layer on the bottom surface of Tohoru method of manufacturing a semiconductor device which comprises a step of forming the buried plug electrode in the contact hole. 4. A step of forming a first silicide layer at least on a source / drain region of a MIS transistor formed on a silicon substrate; and excluding at least a gate electrode of the MIS transistor on the silicon substrate. Forming an undoped silicon layer covering at least a part of the first silicide layer; forming an interlayer insulating film on the silicon substrate so as to cover the MIS transistor and the silicon layer; Selectively etching a part of the interlayer insulating film under an etching condition having a high selectivity to form a contact hole connected to the silicon layer on the first silicide layer; Forming a barrier metal along the side surface; Forming a second silicide layer connected to a first silicide layer on a bottom surface of the contact hole, and forming a plug electrode in the contact hole. A method for manufacturing a semiconductor device, comprising: 5. A step of forming a first silicide layer on at least a source / drain region of a MIS transistor formed on a silicon substrate; and covering the MIS transistor and the first silicide layer on the silicon substrate. Forming an interlayer insulating film on the substrate; selectively etching a part of the interlayer insulating film to form a contact hole connected to a first silicide layer; Forming a silicon layer along the surface of the silicon layer; and performing heat treatment to cause the barrier metal and the silicon layer to react with each other, thereby forming a first layer on the bottom surface of the contact hole. Forming a second silicide layer connected to the first silicide layer, and embedding a plug electrode in the contact hole. The method of manufacturing a semiconductor device which comprises the step of write form.