JP2000164652A - Multilayer interconnection board for wafer collective conduct board, connector connecting to it, connection structure for them, and inspecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a connection structure, etc., for quickly connecting a connector with ease and without misalignment to the outer peripheral pad of a multilayer interconnection board of a wafer collective contact board. SOLUTION: In a multilayer interconnection board 10 constituting a part of a wafer collective contact board, an outer peripheral pad 51 formed in the peripheral region of the board is made into a block for standardization, while a guide part (guide hole 53) for guiding and alignment when a connector is connected to the block outer peripheral pad 51, is provided adjacent to it. A connector 60 comprises a clip structure, provided with an engagement part (guide pin 16) to be engaged with or inserted in a guide part 53 and a spring 62. When the multilayer interconnection board 10 is connected to the connector 60, the guide part 53 and the engagement part 16 are engaged together for connection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer forming a part of a wafer batch contact board used for collectively performing a test (inspection) of a large number of semiconductor devices formed on a wafer in a wafer state. The present invention relates to a multilayer wiring board for a collective contact board, a connector connected to an outer peripheral pad of the multilayer wiring board, and a connection structure thereof.

[0002]

2. Description of the Related Art Inspection of a large number of semiconductor devices formed on a wafer is roughly classified into a product inspection (electrical characteristic test) using a probe card and a burn-in test which is a reliability test performed thereafter. The burn-in test is one of screening tests performed to remove a semiconductor device having an intrinsic defect or a device which causes a time- and stress-dependent failure from manufacturing variations. The burn-in test can be said to be a thermal acceleration test, while the inspection with a probe card is an electrical characteristic test of the manufactured device.

[0003] The burn-in test is an ordinary method (one chip) in which a wafer is cut into chips by dicing after a electrical characteristic test performed for each chip by a probe card, and the packaged products are subjected to a burn-in test one by one. Burn-in systems are not feasible in terms of cost. Accordingly, development and commercialization of a wafer batch contact board (burn-in board) for simultaneously performing a burn-in test of a large number of semiconductor devices formed on a wafer at once are being promoted (Japanese Patent Laid-Open No. 7-2310).
No. 19). Wafer and batch burn-in systems using wafer batch contact boards are not only highly feasible in terms of cost, but also important technologies for realizing the latest technological flows such as bare chip shipping and bare chip mounting. . The wafer batch contact board is different from the conventional probe card in required characteristics in that the wafer is inspected in a batch and used in a heating test, and the required level is high. When the wafer batch contact board is put into practical use, the product inspection (electrical characteristic test) conventionally performed by the probe card can be performed by the wafer batch.

FIG. 13 shows a specific example of a wafer batch contact board. The wafer batch contact board is shown in FIG.
As shown in FIG. 1, a membrane ring 30 with bumps is fixed on a multilayer wiring board for a wafer batch contact board (hereinafter, referred to as a multilayer wiring board) 10 via an anisotropic conductive rubber sheet 20. The membrane ring 30 with bumps is in charge of a contact portion that comes into direct contact with the wafer to be inspected. In the membrane ring 30 with bumps, bumps 33 are formed on one surface of a membrane 32 stretched over the ring 31 and pads 34 are formed on the other surface. The bumps 33 are pads formed on the periphery or center line of each semiconductor chip on the wafer 40 (about 600 to 1000 pins per chip, and the number of pads multiplied by the number of chips is on the wafer). , The same number of pads are formed at corresponding positions. The multilayer wiring board 10 has a wiring for applying a predetermined burn-in test signal or the like to each bump 33 isolated on the membrane 32 via a pad 34 on an insulating substrate. The multilayer wiring board 10 has a multilayer wiring structure because the wiring is complicated. The anisotropic conductive rubber sheet 20 is an elastic body (consisting of silicon resin, in which metal particles are embedded in pad electrode portions) having conductivity only in a direction perpendicular to the main surface, and is formed on the multilayer wiring board 10. (Not shown) and the pads 34 on the membrane 32 are electrically connected. The anisotropic conductive rubber sheet 20 has a projection (not shown) formed on the surface thereof, and a membrane 32.
The contact with the upper pad 34 absorbs irregularities on the surface of the semiconductor wafer 40 and variations in the height of the bump 33, and the pad on the semiconductor wafer and the bump 33 on the membrane 32 are absorbed.
And are securely connected.

[0005]

Since the wafer batch contact board performs inspection of semiconductor devices on the wafer all at once, defects such as disconnection and short circuit (open short) occur in the wafer batch contact board. There must be no. For this reason, inspection at the time of shipment and inspection at the time of delivery of the wafer batch contact board are required. Such a wafer batch contact board inspection apparatus can be realized by the same method as the probe card inspection apparatus used for the open / short check of the probe card. In a probe card inspection device, a motherboard (DUT board) having pogo pins (spring-elongated pins) corresponding to the outer peripheral pads of the probe card in a one-to-one correspondence.
Is used to inspect the probe card.

[0006] However, since the wafer batch contact board has a large substrate and requires a large number of pins, it is very expensive (about 10 million yen) to manufacture a mother board for wafer batch contact board inspection. It has become unprofitable and unpractical. Furthermore, in this method, since the arrangement of the outer peripheral pads of the wafer batch contact board (multilayer wiring board) differs depending on the semiconductor device to be inspected, a dedicated motherboard is required for each semiconductor device, resulting in an enormous cost. Would.

For this reason, at present, a connector such as an FPC (Flexible Printed Circuit) in which wiring is formed on a transparent flexible sheet is visually aligned with the outer peripheral pad and connected. However, even if the power supply line, the ground line, and the signal line of the multilayer wiring board are shared and reduced, the number of outer peripheral pads is still large, and the number of FPCs to be connected must be 10 or more.
It is complicated and time-consuming to accurately and visually align the FPCs one by one with the outer peripheral pads of the substrate. In addition, the inspection at the time of shipment and the inspection at the time of delivery of the wafer batch contact board are all inspections, and the number of wafer batch contact boards is large, so that connectors can be connected easily and quickly without displacement. Requested. These problems are the same in a wafer batch inspection apparatus (burn-in inspection apparatus or the like) that performs an actual inspection using a wafer batch contact board.

SUMMARY OF THE INVENTION The present invention has been made under the above-mentioned background, and has a structure of a multilayer wiring board for easily and quickly connecting a connector to an outer peripheral pad of a multilayer wiring board in a wafer batch contact board without displacement. A first object is to realize a connector structure and a connection structure thereof. Also, there is no need for expensive pogo-pin-integrated motherboards, and the connector can be easily and quickly connected to the outer peripheral pads of the multilayer wiring board in the wafer batch contact board without any displacement, and the connection work can be made more efficient. A second object is to provide an inspection apparatus and a wafer batch inspection apparatus.

[0009]

Means for Solving the Problems To achieve the above object, the present invention has the following configuration.

(Structure 1) A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer. A multilayer wiring board for a wafer batch contact board, comprising a guide portion adjacent to an outer peripheral pad formed in a peripheral region and serving as a guide and an alignment when connecting a connector.

(Structure 2) A multilayer wiring board constituting a part of a wafer batch contact board used for performing a test of a large number of semiconductor devices formed on a wafer at one time, A multilayer wiring board for a wafer batch contact board, wherein peripheral pads formed in a peripheral region are blocked.

(Structure 3) A multilayer wiring board constituting a part of a wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer, wherein the multilayer wiring board is A multilayer wiring board for a wafer batch contact board, wherein a line width and a line interval of an outer peripheral pad formed in a peripheral region are standardized.

(Structure 4) A connector connected to an outer peripheral pad of a multi-layer wiring board constituting a part of a wafer batch contact board used for batch testing of a large number of semiconductor devices formed on a wafer. A connector having an engaging portion that engages or fits with a guide portion formed on the multilayer wiring board.

(Structure 5) The connector according to Structure 4, wherein the connector has a clip structure that can be attached by narrowing the substrate.

(Structure 6) In a multi-layer wiring board constituting a part of a wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer, the multilayer wiring board is formed in a peripheral area of the board. A guide portion that plays a role of guiding and positioning when connecting a connector to the blocked outer peripheral pad, adjacent to the blocked outer peripheral pad, and standardizing the outer peripheral pad. The structure provided, and the structure of the connector for connection to be connected to the blocked outer peripheral pad, has an engaging portion to be engaged or fitted with a guide portion formed on the multilayer wiring board, and And a structure having a clip structure that can be attached by narrowing the multilayer wiring board, and when connecting the connector to the multilayer wiring board, the guide section Connection structure characterized in that said engagement portion has a structure to be connected engage.

(Structure 7) An inspection apparatus for a wafer batch contact board, characterized by using at least the multilayer wiring board for a wafer batch contact board according to any one of Structures 1 to 3 and the connector according to Structures 4 to 5.

(Structure 8) A wafer batch inspection, comprising at least a wafer batch contact board having the multilayer wiring board for a wafer batch contact board according to any one of Structures 1 to 3, and a connector according to Configurations 4 to 5. apparatus.

[0018]

According to the configuration 1, when connecting the connector adjacent to the outer peripheral pad of the multilayer wiring board, it is guided (positioned).
By providing the guide part which fulfills the function of (1), the connector may be connected in accordance with the guide part, and therefore, the connector can be quickly and easily connected to the outer peripheral pad without displacement.

According to the configuration 2, by forming the outer peripheral pads into blocks, a connector may be connected for each block.
Therefore, the connector can be easily and quickly connected to the outer peripheral pad at low cost.

According to the configuration 3, the connector can be standardized by standardizing the line width and the line interval of the outer peripheral pad, and the connector can be manufactured easily and inexpensively. Further, by blocking and standardizing the outer peripheral pad, the connector can be manufactured more easily and at lower cost.

According to the fourth aspect, by providing the connector with the engaging portion, the engaging portion and the guide portion formed on the multilayer wiring board are simply engaged or fitted to each other, so that the outer peripheral pad can be easily and reliably provided. The connector can be quickly and easily connected to the connector without displacement.

According to the fifth aspect, by using a clip-type connector, it is possible to simply and reliably connect the substrate only by narrowing the substrate. Also, the connector can be easily attached and detached.

According to the configuration 6, by combining the above-mentioned configurations 1 to 5, it is not necessary to perform a strict visual alignment at the time of connection, so that the connector can be quickly and reliably connected to the outer peripheral pad without displacement. A connection structure can be realized.

According to the configuration 7, by adopting the above configurations 1 to 5, the connector can be easily and quickly connected to the outer peripheral pad without any displacement in the inspection apparatus for the wafer batch contact board. Thus, the working time can be reduced.

According to the configuration 8, by adopting the above-mentioned configurations 1 to 5, the connector can be easily and quickly connected to the outer peripheral pad without any displacement in the wafer batch inspection apparatus (burn-in inspection apparatus or the like). The working time can be reduced with an inexpensive device.

[0026]

Embodiments of the present invention will be described below.

(Preparation of Multilayer Wiring Board) FIGS. 9 and 10
FIG. 7 is a cross-sectional view of a main part showing an example of a manufacturing process of a multilayer wiring board. As shown in step (1) of FIG. 9, a Cr film was sputtered on one surface of a glass substrate 1 (manufactured by HOYA: NA40, size 320 mm square, thickness 3 mm) whose surface was polished flat. A Ni / Cu / Cr multilayer wiring layer 2 is formed by sequentially forming a Cu film with a thickness of about 2.0 μm and a Ni film with a thickness of about 0.3 μm at 300 Å. Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu. Ni is provided for the purpose of preventing oxidation of Cu, enhancing the adhesion between Cu and the resist, and preventing polyimide from remaining at the bottom of the contact hole (via) due to the reaction between Cu and polyimide. ing. Note that the method for forming Ni is not limited to the sputtering method, and may be formed by an electrolytic plating method. Also, N
It is also possible to reduce the contact resistance by forming an Au film on the i film by a sputtering method, an electrolytic plating method or an electroless plating method.

Next, as shown in step (2) of FIG. 9, a predetermined photolithography step (resist coating, exposure, development, etching) is performed, and the Ni / Cu / Cr multilayer wiring layer 2 is patterned. First-layer wiring pattern 2
a is formed. Specifically, first, a resist (Microposit S1400 manufactured by Shipley Co., Ltd.) is coated to a thickness of 3 μm, baked at 90 ° C. for 30 minutes, and exposed and developed with a predetermined mask to obtain a desired resist pattern ( (Not shown). Using this resist pattern as a mask, the Ni / Cu / Cr multilayer wiring layer 2 is etched using an etching solution such as an aqueous ferric chloride solution,
Thereafter, the resist is stripped using a resist stripper, washed with water and dried to form a first-layer wiring pattern 2a.

Next, as shown in step (3) of FIG.
A polyimide insulating layer 3 is formed by applying a photosensitive polyimide precursor to a thickness of 10 μm on the wiring pattern of the layer using a spinner or the like. A contact hole 4 is formed in the polyimide insulating layer 3. More specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, exposed and developed using a predetermined mask, and is then exposed to contact holes 4.
To form After curing the photosensitive polyimide precursor completely at 350 ° C. for 4 hours in a nitrogen atmosphere, the polyimide surface is roughened by oxygen plasma treatment, and the second wiring layer formed in the next step And oxidizes and removes organic substances such as polyimide and residual developer in the contact hole 4.

Next, as shown in step (4) of FIG. 9, a Ni / Cu / Cr multilayer wiring layer 5 is formed in the same manner as in step (1).

Next, as shown in step (5) of FIG. 9, the Ni / Cu / Cr multilayer wiring layer 5 is patterned in the same manner as in step (2) to form a second wiring pattern 5a. I do.

Next, as shown in step (6) of FIG.
The above steps (3) to (5) are repeated in the same manner to sequentially form the second-layer polyimide insulating layer 6, the contact hole 7, and the third-layer wiring pattern 8a, thereby forming a three-layer glass multilayer wiring board. Obtained. However, the third-layer wiring pattern 8a
Is a multilayer wiring having an Au / Ni / Cu / Cr structure for the purpose of improving electrical contact with an anisotropic conductive film. Specifically, an Au film is formed on a Ni film by electroplating.
Except that the Au film was etched using an aqueous solution of iodine and potassium iodide.
A third-layer wiring pattern 8a was formed in the same manner as the first-layer wiring pattern. The Ni film plays a role in enhancing the adhesion between the Au film and Cu. Although an Au film can be formed on the Ni film by electroless plating, the thickness of the Au film cannot be increased.

In the present embodiment, in step (6) of FIG. 10, as shown in FIG. 1, an outer peripheral pad (external take-out terminal) 5 formed in a peripheral region of the uppermost layer of the multilayer wiring board.
1 was divided into a plurality of outer peripheral pad groups, and the line widths and line intervals of the outer peripheral pads in the vertical, horizontal, and oblique directions on the paper surface of FIG. 1 were respectively standardized. Note that FIG. 1 is drawn in a simplified manner for ease of explanation, and the mode of block formation and standardization is not limited to the mode shown in FIG. The number of blocks can be freely designed, for example, about 10 to 20. Blocking and standardization can be freely designed according to the type of semiconductor device (memory, ASIC, MPC, microcomputer, CLD, etc.).

Next, as shown in a step (10) of FIG. 10, after removing the resist, a polyimide as an insulating film is applied on the substrate, and is patterned to form a protective insulating film 1.
Thus, a multilayer wiring board 10 for a wafer batch contact board was obtained.

(Formation of Guide Portion) Next, as shown in FIG. 1, a guide hole 53 is provided as a guide portion on both sides of each block of the peripheral pad 52 which is formed into a block.

(Preparation of Connector) Next, as shown in FIG. 2, a connector 60 to be connected to the blocked outer peripheral pads was prepared. The connector 60 has a guide pin 61 as an engaging portion that engages with or fits into the guide hole 53 formed in the multilayer wiring board 10. Also, the connector 60
As shown in FIGS. 2 and 3, the clip structure has a spring 62 so that the multilayer wiring board 10 can be attached by narrowing. The connector 60 is connected to the outer peripheral pad 51 on the multilayer wiring board 10 by one-to-one connection with the wiring 6
3, a socket 64 is provided at the other end of the wiring 63, and the wiring 63 is connected to a tester (not shown) via the socket 64.

In the formation of the guide portion, the guide portion includes a penetrated guide hole 54 shown in FIG. 4, a groove-shaped guide hole 55 shown in FIG. 5, and a buried guide pin 5 shown in FIG.
6, an embodiment such as a convex or concave guide pattern 57 shown in FIG. In these cases, the engagement portion of the connector may be shaped to fit the guide portion. It should be noted that the guide portion and the engaging portion may be switched, the guide portion may be formed on the connector side, and the engaging portion may be formed on the multilayer wiring board side.

The formation of the guide holes and the guide grooves in the glass substrate can be performed by using, for example, a drill or an ultrasonic drill. In this case, it is preferable to perform the processing while supplying the abrasive and the water. In the case of a ceramic substrate, a guide hole can be formed by forming a hole in the state of a green sheet and then performing sintering. The depth of the groove-shaped guide hole is 10
If it is about 0 to 500 μm, it can sufficiently function as a guide portion.

The convex or concave guide pattern 57 shown in FIG. 7 can be formed simultaneously with the patterning of the wiring layer or the protective insulating film formed on the uppermost layer of the multilayer wiring board.
When forming a guide pattern using a wiring layer, the protective insulating film around the guide pattern is removed. When the guide pattern is formed using the protective insulating film, the protective insulating film around the guide pattern is removed in the case of a convex shape, and the protective insulating film in the guide pattern portion is removed in the case of a concave shape. The height difference of the convex or concave guide pattern is
A larger one is preferable, but a height difference of several μm can sufficiently function as a guide portion. Therefore, if the height difference is almost the same as the film thickness of the wiring layer (normally 2 to 20 μm) or the film thickness of the protective insulating film (normally 5 to 20 μm), it can sufficiently function as a guide. It is preferable that the positional accuracy and the shape accuracy of the guide portion and the engaging portion are higher. However, even if the accuracy is shifted by several μm, if the guide portion and the engaging portion can be engaged (fitted), the outer peripheral pad 51 and There is no problem in connection with the wiring 63. It is easy to form the guide portion and the engagement portion with such an accuracy.

(Lamination of Anisotropic Conductive Rubber Sheet) Next, the anisotropic conductive rubber sheet made of silicone resin and having metal particles embedded in the pad electrode portions is bonded to the multilayer wiring board 10 for a wafer batch contact board. It was stuck to a predetermined position.

(Preparation of Membrane Ring) Next, a membrane ring with bumps, which serves as a contact portion in direct contact with the wafer, was prepared.

A method for forming a membrane ring will be described with reference to FIG. First, as shown in FIG. 11A, a silicon rubber sheet 36 having a uniform thickness of 5 mm is placed on an aluminum plate 35 having high flatness. On the other hand, for example, on a polyimide film having a thickness of 25 μm,
A film 37 in which copper is formed to a thickness of 18 μm by a sputtering method or a plating method is prepared. The material of the film 37,
The formation method, thickness, and the like can be appropriately selected. For example, thickness 25
μm (12-50 μm) polyimide film,
A silicon rubber sheet having a thickness of about 0.3 mm (0.1 to 0.5 mm) can be used. The film can be formed by a coating method or a commercially available film or sheet can be used. Further, after the polyimide precursor is cast on the copper foil, the polyimide precursor is heated, dried and cured to form a film having a structure in which the copper foil and the polyimide film are bonded. Alternatively, a film having a structure in which a plurality of conductive metals are sequentially formed on one surface of a film and a conductive metal layer having a laminated structure is formed on one surface of the film may be used. A thin Ni film (not shown) may be formed between the polyimide and Cu for the purpose of improving the adhesion between the two and preventing film contamination.

Next, a film 37 having a structure in which copper and a polyimide film are bonded to each other is adsorbed onto the silicon rubber sheet 36 in a state where the film 37 is uniformly spread with the copper side down. At this time, by utilizing the property that the film 37 is adsorbed to the silicon rubber sheet 36, the air layer is adsorbed while being expelled so as not to cause wrinkling or bending, so that the air layer is adsorbed in a uniformly developed state.

Next, an outer diameter of 260 mmφ and an inner diameter of 240 mm
A thermosetting adhesive 38 is thinly and uniformly applied to a bonding surface of a circular SiC ring 31 having a thickness of about 2 mm and having a thickness of about 50 to 100 μm, and is placed on a film 37. Here, as the thermosetting adhesive 38, an adhesive that cures at a temperature 0 to 50 ° C. higher than the set temperature of the burn-in test of 80 to 150 ° C. is used. In the present embodiment, the bond high chip H
T-100L (base resin: hardener = 4: 1) (Konishi Co., Ltd.)
Was used. Further, a highly flat aluminum plate (weighing about 2.5 kg) is placed on the ring 31 as a weight (not shown).

After completion of the above-mentioned preparation step, the temperature (80 to 150 ° C.) or higher (for example, 2
The film 37 and the ring 31 are bonded by heating at (00 ° C., 2.5 hours) (FIG. 11B). At this time, since the coefficient of thermal expansion of the silicon rubber sheet 36 is larger than the coefficient of thermal expansion of the film 37, the film 37 adsorbed on the silicon rubber sheet 36 expands by the same amount as the silicon rubber sheet 36. That is, the thermal expansion of the silicon rubber sheet is greater than when the film 37 is simply heated at a temperature equal to or higher than the set temperature (80 to 150 ° C.) in the burn-in test, and the polyimide film expands more due to this stress. When the tension is large, the thermosetting adhesive 3
8 is cured, and the film 37 and the ring 31 are bonded.
Further, since the film 37 on the silicon rubber sheet 36 is adsorbed in a state where the film 37 is uniformly spread without wrinkles, deflections, or looseness, the film 37 can be bonded to the ring 31 without wrinkles, deflection, or looseness. it can. Furthermore, the silicon rubber sheet 36 has high flatness,
Since it has elasticity, the film 37 can be uniformly and uniformly bonded to the bonding surface of the ring 31. The tension of the polyimide film was 0.5 kg / cm ² or more. When the thermosetting adhesive is not used, the film shrinks and the tension is weakened, and the curing time of the adhesive varies depending on the location, so that the adhesive cannot be uniformly and evenly adhered to the bonding surface of the ring.

After completion of the heating and bonding step, the product is cooled to room temperature and contracted to a state before heating. Thereafter, the film 37 outside the ring 31 is cut and removed along the outer periphery of the ring 31 with a cutter to produce a membrane ring (FIG. 11C).

Next, a process of forming the bumps and pads by processing the above-mentioned membrane ring will be described.

First, as shown in FIG. 12A, on the copper foil (Cu) of the film 37 having the structure in which the copper foil and the polyimide film in the membrane ring prepared above are bonded together.
As shown in FIG. 12 (b), Ni is electroplated to make Ni 0.2 to 0.5 μm (a preferable range is 0.1 to 3 μm).
After plating, Au is formed thereon in a thickness of 0.1 to 0.5 μm (preferably 0.5 to 2 μm), and Au / Ni
/ Cu / polyimide film laminated film structure is formed.

Next, as shown in FIG. 12C, a bump hole having a diameter of about 30 μm is formed at a predetermined position of the polyimide film using an excimer laser.

Next, as shown in FIG. 12D, in order to prevent the surface of the uppermost Au film from being plated, a protective film such as a resist is partially replaced with a part of the Au film used as an electrode. Au is applied with a thickness of about 2 to 3 μm on the entire surface except for Au.
Protect the membrane.

Next, one of the electrodes is connected to the uppermost Au film, and Ni or Ni alloy is electroplated on the polyimide film side. By this electroplating, the plating is grown so as to fill the bump hole shown in FIG. 12D, and then spreads isotropically and grows almost hemispherically when reaching the surface of the polyimide film, and Ni or Ni alloy is formed. Is formed. Subsequently, an electroplating layer made of Au having a thickness of 1 to 2 μm is formed on the surface of the bump. Thereafter, although not particularly shown, the protective film is peeled off.

Then, a new resist is applied to the entire surface of the uppermost layer of Au, and the resist other than the portion where the pad is to be formed is removed by exposure and development.
As shown in (e), a resist pattern is formed.

Next, as shown in FIG.
Etch the film with an aqueous solution of iodine and potassium iodide,
The thin Ni film and Cu film existing between Au and Cu are etched with an aqueous solution of ferric chloride and the like, rinsed well, and then the resist is peeled off, as shown in FIG. A pad made of Ni / Cu is formed. At this time, it is preferable to use a spray method for etching, since side etching is small.

Through the above steps, the membrane ring
The bumps and pads are formed, and the membrane ring with bumps is completed.

(Assembling Step) As shown in FIG. 8, the multilayer wiring board 10 with the anisotropic conductive rubber sheet 20 manufactured as described above is used.
Then, the membrane ring ring 30 with bumps was aligned so that the pad electrode 34 did not come off, and then bonded to complete a wafer batch contact board.

(Board Inspection) As shown in FIG. 8, a metal plate 72 is placed on an X / Y / Z table 71 of a vacuum chuck 70, and a wafer batch contact board is positioned thereon and placed thereon. The interior was evacuated by a pump 73 to adsorb them. One of the blocked pads
A clip-type connector 60 was connected to the two blocks, and a tester 80 was connected between the connector 60 and the metal plate 72. In this state, the tester was operated to check open / short and measure the capacitance. Other blocks were similarly tested. In this case, the connector could be easily and quickly connected to the outer peripheral pad of the multilayer wiring board without displacement by the guide portion and the engagement portion.

(Burn-in test) X / Y of vacuum chuck
・ After placing the wafer on the Z table and aligning the pads on the wafer with the bumps of the membrane ring with bumps, place the wafer batch contact board on the wafer,
The interior was evacuated with a vacuum pump to adsorb them. A clip-type connector was connected to one block of the blocked pad, and a tester was connected between the connector and the metal plate. Then put it in the burn-in device
The test was performed in an operating environment of 5 ° C. Other blocks were similarly tested. In this case, the connector could be easily and quickly connected to the outer peripheral pad of the multilayer wiring board without displacement by the guide portion and the engagement portion.

Note that the present invention is not limited to the above-described embodiment, and can be appropriately modified and implemented within the scope of the present invention.

For example, the number of wiring layers in a multilayer wiring board for a wafer batch contact board is not limited to three layers, but can be a desired number (for example, usually two to five layers).

The glass substrate is manufactured by HOYA: NA4
It is not limited to 0, and is a material having the same thermal expansion coefficient as Si or a similar expansion coefficient to Si, and does not generate warpage due to stress.
A material that can be easily formed can be used.
Examples of such materials include ceramic substrates such as SiC, SiN, and alumina, and other glass substrates (for example, NA35, NA45, SD1, SD2 (HOY and above).
A), Pyrex, 7059 (above manufactured by Corning), etc., have almost the same coefficient of thermal expansion (coefficient of thermal expansion as 0.1).
6-5 PPM), nickel ore, etc.)
And a glass ceramics substrate, a resin substrate (in the case of a particularly small substrate), and the like. Glass substrates are inexpensive, easy to process, have high flatness due to high-precision polishing, are transparent and easy to align, and can control thermal expansion depending on the material. Also excellent in nature. In addition, if the glass is non-alkali, there is no adverse effect due to elution of alkali on the surface.

Further, the materials of the pads, bumps, membranes, etc. and the method of forming them are not limited to the above embodiments.

Specifically, as a material for forming the bump,
Nickel (Ni) or a nickel alloy is preferable from the viewpoints of good conductivity, low cost, easy formation, and good durability, but not limited thereto. The method for forming the bump hole is not particularly limited, but it is preferable to use a laser or a photolithography method in consideration of accuracy and economy.

Material for Forming Pad (Conductive Layer), Forming Method,
The thickness and the like can be appropriately selected. Copper (Cu) is preferable from the viewpoint of good conductivity, low cost, and easy formation. The pad may have a laminated structure of a plurality of metal layers, such as Cu, Ni, Cr, Al, Au, and Ag, or a single-layer structure. As a method of forming the pad (conductive layer), a film forming method such as a sputtering method or a vapor deposition method, a plating method such as electroless plating or electroplating, or a method of bonding a copper foil can be used. The thickness of the pad (conductive layer) is desirably about 5 to 35 μm because durability is required.

Also, Au and pad surfaces are formed on the pad surface and the bump surface, respectively.
Electroplating using an Au-Co alloy can be performed instead of plating. In this case, compared to Au (pure gold), Au
-Since the hardness of the Co alloy is higher, wear of the bump and pad surfaces is less. Similar effects can be obtained by forming palladium, rhodium, or an alloy containing such a metal instead of Au or an Au-Co alloy. In electroplating, plating can be performed in a shorter time than in electroless plating, and mechanical strength and adhesion are strong and hard to peel off.
Also, since the plating film can be formed thick,
Good adhesion (contact property) with the contacted part.

[0065]

According to the present invention, a connector can be quickly and easily connected to an outer peripheral pad without displacement. Therefore, in the inspection of the wafer batch contact board and the wafer batch inspection (burn-in inspection device, etc.), the connection work can be made more efficient, and these devices can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a plan view showing a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a connector according to one embodiment of the present invention.

FIG. 3 is a perspective view showing a connection state according to the embodiment of the present invention.

FIG. 4 is a partially enlarged perspective view showing a guide part in the multilayer wiring board according to one embodiment of the present invention;

FIG. 5 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.

FIG. 6 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.

FIG. 7 is a partially enlarged perspective view showing a guide portion in a multilayer wiring board according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing a wafer batch contact board inspection apparatus according to one embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view for explaining the manufacturing process of the multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view for explaining a manufacturing step of the multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view illustrating a step of forming a membrane ring in one embodiment of the present invention.

FIG. 12 is a cross-sectional view of a main part for describing a processing step of a membrane ring in one embodiment of the present invention.

FIG. 13 is a diagram schematically showing a wafer batch contact board.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 Ni / Cu / Cr multilayer wiring layer 2a first layer wiring pattern 3 insulating layer 4 contact hole 5 Ni / Cu / Cr multilayer wiring layer 5a second layer wiring pattern 6 insulating layer 7 contact hole 8a 3 layer Eye wiring pattern 10 Multilayer wiring board 11 Protective insulating film 20 Anisotropic conductive rubber sheet 30 Membrane ring with bump 31 Ring 32 Membrane 33 Bump 34 Pad 35 Aluminum plate 36 Silicon rubber sheet 37 Film 38 Thermosetting adhesive 40 Silicon Wafer 51 Peripheral pad 52 Blocked peripheral pad 53 Guide hole 54 Penetrated guide hole 55 Groove-shaped guide hole 56 Embedded guide pin 57 Convex or concave guide pattern 60 Connector 61 Guide pin 62 Spring 63 Wiring 64 Socket 7 0 Vacuum chuck 71 X, Y, Z table 72 Metal plate 73 Vacuum pump 80 Tester

Claims (8)

[Claims] 1. A multilayer wiring board constituting a part of a wafer batch contact board used for batch testing of a large number of semiconductor devices formed on a wafer, the peripheral area of the multilayer wiring board. A multi-layer wiring board for a wafer batch contact board, provided with a guide portion adjacent to an outer peripheral pad formed in the connector for guiding and positioning when connecting a connector. 2. A multilayer wiring board constituting a part of a wafer batch contact board used for performing a test of a large number of semiconductor devices formed on a wafer at a time, and a peripheral area of the multilayer wiring board. A multilayer wiring board for a wafer batch contact board, wherein outer peripheral pads formed on the substrate are blocked. 3. A multilayer wiring board constituting a part of a wafer batch contact board used for performing a test of a large number of semiconductor devices formed on a wafer at a time, and a peripheral area of the multilayer wiring board. A multi-layer wiring board for a wafer batch contact board, wherein the line widths and line intervals of outer peripheral pads formed on the substrate are standardized. 4. A connector connected to an outer peripheral pad of a multi-layer wiring board constituting a part of a wafer batch contact board, which is used for batch testing of a large number of semiconductor devices formed on a wafer. A connector having an engaging portion that engages or fits with a guide portion formed on the multilayer wiring board. 5. The connector according to claim 4, wherein the connector has a clip structure that can be attached by narrowing the substrate. 6. A multi-layer wiring board constituting a part of a wafer batch contact board used for performing a test of a large number of semiconductor devices formed on a wafer all at once, an outer periphery formed in a peripheral area of the board. A guide portion that plays a role of guiding and positioning when connecting a connector to the blocked outer peripheral pad is provided adjacent to the blocked outer peripheral pad, and the pad is standardized. And a structure of a connector for connection to be connected to the blocked outer peripheral pad, having an engaging portion for engaging or fitting with a guide portion formed on the multilayer wiring board, and The multi-layered wiring board has a clip structure that can be attached by narrowing the multi-layered wiring board. Connection structure wherein the parts and has a structure to be connected engage. 7. A wafer batch contact board inspection apparatus using at least the multilayer wiring board for a wafer batch contact board according to any one of claims 1 to 3 and the connector according to claim 4 or 5. 8. A wafer batch inspection comprising at least a wafer batch contact board having the multilayer wiring board for a wafer batch contact board according to claim 1 and a connector according to claim 4. apparatus.