JP2000164600A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where a junction leak is prevented from occurring, by a method wherein boron of specific concentration or above is introduced into an b-type layer which is located within a range of a depletion layer that extends from the junction surface of a pn junction. SOLUTION: A silicon oxide film 2 is formed on a p-type silicon substrate 1 which includes interstitial oxygen, and a resist pattern 4 with an opening located in a region 3 which serve as an n-type well layer is formed thereon. n-type impurity ions 5 are implanted into the surface of the substrate 1 using the resist pattern 4 as a mask, and then the resist pattern 4 is removed. Then, boron ions 6 are implanted into all the surface of the substrate 1. The substrate 1 is annealed under a prescribed condition, and an n-type well layer 8 and a p-type well layer 9 as deep as prescribed are formed. Furthermore, boron of density above about 1.0×1017 cm3 is introduced into the n-type well layer 8. By this setup, a junction leak can be restrained from occurring even if oxygen deposits 11 are formed inside the n-type well layer 8 and the p-type well layer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which an oxygen precipitate as a gettering site is formed in a silicon substrate.

[0002]

2. Description of the Related Art In order to increase the speed, function, and integration of a semiconductor device, the demand for miniaturization and large-scale integration of individual semiconductor elements used for the semiconductor device is increasing with time. However, when miniaturization of a MOSFET, which is a typical semiconductor element constituting a semiconductor device, is considered, this involves various difficulties.

First, when the channel length is reduced due to miniaturization, the threshold voltage is reduced accordingly (short channel effect). If the threshold voltage of the actually formed element is different from the threshold voltage intended at the time of designing the semiconductor circuit, the element operates differently from the intention of the design, thereby impairing the function of the entire circuit.

Further, since the threshold voltage depends on the processing dimensions of the gate electrode, it is impossible to obtain an element having the intended characteristics even with a slight processing deviation. This is because semiconductor circuits requiring a large number of uniform elements, such as DRAM (Dy
This is extremely inconvenient for the manufacture of a dynamic random access memory.

The reason why the short channel effect occurs is that when the channel length is shortened, the distortion of the electric field at the source and drain electrode portions affects the channel region. This effect is mitigated by increasing the impurity concentration in the substrate region (well region) where the MOSFET is located.

On the other hand, in the case of a logical operation element using a CMOS circuit, an n-channel M
OSFET source / drain and p-channel MOSFET
The latch-up phenomenon that a current penetrates between the source and the drain of T easily occurs. Once the latch-up phenomenon occurs, the current continues to flow, thus impairing the function of the circuit.

Such a latch-up phenomenon is caused by the p-channel MOSFET where the n-channel MOSFET and the p-channel MOSFET
The impurity concentration in each of the n-type well layer and the n-type well layer is increased, and the n-channel MOSFET and the p-channel M
This can be avoided by cutting off electrical interaction between the source and the drain of the OS.

Further, as the degree of integration of a semiconductor device increases, electrons and hole pairs are generated in a silicon substrate due to radioactive substances or α rays originating from cosmic rays, and these charges cause a malfunction of a circuit, called a soft error. A phenomenon occurs.

A logic circuit or DRAM having a memory function
When a soft error occurs in the pn junction, a large amount of electrons and hole pairs are generated in the silicon substrate due to the radiation applied to the pn junction, causing a large current to flow. Information confusion occurs.

[0010] Soft errors can be suppressed by quickly recombining the generated electron and hole pairs. In order to increase the probability of recombination, the impurity concentration of the silicon substrate and the well must be increased.

As described above, when the speed, function and integration of a semiconductor device are increased, there is a demand that the impurity concentration of the substrate and the well must be increased in order to suppress the single channel effect and the soft error. Was.

On the other hand, as the ULSI semiconductor substrate, a wafer formed by the Czochralski (CZ) method is usually used. In the CZ method, silicon is melted in a quartz crucible and pulled up.

However, in this process, oxygen from the quartz crucible dissolves into the melt, and supersaturated oxygen is mixed into the silicon crystal. This oxygen exists at the interstitial position and has the effect of fixing dislocations, and thus has the function of increasing the mechanical strength of the crystal.

This kind of oxygen is used for intrinsic gettering because it coagulates with heat treatment to form oxygen precipitates. That is, the oxygen precipitate functions as a gettering site for capturing heavy metal impurities and the like mixed in during the manufacturing process of the semiconductor device and removing harmful impurities from the element region.

As a result of miniaturization of semiconductor elements to achieve high integration, the manufacturing process has become more sophisticated and complicated.
The chance of contamination by harmful impurities such as heavy metals increases. In addition, high-performance and high-integration of a semiconductor element lowers an allowable concentration of contaminants, and an extremely small amount of contaminants tends to become a problem. Therefore, intrinsic gettering is indispensable in a semiconductor device forming process.

Conventionally, a method has been adopted in which a wafer is subjected to a high-temperature heat treatment to diffuse oxygen on the surface of the substrate outward, and to form an oxygen precipitate deep in the substrate without forming a precipitate on the surface portion.

In order to effectively remove contaminants in the element formation region by intrinsic gettering, it is necessary to form an oxygen precipitate immediately below the element region. The object was formed for the following reason.

That is, since it is difficult to control the formation region of the oxygen precipitate with good control, if the oxygen precipitate is to be formed immediately below the element region, there is a certain probability that the oxygen precipitate is also formed in the element region. This is because, when this oxygen precipitate is formed and reaches the depletion layer formed by the pn junction in the element region, a junction leak occurs, which causes a problem that the normal operation of the semiconductor element is hindered.

On the other hand, the diameter of a semiconductor substrate (wafer) has been increasing to improve productivity. However, it is difficult to uniformly form oxygen precipitates over the entire surface of a large-diameter semiconductor substrate.

When oxygen precipitates are formed non-uniformly in the substrate, there is a certain probability that oxygen precipitates are also formed in the element region, and when this is applied to a depletion layer formed by a pn junction, a junction leak occurs to cause a semiconductor leak. There is a problem that the device can operate normally.

In particular, as a result of our detailed research, the above-described junction leakage appears remarkably when the impurity concentration of the well in which the pn junction is formed becomes a high impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more. Do you get it.

As described above, in order to suppress the single channel effect and the soft error, it is necessary to increase the impurity concentration of the substrate and the well.
The junction leak problem described above becomes more serious as the functionality and integration increase.

[0023]

As described above, in order to effectively remove contaminants in the element formation region by intrinsic gettering, it is necessary to form an oxygen precipitate immediately below the element region. However, if an attempt is made to form an oxygen precipitate immediately below the element region, a problem of junction leakage occurs. Therefore, conventionally, an oxygen precipitate was formed deep in the substrate. Therefore, conventionally, contaminants in the element forming region cannot be effectively removed.

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to effectively prevent contaminants in an element formation region by intrinsic gettering without causing junction leakage. It is to provide a semiconductor device which can be removed.

[0025]

Means for Solving the Problems [Structure] To achieve the above object, a semiconductor device according to the present invention (claim 1)
An oxygen precipitate as a gettering site formed in a silicon substrate and an n-type layer and a p-type layer having an impurity concentration exceeding 1 × 10 ¹⁷ cm ⁻³ , constituting a semiconductor element formed on the silicon substrate. A pn junction formed, and boron introduced into the n-type layer within a depletion layer extending from the junction surface of the pn junction and having a concentration exceeding 1 × 10 ¹⁷ cm ^-3 . It is characterized by.

[Operation] The present inventors have investigated why an oxygen precipitate is formed in an element region and the oxygen precipitate is applied to a depletion layer formed by a pn junction in the element region, thereby causing a junction leak. Investigated in detail.

As a result, the cause of the junction leakage is that a few high-concentration interstitial oxygen atoms existing near the oxygen precipitates are condensed by the heat treatment, and the thermal donor (Thermal Donor: T)
It was clarified that a shallow donor level called D) was formed, and electrons were supplied to the shallow donor level through the “silicon / oxygen precipitate” interface.

TD is a bivalent donor and is known to have a structure shown in FIG. 8 (P. Deaket. Al., Phys, Rev.
B45 p11612 (1992)). At the center of the TD, an oxygen atom is taken in and a bond of Si—O—O—Si is formed.

As a result of a simulation using our molecular orbital method, boron atoms existing in the silicon substrate have a strong bonding force with oxygen atoms, and are positively incorporated into the bond of Si—O—O—Si. It was found that a structure of Si-OBO-Si was formed and the structure of TD was destroyed. At this time, boron is negatively charged and loses the nature of the TD donor.

In forming the TD, interstitial silicon is released. Interstitial silicon launches boron atoms at interstitial sites in the interstitial space and significantly increases the diffusion of boron (NEBCowern et. At., Phys. Rev. Lett., 65 p.
2434 (1990)).

Therefore, if high-concentration boron is introduced into the high-concentration n-type well layer within a range that does not negate the n-type property, when oxygen precipitates are formed in the element region, the oxygen precipitates When high-concentration interstitial oxygen existing in the vicinity is condensed by heat treatment to form TD, interstitial silicon is released, and boron atoms around the interstitial are ejected between the lattices, thereby promoting the diffusion of boron.

The boron atoms launched between the lattices are Si
It is positively incorporated into the bond -OO-Si. At this time, the boron is negatively charged and loses the TD donor properties.

When the nature of the TD donor disappears, the junction leak due to the oxygen precipitate does not occur because the exit of the electron passing through the "silicon / oxygen precipitate" interface to the conduction band is blocked. On the other hand, if the p-type well layer is formed using boron as the p-type impurity, the junction leak due to the oxygen precipitate does not occur here.

Since the diffusion of boron is caused by interstitial silicon released when forming TD,
It is performed consistently only at low temperature and in the vicinity where TD is formed. Therefore, even if the TD is formed during a process in which the high-temperature heat treatment cannot be performed in the latter half of the semiconductor device manufacturing process, it is possible to suppress the junction leak due to the oxygen precipitate without requiring any special heat treatment.

Further, since boron is already used in the semiconductor manufacturing process, its introduction can be achieved without requiring special consideration.

In addition, boron may be introduced following the introduction of an n-type impurity such as phosphorus (P) into a region to be an n-type well layer. Can be done without any additions. That is, the mask used for the introduction of the n-type impurity can be used as it is for the introduction of boron.

In particular, when a semiconductor device having a twin-tub structure for forming an n-type well layer and a p-type well layer is formed, a step of forming a p-type well layer is performed following the step of forming an n-type well layer. Therefore, boron can be introduced into the n-type well layer in conjunction with the boron implantation for forming the p-type well layer.

Therefore, boron can be introduced without adding any process or omitting the conventional process as compared with the conventional method. Therefore, the junction leak due to the oxygen precipitate can be suppressed without complicating the process.

As a result of suppressing the junction leak due to the oxygen precipitate, even if the oxygen precipitate is formed in the element region, the function of the semiconductor element is not impaired. Therefore, it is permitted to form oxygen precipitates immediately below the element region.

Here, the yield of the semiconductor device does not decrease even if oxygen precipitates are formed in the element region due to some probability fluctuation or non-uniformity. Conversely, the effect of intrinsic gettering can be maximized. As a result, the yield of the semiconductor device is improved.

Further, conventionally, the requirement for uniformity of the concentration of oxygen contained in the semiconductor substrate, which has been required to achieve extremely uniform oxygen precipitation, is relaxed. As a result, a large-diameter silicon substrate (wafer) can be used, and manufacturing costs can be reduced.

[0042]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIGS. 1 and 2 show a CMOS having a twin-tub structure according to a first embodiment of the present invention.
FIG. 4 is a process sectional view illustrating the method for manufacturing the FET.

The feature of the CMOSFET of the present embodiment is that oxygen precipitates as gettering sites are formed in a shallower region, which is within 10 μm immediately below the element formation region, as compared with the conventional one, and furthermore, a concentration is formed in the n-type well layer. Is 1 × 10 ¹⁷ cm ^-3
Of boron, which is a p-type impurity, which exceeds that of boron. However, the concentration of boron is at a level that does not extinguish the n-type properties of the n-type well layer.

First, as shown in FIG. 1A, a p-type silicon substrate 1 containing 1.4 × 10 ¹⁸ cm ^{-3 of} interstitial oxygen was used.
A silicon oxide film 2 having a thickness of 100 nm is formed thereon, and a resist pattern 4 having an opening in a region 3 serving as an n-type well layer is formed on the silicon oxide film 2 and then using the resist pattern 4 as a mask. Phosphorus (P) ions 5 are implanted as n-type impurity ions into the substrate surface at an acceleration energy of 150 KeV and a dose of 1.4 × 10 ¹⁴ cm ⁻² . Thereafter, the resist pattern 4 is removed by a known method such as an ashing method.

Next, as shown in FIG. 1B, boron (B) ions 6 are implanted into the entire surface of the substrate at an acceleration energy of 100 ^{KeV and} a dose of 7.0 × 10 ¹³ cm ⁻² .

As a result of the above-described two ion implantations, the region 7 serving as the p-type well layer has boron of 7.0 × 10 ¹³ cm ⁻² , and the region 3 serving as the n-type well layer has 7.0 × 10 ¹³ cm ^−2. 10 ¹³ cm
⁻² boron and 1.4 × 10 ¹⁴ cm ⁻² phosphorus will be implanted respectively.

As described above, the ion implantation process for forming the p-type well layer and the n-type well layer of the present embodiment
Since the lithography step can be omitted in the ion implantation step for forming the p-type well layer, the number of steps can be reduced as compared with the conventional ion implantation step for forming the p-type well layer and the n-type well layer. Accordingly, the number of steps for forming the p-type well layer and the n-type well layer is smaller than that in the related art.

Of course, after phosphorus ions and boron ions are implanted into the region 3 to be the n-type well layer, boron ions may be selectively implanted into the region 7 to be the p-type well layer by using photolithography. This method has an advantage that the boron concentration in the n-type well layer can be set regardless of the boron concentration in the p-type well layer.

Further, since boron is already used in the semiconductor manufacturing process, its introduction can be achieved without requiring special consideration. In the case of this embodiment, the diffusion coefficient of n-type impurity is almost the same as that of boron. No special considerations are required for annealing in the next step because phosphorus having the above formula is used.

Next, as shown in FIG.
Annealing is performed in a nitrogen atmosphere at 30 ° C. for 30 minutes to form an n-type well layer 8 and a p-type well layer 9 having a depth of about 3 μm. The conductive impurity concentration of the n-type well layer 8 and the p-type well layer 9 is approximately 5.0 × 10 ¹⁷ cm ⁻³ ,
Exceeds 1.0 × 10 ¹⁷ cm ^-3 . With such a concentration, the occurrence of the single channel effect and the latch-up phenomenon can be effectively suppressed.

At the time of the above annealing, about 5 μm from the substrate surface
The interstitial oxygen in the region up to m deep diffuses out. On the other hand, in the region 10 deeper than this, since interstitial oxygen is aggregated, an oxygen precipitate 11 having a size of about 100 nm and an octahedral structure surrounded by [111] planes is formed. Such oxygen precipitates 11 function as gettering sites.

Here, the formation of the oxygen precipitate 11 is a stochastic process and cannot be controlled accurately. Therefore, in the prior art, in order to reduce the probability that the oxygen precipitate 11 is formed in the n-type well layer 8 and the p-type well layer 9, before forming the n-type well layer 8 and the p-type well layer 9, By performing heat treatment at 1200 ° C. for several hours, oxygen precipitates were formed in a region at a depth of 50 μm or more from the substrate surface.

The oxygen precipitate formed in such a deep region has a small ability to capture harmful impurities mixed in the element region. On the other hand, the oxygen precipitate 11 of this embodiment is formed up to the vicinity immediately below the n-type well layer 8 and the p-type well layer 9. Therefore, the ability to capture harmful impurities mixed in the element region is large.

The formation of the oxygen precipitate 11 immediately below the n-type well layer 8 and the p-type well layer 9 as in this embodiment means that the n-type well layer 8 and the p-type well layer 9 have a certain probability. This means that the oxygen precipitate 11 is also formed therein.

However, if boron having a concentration exceeding 1.0 × 10 ¹⁷ cm ⁻³ is introduced into the n-type well layer 8 as in this embodiment, the n-type well layer 8 and the p-type The problem of junction leakage does not occur even if oxygen precipitates 11 are formed in the substrate.

Hereinafter, the reason will be described.

First, when boron is not introduced,
A phenomenon that occurs when the oxygen precipitate 11 is formed in the n-type well layer 8 will be described.

FIG. 3 shows the result of examining the relationship between the reverse bias voltage V _{R of the} pn junction and the reverse bias leak current I _R by the n-type well layer 8 into which boron is not introduced and the p-type layer formed therein. FIG.

In FIG. 7A, Aa indicates the case where the oxygen precipitate 11 was formed in a relatively deep portion of the n-type well layer 8, and Ba indicates the case where the oxygen precipitate 11 was not formed. In ()), Ab indicates a leak current when the oxygen precipitate 11 is formed at a relatively shallow position of the n-type well layer 8 and Bb indicates a leak current when the oxygen precipitate 11 is not formed.

As can be seen from the drawing, regardless of the position of the oxygen precipitate, the case where the oxygen precipitate 11 was formed in the n-type well layer 8 containing no boron was larger than the case where the oxygen precipitate 11 was not formed. It can be seen that the reverse bias leak current I _R significantly increases.

FIG. 4 shows the reverse bias leak currents (Aa, Ab) caused by the oxygen precipitates in FIGS. 3A and 3B as a function of the width W of the depletion layer extending below the pn junction. It is a semi-log plot (IW characteristic). Depletion layer width W
Is a linear function of the electric field present in the pn junction. Aa and Ab in FIG. 4 correspond to Aa and Ab in FIG. 3, respectively.

FIG. 5 shows that when the IW characteristic is plotted semilogarithmically, it has linear components (Ca, Cb) and components (Da, Db) proportional to the width W ^1/2 of the depletion layer. It is. Aa and Ab in FIG. 5 are respectively Aa and Ab in FIG.
It corresponds to.

Since the width W of the depletion layer is a linear function of the electric field F existing in the pn junction, the IW characteristic is expressed by the following function.

I _R = _ept · e _fp / (e _pt + e _fp ) ··· Junction leakage current (curves Aa and Ab) e _pt (F) = exp {α _{pt +} β _pt · F} linear component ( Straight line Ca, Cb) e _fp (F) = exp {α _{fp +} β _fp · F ^1/2 }... Component (curve Da, Db) proportional to W ^1/2 ep indicates phonon assist tunneling mechanism, and efp indicates Fre
It turns out to represent the nkel-Poole mechanism.

Further investigation of the temperature dependence of these components revealed that ept is hopping conduction in which electrons travel through the level existing at the interface between oxygen precipitate 11 and silicon, and efp is a shallow divalent Coulomb center, that is, It was found that electrons were emitted from the TD formed near the oxygen precipitate 11.

FIG. 6 is a view showing a junction leak mechanism based on the oxygen precipitate 11 based on the above findings.

When the oxygen precipitate 11 enters the influence of the electric field created under the pn junction, electrons hop between the interface states existing at the interface between the oxygen precipitate 11 and silicon so as to propagate the stepping stone. Also, electrons are supplied from the valence band Ev. It goes without saying that this conduction mechanism becomes more effective as the electric field becomes stronger.

On the other hand, in the vicinity of the oxygen precipitate 11, a high concentration of interstitial oxygen dissolved from the oxygen precipitate 11 exists.
This condenses at a certain probability to become TD. Since the TD is charged to ++, electrons during hopping are strongly attracted, and electrons are emitted to the conduction band Ec from a portion reduced by the potential electric field. Such an electron conduction band Ec
Release causes junction leakage.

From these findings, it is understood that the effect of the electric field is indispensable for the junction leak due to the oxygen precipitate 11.

When the impurity concentrations of the n-type well layer 8 and the p-type well layer 9 increase, the electric field of the pn junction formed here also increases, and the junction leak due to the oxygen precipitate 11 poses a serious threat. In fact, in our experiments, it has been found that when the impurity concentration exceeds 1.0 × 10 ¹⁷ cm ⁻³ , the junction leak significantly occurs.

As demonstrated above, the junction leak due to the oxygen precipitate 11 was (1) at a well concentration of 1.0 × 10 ¹⁷ cm ^-3 or more and (2) TD was generated near the oxygen precipitate. Occurs when.

Incidentally, TD is a divalent donor, and an oxygen atom is incorporated into the center of TD, and Si—O—O—Si
Is formed.

As a result of a simulation using the molecular orbital method of the present inventors, boron atoms existing in silicon
It is clear that it has a strong bond with oxygen atoms, is positively incorporated into the bond Si-OO-Si, forms a structure Si-O-BO-Si, and destroys the TD structure. became.

In forming the TD, interstitial silicon is released. Interstitial silicon launches boron atoms at lattice positions between lattices, significantly increasing boron diffusion.

Therefore, in the step of forming oxygen precipitates 11 by annealing shown in FIG. 1C, high-concentration interstitial oxygen present in the vicinity of oxygen precipitates 11 is condensed by the above-mentioned annealing to reduce TD. Once formed, interstitial silicon will be released.

In the n-type well layer 8 having a high impurity concentration,
Since boron having a high concentration of 5.0 × 10 ¹⁷ cm ⁻³ has been introduced, the released interstitial silicon drives out the surrounding boron atoms between the lattices to promote the diffusion of boron.

This boron atom is positively incorporated into the bond Si—O—O—Si. At this time, the boron is negatively charged and loses the TD donor properties. When the nature of the TD donor disappears, the exit of the electrons passing through the “silicon / oxygen precipitate” interface to the conduction band is blocked, and no junction leak due to the oxygen precipitate 11 occurs. Actually, 1.0 × 1
Experiments have confirmed that when the boron concentration is 0 ¹⁷ cm ^-3, the junction leak due to the oxygen precipitate 11 does not occur.

In this embodiment, the high density (5.0 × 10 ¹⁷⁾
Since the n-type well layer 8 containing boron (cm ⁻³ ) is formed, even if the oxygen precipitate 11 is formed in the n-type well layer 8 as shown in FIG. It is possible to effectively suppress the occurrence of TD having the property of the donor that causes the TD. In addition, since the oxygen precipitate 11 is formed immediately below the n-type well layer 8, the effect of the intrinsic gettering can be maximized.

After the step of FIG. 1C, the process is the same as the conventional process.
First, the silicon oxide film 2 is removed, and then, as shown in FIG.
An element isolation insulating film 12 is formed by wTrench Isolation. The element isolation insulating film 12 is an insulating film such as a silicon oxide film buried in a shallow groove.

Next, as shown in FIG. 2D, after a gate insulating film 13 is formed on the n-type well layer 8 and the p-type well layer 9, the n-type well layer 8 contains an n-type impurity. On the gate electrode 14n made of a polysilicon film and the p-type well layer 9, a gate electrode 14p made of a polysilicon film containing a p-type impurity is formed.

To form such gate electrodes 14n and 14p, first, an undoped polysilicon film having a thickness of 200 nm is formed, and then a resist pattern having an opening in the n-type well layer 8 is formed. Using this as a mask, n
An n-type impurity is selectively introduced into the polysilicon film located on the p-type well layer 8, and after removing the resist pattern, a resist pattern having an opening is formed on the p-type well layer 9, Using this as a mask, p-type impurities are selectively introduced into the polysilicon film located on p-type well layer 9. Note that the order of introduction of the n-type impurity and the p-type impurity may be reversed.

Next, as shown in FIG. 2F, a not-shown resist covering the p-type well layer 9 and the gate electrode 14n
Is used as a mask, p-type impurity ions are selectively implanted into the surface of the n-type well layer 8, then the resist is removed, and then a resist (not shown) covering the n-type well layer 8 and the gate electrode 14p are used as a mask. Then, by implanting n-type impurity ions into the surface of the p-type well layer 9 and subsequently performing annealing, the n-type and p-type impurities are activated, and the p-type source / drain diffusion layers 15p and n-type A source / drain diffusion layer 15n is formed. The annealing at this time also activates the n-type impurity of the gate electrode 14n and the p-type impurity of the gate electrode 14p.

Finally, through a well-known interlayer insulating film deposition step, contact hole opening step, metal wiring setting step, mounting step, etc., the oxygen precipitate 11 as a gettering site is formed within 10 μm immediately below the element formation region. The CMOSFET having the twin tub structure having the above structure is completed. (Second Embodiment) FIG. 7 is a process sectional view showing a method of manufacturing a CMOSFET having a twin tub structure according to a second embodiment of the present invention. 1 and 2 are denoted by the same reference numerals as in FIGS. 1 and 2, and the detailed description is omitted.

This embodiment differs from the first embodiment in the way of introducing boron. That is, in the present embodiment, the process proceeds to the step of forming the gate electrodes 14n and 14p in FIG. 2D without introducing boron into the n-type well layer 8 in the step of FIG. FIG. 7A shows a cross section at this stage.

Next, as shown in FIG. 7B, a not-shown resist covering the p-type well layer 9 and the gate electrode 14n
After implanting boron ions into the n-type well layer 8 using the mask as a mask, annealing is performed.

Here, the boron concentration does not exceed the n-type impurity concentration of the n-type well layer 8 and is in a range of 1.0 × 10 ¹⁷ cm ⁻³ or more, for example, 2.0 × 10 ¹⁷ cm ^−3. Adjust as follows.

The depth of the boron-containing region 16 is set so as to exceed the width of a depletion layer extending from a pn junction formed thereafter. Specifically, it is desirable that the depth be 0.5 μm or more. Note that heat treatment may be performed as necessary to adjust the boron introduction depth.

Since such a method of introducing boron can be performed as a series of steps including the formation of the p-type source / drain diffusion layer 15p in the next step, it is not necessary to add a new step.
Further, such a method for introducing boron is based on p-channel M
Since boron is not introduced into the channel region of the OSFET, the scattering of impurities in the channel region is reduced as compared with the first embodiment, which is advantageous for high-speed operation of the device.

Next, as shown in FIG. 7C, the resist (not shown) and the gate electrode 14n are used as a mask,
After selectively implanting p-type impurity ions into the n-type well layer 8, annealing is performed to form p-type source / drain diffusion layers 15p. The implantation depth is set to 0.1 μm or less, and the impurity concentration is set to 5.0 × 10 ¹⁹ cm ⁻³ or more.

Next, as shown in FIG.
After selectively implanting n-type impurity ions into the n-type well layer 9, annealing is performed to form n-type source / drain diffusion layers 15.
forming n. Subsequent steps are the same as in the first embodiment.

In this embodiment, the same effect as that of the first embodiment can be obtained. Further, since boron is not introduced into the channel region of the p-channel MOSFET, the operation speed of the element can be increased as compared with the first embodiment. can do.

The present invention is not limited to the above embodiment, but includes, for example, the interstitial oxygen concentration of the substrate, the thickness of various films, the types of n-type and p-type impurity ions, the acceleration voltage for ion implantation, The dose, annealing temperature, time, atmosphere, and the like can be appropriately set.

In the above embodiment, the diameter of the substrate (wafer) is not specifically mentioned. However, as described in the section of the operation, according to the present invention, the problem of junction leakage can be obtained even if a large-diameter substrate is used. Therefore, it is desirable to use a large-diameter substrate from the viewpoint of reduction in manufacturing cost.

In the above embodiment, the case of the CMOSFET has been described. However, the present invention is effective regardless of the type of the semiconductor element. In particular, the present invention is effective for semiconductor elements in which high-temperature heat treatment cannot be performed in the latter half of the manufacturing process. The reason is that, as explained in the operation section, the diffusion of boron is T
This is because boron is generated by interstitial silicon released when forming D, and boron diffusion is performed consistently only at a low temperature and in the vicinity of the formation of TD.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0096]

As described in detail above, according to the present invention, it is possible to extinguish the property of TD as a donor which causes a junction leak without causing a junction leak.
By the intrinsic gettering, a semiconductor device capable of effectively removing contaminants in an element formation region can be realized.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing the first half of a method for manufacturing a CMOSFET having a twin-tub structure according to a first embodiment of the present invention;

FIG. 2 is a process sectional view showing the latter half of the method for manufacturing the twin-tub structure CMOSFET according to the first embodiment of the present invention;

[3] The pn junction by n-type well layer not to introduce boron the p-type layer formed on it, shows the results of examining the relationship between the reverse bias voltage V _R and the reverse bias leakage current I _R

FIG. 4 shows the reverse bias leak current (Aa, A
b) as a function of the width W of the depletion layer extending below the pn junction

5 shows that the IW characteristics (Aa, Ab) shown in FIG. 4 have linear components (Ca, Cb) and components (Da, Db) proportional to the width W ^1/2 of the depletion layer. Illustration

FIG. 6 is an energy band diagram showing a junction leak mechanism caused by oxygen precipitates.

FIG. 7 is a process sectional view showing a method for manufacturing a twin-tub structure CMOSFET according to the second embodiment of the present invention.

FIG. 8 is a diagram showing a structure of a TD (Thermal Donor).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... silicon oxide film 3 ... area | region which becomes an n-type well layer 4 ... resist pattern 5 ... phosphorus ion 6 ... boron ion 7 ... area | region which becomes a p-type well layer 8 ... n-type well layer 9 ... p-type Well layer 10 ... Deep region where oxygen precipitate is formed 11 ... Oxygen precipitate 12 ... Element isolation insulating film 13 ... Gate insulating film 14n ... Gate electrode (n-type polysilicon film) 14p ... Gate electrode (p-type polysilicon film) 15n: n-type source / drain diffusion layer 15p: p-type source / drain diffusion layer 16: boron-containing region

Claims (6)

[Claims] An oxygen precipitate as a gettering site formed in a silicon substrate; and a semiconductor element formed on the silicon substrate.
A pn junction formed by an n-type layer and a p-type layer having an impurity concentration exceeding 1 × 10 ¹⁷ cm ⁻³ , and introduced into the n-type layer within a depletion layer extending from the junction surface of the pn junction. And the concentration is 1 × 10 ¹⁷ cm ^-3
A semiconductor device comprising: boron. 2. An oxygen precipitate as a gettering site formed in a silicon substrate, and a semiconductor element formed on the silicon substrate.
A pn junction formed by an n-type layer and a p-type layer having an impurity concentration exceeding 1 × 10 ¹⁷ cm ⁻³ , and introduced into the n-type layer within a depletion layer extending from the junction surface of the pn junction. And n within the above range
A boron having a concentration capable of extinguishing the donor properties of a thermal donor present in the mold layer. 3. The semiconductor device according to claim 1, wherein the oxygen precipitate is formed in a region within a depth of 10 μm or less from a surface of the semiconductor element formation region of the silicon substrate. Semiconductor device. 4. The p-type layer is a p-type source / drain diffusion layer of a p-channel MOSFET, and the n-type layer is an n-type layer on which the p-type source / drain diffusion layer is formed. The semiconductor device according to claim 1 or 2, wherein 5. The semiconductor device according to claim 4, wherein the channel region under the gate electrode of the p-channel MOSFET does not contain boron having a concentration exceeding 1 × 10 ¹⁷ cm ⁻³ . 6. The semiconductor device according to claim 4, wherein said boron is introduced into the whole of said n-type layer.