JP2000163322A - Memory patrolling method and control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability by reinforcing the patrolling of a memory in use by patrolling respective divided memory areas of the memory while discriminating between an in-use state and an unused state. SOLUTION: The memory part 1 is divided into memory areas 7 of the same size. A patrol control circuit 2 patrols memory areas that a system is using in the memory part 1 in timing generated by a timing control circuit 6 according to addresses given by an address counter 3 and memory areas 7 which are currently unused and being to be used newly according to addresses given by an address counter 4. The patrol control circuit 2 outputs an end signal 12 to the timing control circuit 6 after the final address of the memory areas 7 is patrolled. Consequently, the reliability of the memory which is not used can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patrol (inspection) control circuit of a memory device incorporated in an information processing system, and more particularly to a patrol timing of a memory patrol when an unused memory area changes to a use state. Regarding the change function.

[0002]

2. Description of the Related Art In a data processing system, the frequency of occurrence of bit inversion (referred to as a soft error failure) in the storage contents of a memory element due to the influence of cosmic rays, radiation, etc., increases with the increase in the capacity of a main memory. It is getting bigger when I look at it. In the case of a soft error, if a failure of 2 bits or more occurs in a certain unit such as the same byte, it is often impossible to repair the failure.

[0003] There is also a fault that occurs constantly or intermittently not due to cosmic rays, radiation or the like but originally due to a defect in the memory manufacturing stage.

For this reason, during the operation of the information processing apparatus, inspection of all addresses of the memory section is periodically performed independently of normal memory access by software or the like, and a failed part is repaired as much as possible. For a memory that cannot be recovered, a memory patrol function mainly by hardware that reports the fact has been used.

At present, general-purpose computers are provided with a main memory having a memory capacity on the order of gigabytes. According to Japanese Patent Laid-Open No. 9-91206, in the case of a memory of the order of 1 GB, a soft error failure of about 1 bit per day occurs. In a large-sized memory device, it takes several tens of hours to complete patrol for all addresses in the memory unit. For this reason, in a computer with a large capacity memory, the time it takes to recover the soft error that occurred and the time it takes to correct it are currently about the same,
It is necessary to provide an efficient memory patrol method in order to cope with an increase in the amount of memory in the future.

Some measures have been taken to solve such a problem. For example, Japanese Patent Laid-Open No.
A technique has been disclosed in which a memory inspection is performed in a refresh cycle to a RAM memory and a memory patrol is performed without deteriorating system performance.

In Japanese Patent Application Laid-Open No. 6-324954, the memory section is classified into two types based on the contents of use, and one is resident O
A portion where only the read operation is frequently performed, such as a memory area where the S program is stored, and another portion where both the write operation and the read operation are performed, such as a memory area where the user program is stored. In order to perform the efficient memory patrol in consideration of a measure to increase the number of memory patrols to the memory area in comparison with the latter, the former is performed.

However, in the prior art, including the invention described above, the memory is divided into a state in which the memory is used and a state in which the memory is not used, and the memory patrol is performed in consideration of each state. Was not done.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the case of an information processing apparatus having a large amount of memory such as gigabytes, all memories are always used by the system. Not necessarily. For example, there may be a large amount of unused memory area at night, etc., but the current memory patrol is also performed for parts not used by the system without distinguishing it from the used memory area. Therefore, even if a soft error is detected in an unused memory area by a memory patrol and corrected, the data itself has substantially no meaning.

In such a case, if only the memory area used by the system is subjected to the memory patrol, the memory reliability of the area can be improved.

If a memory patrol is performed only on an area that is being used, if a memory area in which no read / write operation has been performed by software or has not been used for a long time is newly used, Conversely, the problem that the reliability of the memory area is low occurs.

For this reason, according to the present invention, when starting to use a memory area which has not been used and has not been subjected to a memory patrol, the number of memory patrols to the memory area is increased as compared with the memory area which is already in use. Such considerations are also given.

[0013]

According to a first aspect of the present invention, there is provided a memory patrol method for a memory patrol function for inspecting a memory of a main memory of an information processing apparatus, wherein the memory of the main memory is assigned to a plurality of memory areas. It is provided that a memory patrol is performed by dividing the memory area and distinguishing between an in-use state used by the system and an unused state not used by the system.

According to a second aspect of the present invention, in the memory patrol method according to the first aspect, the memory patrol function performs a memory patrol on a memory area in which the system is in use and a memory area in an unused state. , No memory patrol is performed.

Further, according to the memory patrol method of the third invention, in the first invention, when the memory area in the unused state is switched to the used state, the number of memory patrols for the memory area is changed to the number of the memory patrol in the already used state. The number of patrols is increased compared to the number of patrols for the memory area.

Further, in the memory patrol method according to a fourth aspect of the present invention, in the first aspect, when a memory area being used by the system is released, the memory area is monitored for an elapsed time, and the monitored time is monitored within the monitored time. And setting the memory area to an unused state when the memory area is not in use.

Further, in the memory patrol method according to the fifth invention, in the first invention, the patrol of the memory in the unused state is performed, and the patrol is performed when the memory area in the unused state is switched to the used state. A user specifies the number of memory patrols for the memory area, the size of the memory area obtained by dividing the memory into the same size, and the number of elapsed time for shifting to the unused memory state, and executes the memory patrol function according to the user.

Further, a memory patrol control circuit according to a sixth aspect of the present invention comprises a memory comprising a main memory, a memory area obtained by dividing the memory into any equal size, a patrol control circuit for inspecting the memory area, An OS that manages a register that indicates the in-use state / unused state of the area as a valid bit string and that represents the memory area as a bit string when the unused memory area changes to the in-use state; and a patrol from the valid bit string An address counter 1 for outputting an address of a memory area to be patroled to the patrol control circuit, an address counter 2 for outputting an address of a memory area to be patroled from the register to the patrol control circuit, and an output from the address counter 2 Address is output from the address counter 1 And a patrol parameters accumulated timing control circuit which instructs the selector provided at the entrance point of the patrol control circuit so as to more preferentially, the setting values for the variable parameters related to memory patrol instructed from the user.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram according to a first embodiment of the present invention.

In this embodiment, a memory unit 1, a patrol control circuit 2, an address counter 3, an address counter 4, a register 5, a timing control circuit 6, a memory area 7, a valid bit string 8, a selector 9, an operating system (OS) 10, select signal 11, end signal 1
2, a register 13, a register 14, a register 15, a patrol parameter 16, and a user 17.

The memory section 1 is a main memory of an information processing apparatus usually composed of a DRAM, and the description will be made assuming a memory capacity of about 1 gigabyte, but the present invention is not limited to this. Note that the memories of the present invention all represent physical memories, and the start address is address 0. In addition, the entire size of the memory is also set in a register or the like, and the above-mentioned constituent elements appropriately refer to the register.

The patrol control circuit 2 performs a patrol to the memory area 7 used by the system according to the address notified from the address counter 3 in the memory unit 1 in accordance with the timing generated from the timing control circuit 6.
In accordance with the address notified from the address counter 4, patrol is performed for the memory area 7 which has been unused and starts to be used anew. When the patrol of the last address of the memory area 7 is completed, the patrol control circuit 2 outputs an end signal 12 to the timing control circuit 6.

The address counter 3 is a memory area 7 that is in use by the system indicated by the valid bit string 8.
Is output to the patrol control circuit 2.

When the memory area 7 in the unused state indicated by the register 5 and newly changed to the used state occurs, the address counter 4 sequentially sends the addresses of the memory area 7 to the patrol control circuit 2. Continue to output. When the patrol of the last address of the patrol to one memory area 7 is completed, the corresponding bit of the memory area 7 of the register 5 is turned off, and the next on bit in the register 5 is searched. If there is, patrol to the memory area 7 is subsequently performed. When all the bits of the register 5 are turned off, the transmission of the address to the patrol control circuit 2 is stopped.

The register 5 indicates which memory area 7 has been newly used. When the memory management function of the OS 10 allocates memory to all or a part of the unused memory area 7, Turned on by the memory management function. The register 5 may be implemented by a main memory or a register.

The timing control circuit 6 notifies the selector 9 of the address to be subjected to the memory patrol output from the address counter 3 and the address counter 4 as the select signal 11 and instructs the selection. As an initial value when the system is started, a select signal 11 for selecting an address of the memory area 7 indicated by the address counter 4 is generated. In addition, O
Check the bit turned on by S10,
The occurrence of the memory area 7 that is newly started to be used notified from 10 is monitored. Further, it also monitors an end signal 12 output from the patrol control circuit 2 when patrol to one memory area 7 ends. The timing control circuit 6 turns on the bit of the register 5 and
When the end signal 12 is generated, a select signal 11 for validating the output from the address counter 4 is generated. Or later,
The output from the address counter 4 is made valid until all the bits of the register 5 are turned off, and the output from the address counter 3 is made valid when all the bits of the register 5 are turned off.

The memory area 7 represents each divided memory area when the memory unit 1 is divided into the same size.
It is assumed that it has a size of 32 megabytes, but is not so limited. However, when the size of the memory 1 is not divisible by the size of the memory area 7, the size of the last memory area 7 of the memory 1 is smaller than the other memory areas 7.

The valid bit string 8 indicates whether each memory area 7 is in use by the system from the head memory area 7 of the memory unit 1 bit by bit sequentially. Indicates a busy state. The on / off control of the bits of the effective bit string 8 is performed by the memory management function of the OS 10. According to the size of the memory area 7, the number of necessary effective bits changes even when the memory 1 has the same capacity, but it is assumed that the memory 1 has a sufficient number of bits to cope with the change.

The OS 10 represents an operating system (basic software). In the present invention, a memory management function for allocating and releasing a memory used in a system (mainly software) in the operating system is an object. Become. (The term OS in the following description means a memory management function.) The OS 10 controls on / off of the bits of the effective bit string 8 and on / off of the bits of the register 5. When the system is started, the OS 10 recognizes the size of the memory area 7 from the contents of the patrol parameter 16 and the start address of each memory area 7 from the overall size of the memory 1 which is not shown but is separately stored. OS 10 based on the size of the memory unit 1
In accordance with the occurrence and disappearance of the program, the system-provided application program, and the user program, which memory area 7 is used by the system and which memory area 7 is in an unused state are identified. On / off control of each bit of the effective bit string 8 corresponding to the memory area 7 is performed. Until the memory area 7 used by the system is released, the unused area is not immediately changed to the unused state. If the memory area 7 is not allocated by the memory management function even after a certain period of time, the state changes to the unused state, and the valid bit string is changed. The corresponding bit of 8 is turned off. When the memory area 7 which has been in the unused state is assigned and the state is changed to the in-use state, the corresponding bits of the register 5 and the effective bit string 8 are turned on.

The select signal 11 is supplied to the timing control circuit 6
Are signals for selecting an address signal from the address counter 3 and an address signal from the address counter 4.

When the patrol control circuit 2 outputs 1
When the patrol of the last address of one memory area 7 is completed, this signal notifies the timing control circuit 6 of the state.

The register 13 includes an identification bit indicating whether or not to execute a memory patrol on the unused memory area 7, and the contents of the patrol parameter 16 are copied by the OS 10 when the system is started.

The register 14 specifies how many times the patrol to the entire memory area 7 is to be continued when the unused memory area 7 is changed during use. Normally, it can be performed a plurality of times to increase the reliability of the newly used memory. When the system is started, the OS 10 copies the contents of the patrol parameters 16.

The register 15 has an OS at system startup.
10, the size of the memory area 7 is copied from the patrol parameter 16.

The patrol parameter 16 holds information required when the memory patrol of the present invention operates, and has the following contents.
It is set on the non-volatile memory via S10. When performing a memory patrol, the memory area 7 is classified into an in-use state and an unused state, and identification information indicating whether or not to perform patrol on the memory area 7 in the unused state. The number of patrols when a memory patrol is performed on the memory area 7 in which the memory patrol is not in use and has been changed to a newly used state. The size of the memory area 7. The elapsed time from when the memory area 7 in use is changed to the unallocated state by the memory management function of the OS 10 due to the end of the program operating on the memory area 7 or the like, until it becomes the memory area 7 in the unused state. The patrol parameter 16 is composed of the above information.

The user 17 sets the patrol parameter 16
Make the settings for

Next, an embodiment (FIG. 1) of the present invention will be described in detail with reference to FIG.

When the system is started, the memory management function of the OS 10 copies the information of the patrol parameters 16 to the registers 13, 14, and 15. As a result, the register 13 has identification information indicating whether or not to perform patrol equivalent to that of the memory that is being used, even if the memory is not being used. In the register 15, the size of the memory area 7 is set to the number of times the patrol to the memory area 7 is continuously performed.

Hereinafter, a case will be described in which patrol is not performed on an unused memory.

Next, when the memory management function allocates the memory to the operation program in the processing at the time of startup, the memory management function turns on the register 5 and the bit of the valid bit string 8 corresponding to the allocated memory area 7. The timing control circuit 6 instructs the selector 9 to select a signal from the address counter 4 immediately after the start.

FIG. 2A shows a state where the memory unit 1 is divided into n memory areas 7. .., Memory area-n in this order. In the figure, the hatched portion indicates that the memory area 7 which has been in the unused state immediately after the start-up has changed to the used state. In the figure, the memory area
If the memory area 1 and the memory area 3 change to the in-use state, the memory management of the OS 10 determines that the register 5 corresponding to the memory area 1 and the memory area 3 and the corresponding bit of the effective bit string 8 (specifically from the left) The first bit and the third bit (hereinafter referred to as bit 1 and bit 3) are turned on.

The address counter 3 detects that bits 1 and 3 of the effective bit string 8 are on, and outputs the head address of the first memory area -1 corresponding to bit 1 to the patrol control circuit 2 first. I do. Similarly, the address counter 4 stores bits 1 and 3 corresponding to the memory areas -1 and -3 in the register 5.
Is turned on, first, the head address of the memory area-1 corresponding to bit 1 is output to the patrol control circuit 2. When obtaining this address, the address counter 3 and the address counter 4 each store
The size of the memory area 7 is extracted from the calculation. The timing control circuit 6 starts address counter 4 immediately after startup.
The patrol control circuit 2 receives the address from the address counter 4 (in this case, the address is the same as that of the address counters 3 and 4), and instructs the selector 9 to select the signal of the memory area-1. Execute. The patrol by the patrol control circuit 2 is performed continuously from the beginning to the end of the memory area-1 according to the addresses sequentially indicated by the address counter 4.

When the patrol of the last address of the memory area-1 is completed, the address counter 4
With reference to the number of patrols to the newly used memory area 7 fetched from the server, if the number of patrols is one, the patrol to the memory area 7 ends,
The bit 1 corresponding to the memory area-1 of the register 5 is turned off. If the number of patrols to the memory area 7 is plural, the number of patrols to that memory area 7
When the last patrol to the memory area-1 is completed, bit 1 of the register 5 is turned off.

Next, since the address counter 4 searches the register 5 and the bit 3 corresponding to the memory area-3 is ON, the size of the memory area 7 is taken out from the register 15 in order to obtain the head address of the memory area 7. calculate. This address is output to the patrol control circuit 2, and the patrol of the memory area-3 is sequentially performed up to the last address of the memory area-3. If it is specified a plurality of times, the same process is executed for that number of times. When the address counter 4 completes patrol of the memory area-3, it turns off bit 3 of the register 5.

Here, all bits of the register 5 are turned off. The timing control circuit 6 receives the end signal 12 from the patrol control circuit 2 indicating the end of patrol of the previous memory area-3, but all bits of the register 5 are off, so that the patrol request from the address counter 3 is validated. .

In the following description, the patrol count value of the register 14 is assumed to be 1 for the sake of simplicity.

The arrows in FIG. 2B indicate the memory area-1 and the memory area- based on the instruction of the address counter 4.
3 shows a conceptual order of the memory patrol for No. 3. FIG. 2C shows memory area-1 and memory area-
The portion 3 is indicated by dots, which indicates that the device is in use. When this condition continues, the address counter 3 determines whether or not the memory area -1 and the memory area 3 based on the valid bit string 8. The patrol address is designated alternately. When the execution of the memory area-1 is completed, the operation proceeds to the memory area-3, and when the patrol of the memory area-3 is completed, the patrol is repeated so as to return to the memory area-1 again.

In this state, as shown in FIG. 2D, during the patrol of the memory area-3 by the address from the address counter 3, the memory area-4 which has been in the unused state until now becomes in the used state. Let's say it has changed. Bits corresponding to the memory area-4 of the register 5 and the effective bit string 8 are turned on by the OS 10.

The address counter 4 detects that the bit 4 corresponding to the memory area-4 on the register 5 is on, and sets the start address of the memory area-4 to the register 15.
And outputs it to the patrol control circuit 2. The timing control circuit 6 detects the bit turned on on the register 5, but the memory area from the patrol control circuit 2
Until the end signal 12 for 3 is generated, the patrol request from the address counter 3 is kept valid. When the patrol to the memory area-3 by the address counter 3 ends, the patrol control circuit 2 sends an end signal 12. When the timing control circuit 6 receives this signal, the patrol request from the address counter 4 is made valid, so that patrol to the memory area-4 by the address counter 4 is started.

FIG. 2 (e) shows a case where the memory area n which has been newly unused is changed to the used state in the patrol state in accordance with the instruction from the address counter 4. When the patrol of the memory area-4 by the address counter 4 is completed, the address counter 4 turns off the corresponding bit 4 of the register 5. Since the bit n corresponding to the memory area-n is on in the register 5 and the end signal 12 of the previous memory area-4 has been generated, the timing control circuit 6 continues to make the patrol request from the address counter 4 valid. to continue. When the patrol of the memory area-n by the address counter 4 is completed, the register 5 has no ON bit as described above, so the timing control circuit 6 selects the patrol request from the address counter 3. At this time, as shown in FIG. 2 (f), memory areas-1, -3, -4,-
Indicates that n has changed to a busy state.

Memory area 7 represented by valid bit string 8
Is released by the memory management function of the OS 10 when the software or the like operating using the memory area 7 ends, and transitions to a state where it is not used. However, there is a case where the memory area 7 is immediately allocated for the start of another software function and returns to the busy state. Therefore, even if the memory area 7 is released by the memory management function, the corresponding bit of the valid bit string 8 is not immediately turned off at that time, but the elapsed time is monitored by the timer of the memory area 7 and the monitoring time is monitored. Only when the busy state does not occur, the OS 10 can turn off the corresponding bit in the valid bit string 8. The time length of the monitoring time can be set from the user 17 to the non-volatile memory by the patrol parameter 16 and
S10 reads the data and sets the timer monitoring time.

By setting the patrol parameter 16, it is possible to execute patrol on an unused memory, which is a feature of the present invention, as in the conventional case. This content is copied to the register 13. At this time, for example, OS10
Sets the used / unused state of the memory area 7 for the valid bit string 8 as described above. If the address counter 4 refers to the contents of the register 13 and the patrol of the unused memory is set to perform the same patrol as that of the used memory, the address counter 4 does not refer to the contents of the register 5 but the top of the memory unit 1. The patrol is executed by a continuous memory address from the memory area 7 to the end of the memory unit 1. When the patrol of the last address of the memory unit 1 is completed, the process returns to the head of the memory unit 1 and the patrol in this form is repeated.

Although not shown, the entire size of the memory 1 is set in a register or the like, and the patrol control circuit 2 recognizes the last address of the memory 1 from the register, and when the patrol of the address is completed, the patrol control circuit 2 becomes unused. When the patrol is not performed for the memory of, the end signal 12 is generated. When patrol is performed on an unused memory in the same manner as a used memory, control is performed so as to return to the start address of the memory 1.

Address counter 3 and address counter 4
Also, the end address in the case of the last memory area 7 of the memory 1 is recognized from the entire size of the memory 1 set in a register or the like, and the final address is determined, and the processing is performed in accordance therewith.

[0056]

As described above, the whole memory is divided into the memory area used by the system and the memory area not used, and the patrol to the memory used is prioritized, and the memory area not used is given priority. Since it is possible to prevent execution of the memory patrol, the patrol of the memory in use can be strengthened, and therefore, there is an effect of improving the reliability of the memory in use. Also, immediately after the unused memory area changes to the busy state, the patrol to the unused memory is temporarily strengthened.
It is possible to ensure the same quality as the memory in use even for the memory in the unused state. Further, it becomes possible for the user to set a variable factor relating to the memory patrol in a convenient form according to the use situation of the user.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a memory use situation diagram showing an example of a memory patrol operation according to the first embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory part 2 Patrol control circuit 3 Address counter 4 Address counter 5 Register 6 Timing control circuit 7 Memory area 8 Effective bit string 9 Selector 10 OS 11 Select signal 12 End signal 13 Register 14 Register 15 Register 16 Patrol parameter 17 User

Claims (6)

[Claims] In a memory patrol function for inspecting a memory of a main storage device in an information processing apparatus, a memory of the main storage device is divided into a plurality of memory areas, and each memory area is used by a system in use state. A memory patrol method characterized by performing a memory patrol while distinguishing unused states that are not being used. 2. The system according to claim 1, wherein the memory patrol function performs a memory patrol on a memory area in use by the system and does not perform a memory patrol on a memory area in an unused state. 2. The memory patrol method according to 1. 3. When the memory area in the unused state is switched to the used state, the number of memory patrols for the memory area is increased as compared to the number of patrols for the memory area already in use. The memory patrol method according to claim 1. 4. When the memory area used by the system is released, the elapsed time of the memory area is monitored, and when the memory area is not used within the monitoring time, the memory area is unused. 2. The memory patrol method according to claim 1, wherein the memory patrol is performed. 5. The presence or absence of patrol of a memory in an unused state, the number of memory patrols for the memory area when the memory area in the unused state is switched to the used state, and a memory obtained by dividing the memory into equal parts A memory patrol method characterized by a user designating the size of an area and the number of elapsed time for shifting to an unused memory state, and executing a memory patrol function in accordance therewith. 6. A memory comprising a main memory, a memory area obtained by dividing the memory into arbitrary equal sizes, a patrol control circuit for inspecting the memory area, and a use state / non-use state of the memory area. An OS that manages a register that represents the memory area as a bit string when the unused memory area is changed to a busy state when represented as a valid bit string, and patrols the address of the memory area to be patroled from the valid bit string. An address counter 1 that outputs the address of the memory area to be patroled from the register to the patrol control circuit; and an address counter 1 that outputs the address output from the address counter 2 to the patrol control circuit.
A timing control circuit that instructs a selector provided at the entry point of the patrol control circuit to take precedence over the address output from the controller, and a patrol parameter that stores a set value of a variable parameter related to a memory patrol specified by a user. A memory patrol control circuit comprising: