JP2000162641A - Liquid crystal display device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a liquid crystal display device which is bright in screen and low in power consumption by solving various problems caused by the shape of an intersection between the scanning line and the display signal line thereby drastically improving manufacturing yield, reducing cost and increasing its aperture ratio. SOLUTION: This device has a pixel substrate 2, in which provided at least are a scanning line 5 connected to a gate electrode 18 of a switching element 8, a pixel electrode 9 connected to a drain electrode 19b, a reference signal line 6 connected to a source electrode 19a, and a gate insulating film 16 that insulates/protects the gate electrode 18 and the scanning line 5 or the reference signal line 6. The gate insulating film 16, at least one a part of the gate electrode 18 the scanning line 5 and the reference signal line 6, contains a first insulating layer 16a which is formed thinner than the periphery of the part and a second insulation layer 16b which is formed on the upper face side of the first insulating layer 16a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal display device provided with a switching element such as a thin film transistor with low power consumption and a method of manufacturing the same.

[0002]

2. Description of the Related Art A liquid crystal display device using a nematic liquid crystal has been widely used for a long time in segment type liquid crystal display devices such as clocks and calculators. Even recently, by utilizing the features such as thinness, light weight, and low power consumption, the market has been broadly expanded as various displays including a word processor, a computer, and a navigation system.

In particular, an active matrix type liquid crystal display device in which pixels are arranged in a matrix using an active element such as a TFT as a switching element is often used.

[0004] Such a liquid crystal display device has the advantages that the thickness (depth) can be significantly reduced, the power consumption is small, and the full-color display is easy as compared with the CRT. Applications and demands are expanding in a wider range of fields such as monitors for monitors, portable televisions, and displays for digital cameras.

[0005] However, the above liquid crystal display device has a CR
Compared to T, the viewing angle is narrower, and the manufacturing cost is 3 to 1
Many companies, universities and research institutes are proposing various methods and competing for the development because they are about 5 times more expensive, and CRT products are replaced by more liquid crystal display devices or new mobile phones. We are working to create electronic devices.

A conventional transmission type active matrix type liquid crystal display device has a light transmitting substrate (active matrix substrate). As shown in FIG. 5, a plurality of pixel electrodes 51 for applying a voltage to a liquid crystal layer (not shown) are formed in a matrix on the active matrix substrate.

As active elements, which are switching means for selectively driving the pixel electrodes 51, thin film transistors (hereinafter referred to as TFTs) 52 are formed on the active matrix substrate and connected to the pixel electrodes 51. .

Further, in order to perform color display, a color filter layer (not shown) for red, green, blue or the like is provided on the active matrix substrate or the other substrate opposite thereto.

In the TFTs 52, the scanning lines 53 are formed on the gate electrodes, and the display signal lines 54 are formed on the source electrodes.
Are connected to each other. The scanning lines 53 and the display signal lines 54 are connected to the pixel electrodes 5 arranged in a matrix.
1 and are arranged so as to be orthogonal to each other.

The driving of the TFTs 52 is controlled by inputting gate signals via the scanning lines 53. Further, the TFTs 52 are connected via the display signal lines 54.
, A data signal (display signal) is input to the pixel electrodes 51 through the TFTs 52.

The drain electrodes of the TFTs 52 ...
The pixel electrodes 51 and the additional capacitors 55 are connected by the drain wiring 57. The electrodes on the other side of the additional capacitors 55 are connected to common wirings 56, respectively.
The additional capacitors 55 have a role of holding a voltage applied to the liquid crystal layer.

In an active matrix type liquid crystal display device, a liquid crystal is usually between 4.5 μm and 5.3 μm on average between the active matrix substrate and a counter substrate facing the active matrix substrate.
m to form a liquid crystal capacitor. The additional capacitors 55 are connected in parallel with the liquid crystal capacitors.

The TFT 52 will be described in more detail.
As shown in FIG. 6 (first prior art), a transparent insulating substrate 6
On 1, a gate electrode 62 is formed, and a gate insulating film 63 is formed so as to cover the gate electrode 62. A semiconductor thin film 64 is formed on the entire upper surface of the gate electrode 62 with the gate insulating film 63 interposed therebetween.

A channel protective film 65 is formed at the upper center of the semiconductor thin film 64. This channel protective film 6
A source electrode 66a made of a microcrystalline n + silicon layer is provided on the source portion side of the semiconductor thin film 5 and the drain electrode 66 also made of a microcrystalline n + silicon layer on the drain portion side.
b is formed.

A metal layer 67a serving as a source wiring (display signal line) 54 (see FIG. 5) is connected to the source electrode 66a, and a drain wiring 57 (see FIG. 5) is connected to the drain electrode 66b. Metal layer 67b is connected.

The surface of the TFT 52 is covered with an interlayer insulating film 68, on which a transparent conductive film serving as the pixel electrode 51 is formed. Pixel electrode 5
A metal layer 67 b serving as the drain wiring 57 of the TFT is connected to the first through a contact hole 69.
Further, on the pixel electrode 51, an alignment film (not shown) for aligning the liquid crystal is formed substantially uniformly over the entire display region.

As the gate insulating film 63, an inorganic thin film such as SiNx (silicon nitride) or SiO ₂ has been used. The silicon nitride film is, for example,
The film is formed to have a thickness of about 300 nm by using the CVD method.

Further, for the gate electrode 62, a material capable of forming an insulating film by anodic oxidation, such as aluminum or tantalum, is used because of its low resistance and high reliability as described later. Many of these materials are increasingly used. When these materials are used for the gate electrode 62, as shown in FIG. 6, the top and side surfaces of the gate electrode 62 are covered with an anodic oxide film 63a,
A multi-layer gate insulating film 70 having a two-layer structure of the anodic oxide film 63a and the gate insulating film 63 is formed, for example.
Details are described in Japanese Patent Publication No. 2538523).

Next, a process for forming such a multilayer gate insulating film 70 will be described with reference to FIGS. 7 (a) to 7 (g).

First, as shown in FIG.
A metal film 72 made of aluminum, tantalum, or the like is formed thereon by a sputtering apparatus or the like.

Next, as shown in FIG.
2 on the resist film 73 by a spin coater or the like.
Is applied.

Then, the resist film 73 is patterned by photolithography to obtain a resist film pattern 73a as shown in FIG. At this time, by setting the heat treatment temperature after the development to be higher, the resist film pattern 73a can have a taper.

Thereafter, the metal film 72 is subjected to chemical treatment or dry etching to form a metal film pattern 72a, adjacent metal film patterns 72b,... As shown in FIG. 7D, and a resist film pattern 73a is formed by chemical treatment. It is removed (FIG. 7E).

Next, as shown in FIG. 7 (f), a part of the surface side of the metal film patterns 72a, 72b,... Is anodized, and an anodic oxide film 74 of Ta ₂ O ₅ or the like is formed on the surface side. Are grown, and the formation of the scanning lines 75a, 75b... Is performed in the conductive portions where the metal film patterns 72a, 72b.

Then, as shown in FIG. 7 (g), an insulating film made of silicon nitride or the like is formed by a CVD (chemical vapor deposition) apparatus or the like so as to cover the scanning lines 75a, 75b. 76, and the scanning lines 75a, 7
5b... A gate insulating film 77 having a two-layer structure of the upper insulating film 76 and the anodic oxide film 74 is formed.

In the liquid crystal display device obtained by such a manufacturing process, there are various failure occurrence modes, and one to three or more of the manufacturing processes are performed so that unnecessary processes and materials are not introduced into the defective product. A total number of inspection processes are provided, and defective products are deleted, reworked, and pseudo-corrected. Nevertheless, the overall yield is as low as 50% to at most 90%, and there are problems such as capital investment, increase in man-hours, and increase in manufacturing defects for the above inspection and repair.

In order to prevent such a reduction in the yield of products, liquid crystal display devices disclosed in, for example, JP-A-5-27264 and JP-A-7-128687 have been proposed.

For example, the liquid crystal display device disclosed in Japanese Unexamined Patent Application Publication No. 7-128687 (second prior art) is different from the above conventional (first prior art) liquid crystal display device in that the display signal line is provided on the opposite substrate. It has a structure formed on the side.
In this structure, as shown in FIG. 8, a scanning line 78 and a display signal line 79 are formed on separate substrates, respectively, and each terminal of each of three switching elements 90 arranged in a matrix is connected to a pixel electrode 91. And a scanning line 78, and also connected to a reference signal line 93 via a connection line 92.

In the liquid crystal display device having such a structure, the scanning lines 78 and the display signal lines 79 do not intersect on a common substrate, so that the rate of occurrence of line defects due to disconnection or short circuit is reduced and the yield can be improved. .

Further, when aluminum or tantalum is used for the scanning line 78, the same defect% of the gate electrode portion can be reduced by 1% by using a two-layer gate insulating film structure using an anodic oxide film.
Since such a structure is expected to be suppressed to less than an order of magnitude, such a structure will significantly increase the overall yield, and it is possible to further reduce the number of inspection processes installed in the manufacturing process of the conventional liquid crystal display device or eliminate the inspection process Becomes

[0031]

However, the liquid crystal display devices of the first and second prior arts have the following problems.

First, the problems of the liquid crystal display device of the first prior art will be described.

In the liquid crystal display device of the first prior art, as the interlayer insulating film 68, a transmission insulating film of SiNx or SiO2
When a film is formed by a CVD method or a sputtering method, irregularities on the surface of a metal film 72 serving as a base are formed on the interlayer insulating film 68.
Will be reflected in much the same way above.

Further, the scanning lines 53 and the display signal lines 5
4 ... on the transparent insulating substrate 61 which is the same substrate,
Are arranged so as to pass around the pixel electrodes 51 arranged in a matrix and to be orthogonal to each other.

Therefore, the scanning lines 53 and the display signal lines 5
4 at the intersection with the scanning line 53 (the gate electrode 6).
2) On the gate insulating film 6 reflecting the step shape
3 and display signal lines 54 are stacked. Therefore,
The structure having such a step shape causes the following problems.

At the intersection between the scanning lines 53 and the display signal lines 54 and near the gate electrode 62, the multi-layer gate insulating film 70
Crack A (or B) as shown in FIG.
4 are easy to break during manufacturing.

The multilayer gate insulating film 70 (interlayer insulating film 6)
8), the display signal lines 54 in the upper layer and the scanning lines 53 in the lower layer are short-circuited to lower the yield.

By forming the gate insulating film 63 in a two-layer structure, defects are significantly reduced. However, the defect rate is still not zero, and the defective rate of the scanning line 53 and the display signal line 54 is several percent or more. In a newly developed large-size or high-definition liquid crystal display device, the number of wirings is increased or the wiring width is reduced. As a result, 10
% To several tens of percent, and high-definition models to be developed in the future tend to further increase the defect rate.
Also, in the gate electrode 62, such a defect occurred at about 0.1% to 1% or more.

In the multi-layer gate insulating film 70 (or the interlayer insulating film 68), new cracks or cracks A and B are liable to be formed over time due to the influence of film formation residual stress, and the commercialization of the film is difficult. Later, defects may occur and reliability is low.

At the intersection of the scanning lines 53 and the display signal lines 54, a particularly large step is formed, so that the alignment process (rubbing process) of the alignment film is disturbed or the electric field from the display signal lines 54 is disturbed. Easily act on the liquid crystal in the vicinity to cause light leakage.

Since the scanning lines 53 and the display signal lines 54 are formed on the same substrate, the yields of the respective steps are substantially multiplied, which also lowers the yield. Normally, it is not strictly related to other steps and the like, but it is assumed that the yields of the forming step up to the scanning lines 53 and the subsequent forming steps of the display signal lines 54 are 80% and 90%, respectively. Total yield is 72
%.

Since the scanning lines 53 and the display signal lines 54 are formed on the same substrate, it is necessary to go through each step in order, and it takes too much time or days to manufacture. For this reason, the in-process stock and the delivery date are lengthened.

By the way, as described above, the gate insulating film 63 has a two-layer structure for the following reasons. That is,
When forming the scanning lines 78 by performing chemical treatment or dry etching on the metal film 72, it is difficult to form an ideal tapered shape due to a mixture of a chemical isotropic component and a resist shape effect. That is, for example, as shown in FIG. 7E, a steep portion A is formed on the side wall of the scanning line 78, which deteriorates coverage (coating adhesion of the upper layer), and reduces fineness of the upper layer formed in a later step. Disconnection of the display signal line, which is a thin line, or a lack of the gate insulating film 63 causes an electric leak failure between the scanning line and the display signal line.

Conventionally, in order to prevent this, a two-layer structure in which an anodic oxide film is formed on the surface of the scanning line 78 so as to have rounded corners and an insulating film such as silicon nitride formed thereon. Of the gate insulating film 63 is provided. In addition, the two-layer structure of the gate insulating film 63 has favorable characteristics, such as improved withstand voltage and reliability, a low interface state density with a semiconductor having a low mobile ion density, and a large electric field effect on the semiconductor. Such a two-layer structure is usually used because a TFT can be obtained.

However, when the gate insulating film 63 has a two-layer structure as described above, there is a problem that an additional step or apparatus for forming an anodic oxide film is required. Further, as shown in FIG. 7F, the thickness t3 of the scanning line 75a of the conductive portion after the anodic oxidation is naturally smaller than the thickness t1 of the metal film pattern 72a before the anodic oxidation step, but the thickness of the anode is the difference in thickness. The thickness of the oxidized portion is insulated and oxidized and swells to about twice the thickness.

Therefore, even when the taper shape is gentle, the total step t2 becomes much larger than the film thickness t1 required for the scanning line 75.

Next, problems of the liquid crystal display device of the second prior art will be described.

The liquid crystal display device according to the second prior art includes a scanning line 53 and a display signal line 54 among the above-mentioned problems.
This is effective for a defect caused by the intersection of. Therefore, in the liquid crystal display device of the second prior art, although the defect rate of the gate electrode portion can be somewhat reduced, the same problem as in the first prior art remains.

The uppermost pixel electrode 9 made of ITO
1 and the connection line 92 may be superimposed on the scanning line 78 and the reference signal line 93 (not shown), and the ITO has a higher etching rate at the stepped portion of such a superimposed portion than at the surrounding flat portion. There is a risk of disconnection or a short circuit with another electrode due to lack of the lower gate insulating film 63.

Therefore, in order to solve the above problem, it is conceivable to avoid a superimposed structure of each wiring as shown in FIG. However, when the superposed structure is avoided in this way, the pixel electrode 91 becomes small, and a useless space such as the connection line 92 increases, so that there is a problem that the aperture ratio (effective screen, area ratio) decreases.

Also, in the liquid crystal display device of the second prior art,
The insulating film 63 and the gate electrode portion of the reference signal line 93 have a two-layer structure as in the liquid crystal display device of the first prior art. Further, a pixel electrode 91 or an ITO film may be formed on the insulating film 63 above the scanning line 78 and the reference signal line 93 in some cases.

Therefore, since the liquid crystal display device of the second prior art also has such a two-layer structure, similarly to the liquid crystal display device of the first prior art, the ITO film is formed at the stepped portion at the time of film formation. Is considered to be different from the film formation crystal structure, and the etching rate (etching rate) is different between the two. Then, due to the difference in the etching rate, there arises a problem that the pattern accuracy of the ITO film is deteriorated in the vicinity of the step and the disconnection failure increases.

Further, if the etching time is shortened in order to reduce disconnection defects, short-circuit defects increase in other pattern portions,
Alternatively, if the pixel electrode 91 is made small in order to avoid a short circuit defect, there arises a problem that the aperture ratio decreases.

Further, the liquid crystal display device having the structure of the second prior art is different from the manufacturing process of the liquid crystal display device of the first prior art,
Inspection and defect correction can be simplified, or all inspections can be reduced.However, defective products are removed from the manufacturing process in the post-process or final process as much as no defective products are deleted or reworked. If even a small defect rate is not improved, there is a problem that the process and material loss increase.

The present invention has been made to solve the above problems, and an object of the present invention is to solve various problems caused by the shape of the intersection between a scanning line and a display signal line. Provided is a liquid crystal display device capable of realizing a significant improvement in yield and cost reduction, and realizing low power consumption by increasing the aperture ratio and brightening the screen or reducing the power consumption of the backlight, and a method of manufacturing the same. Is to do.

[0056]

According to a first aspect of the present invention, there is provided a liquid crystal display device comprising: a three-terminal switching element provided in a matrix; and a gate electrode of the switching element. A scanning line, a pixel electrode connected to a drain electrode of the switching element, a reference signal line connected to a source electrode of the switching element, and a gate for insulating and protecting the scanning line or the reference signal line from the gate electrode. A pixel substrate having at least an insulating film, wherein the gate insulating film is formed on the gate electrode;
At least a portion of the first insulating layer formed on the scanning line and the reference signal line is thinner than the periphery thereof, and a second insulating layer formed on an upper surface side of the first insulating layer. I have.

According to the above structure, the gate insulating film is composed of at least the first insulating layer and the second insulating layer provided on the upper surface side of the first insulating layer, and the first insulating layer is formed on the gate electrode. Since at least part of the scanning line and the reference signal line are formed thinner than their surroundings, there is little undulation on the electrode forming surface side of the pixel substrate.

As a result, the step at the edge portion of each electrode is reduced, so that the alignment process is further improved, and the disconnection failure at the step portion where each electrode intersects is reduced. Thereby, the yield can be improved.

Further, since the uniformity of the etching rate of the ITO material is improved, the yield can be further improved.
The pixel electrode can be made large so that the aperture ratio can be improved without lowering the yield by bringing the pixel electrode close to a scanning line or the like or stacking the pixel electrode.

Further, since the step at the edge portion of each electrode is reduced, the process of forming an anodic oxide film, which was conventionally required, can be reduced, and as a result, the entire process can be simplified.

Therefore, the thickness for laminating the first insulating layer for the flattening process can be made smaller than before, the throughput can be reduced, the residual stress (or crack remains) can be reduced, the reliability can be improved, and the dryness can be improved. Etching conditions (selecting several conditions such as gas partial pressure ratio and power for adjusting the etching rate selectivity with the first insulating layer, resist film type, viscosity selection, and coating film thickness) are easy, and processing can be performed with less variation in mass production. .

Although the defects at the gate electrode portion and the step portion of the ITO film are not so large from the beginning, in a production line in which the inspection process and the like are simplified, if the defects are slightly reduced, the effect of improvement in man-hour and material loss is reduced. Can be increased. That is, according to the above configuration, it is possible to reduce defects in the gate electrode portion and the step portion of the ITO film, so that the effect of reducing man-hours and material loss in a production line in which an inspection process or the like is simplified can be increased. Can be.

According to a second aspect of the present invention, in order to solve the above problem, in addition to the configuration of the first aspect, a display signal line connected to a counter electrode of a counter substrate facing the pixel substrate is provided. It is characterized in that it is formed on the counter substrate together with the counter electrode.

According to the above configuration, in addition to the function of the first aspect, the scanning lines and the display signal lines are separately provided on the pixel substrate and the counter substrate, respectively, and do not overlap on the same substrate. This can solve various problems caused when the scanning line and the display signal line overlap.

For example, unlike the case where the scanning line and the display signal line are overlapped, there is no disconnection of the display signal line and no short circuit between the two lines, and the reliability is improved and the yield is improved. .

In addition, there is no defect caused by cracks occurring in the gate insulating film with the lapse of time due to the influence of film formation residual stress or the like at the portion where the scanning line and the display signal line overlap, so that reliability can be improved.

Further, there is no large step at the intersection between the scanning line and the display signal line, and the occurrence of light leakage due to defective alignment processing or the like can be suppressed.

Further, since the scanning lines and the display signal lines are formed on different substrates, the yield can be improved by combining only non-defective products of both substrates on the same substrate. In addition, since the scanning lines and the display signal lines are formed on separate substrates, each process can be separately processed in parallel,
Production time or days are shortened, delivery times are reduced, and wasteful production and stock (or in-process inventory) is reduced.

Since the scanning line and the display signal line are not close to each other, the load capacitance added to each wiring can be reduced, and the signal delay can be reduced. As a result, a material having a specific resistance one rank higher can be used as a wiring material, and the degree of freedom in design increases.

Further, the gate insulating film has at least a first
An insulating layer and a second insulating layer provided on the insulating layer, and the first insulating layer is formed thinner than its periphery on at least a part of the gate electrode, the scanning line, and the reference signal line. Less undulation.

As described above, since the step at the edge portion is reduced, the process of forming the anodic oxide film, which was conventionally required, can be reduced and the entire process can be simplified. As a result, the first insulating layer for the planarization process can be obtained. The thickness required for laminating the layers can be smaller than before, the throughput can be reduced, the residual stress (or crack remaining) can be reduced, the reliability can be improved, and the dry etching conditions (adjustment of the etching rate selectivity with the first insulating layer) Pressure, gas pressure ratio, power, resist film type, viscosity selection, coating film thickness, etc.), and processing can be performed with little variation in mass production. In addition, the orientation treatment is further improved, and disconnection defects at step portions are reduced.

Further, since the uniformity of the etching rate of the ITO material is improved, the yield can be further improved,
The pixel electrode can be made large so that the aperture ratio can be improved without lowering the yield by bringing the pixel electrode close to a scanning line or the like or stacking the pixel electrode.

According to a third aspect of the present invention, in order to solve the above-mentioned problem, in addition to the configuration of the first or second aspect, a part of the pixel electrode is provided at least between the scanning line and the reference signal line. It is characterized in that it is superimposed on one side in a plane.

According to the above configuration, in addition to the function of the first or second aspect, a part of the pixel electrode is planarly overlapped with at least one of the scanning line and the reference signal line. As a result, the size of the pixel electrode can be increased, and as a result, the aperture ratio of the liquid crystal display device can be improved.

According to a fourth aspect of the present invention, in order to solve the above problem, in addition to any one of the first to third aspects, the pixel electrode directly connected to the drain electrode of the switching element is made of ITO ( Indium Tin Oxid
e) wherein the source electrode of the switching element is IT
It is characterized in that it is connected to the reference signal line via a connection wiring made of O.

According to the above configuration, in addition to the function of any one of the first to third aspects, the source electrode and the reference signal line are connected by the material used for the pixel electrode. It can be produced with a simple process without any additional steps. By applying the present invention to the configuration of claim 1 or the like, the disconnection failure rate of ITO is almost eliminated.

The above-described liquid crystal display device according to claims 1 to 4 is manufactured as follows.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: a three-terminal switching element provided in a matrix; and a scanning line connected to a gate electrode of the switching element. A pixel electrode connected to the drain electrode of the switching element, a reference signal line connected to the source electrode of the switching element, a gate insulating film for insulating and protecting the gate electrode and the scanning line or the reference signal line; A method of manufacturing a liquid crystal display device including at least a pixel substrate having at least a gate insulating film, a first insulating layer constituting a gate insulating film, which is thinner than at least part of the gate electrode, the scanning line, and the reference signal line. And the step of:
Forming a second insulating layer constituting the gate insulating film.

According to the above configuration, as in the case of the liquid crystal display device of the first aspect, a flat two-layer gate insulating film is formed, so that the same effect as the configuration of the first aspect is exerted.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device according to the fifth aspect.
Forming a display signal line connected to a counter electrode of the counter substrate facing the pixel substrate together with the counter electrode on the counter substrate.

According to the above arrangement, in addition to the function of claim 5, the display signal line connected to the counter electrode of the counter substrate facing the pixel substrate is formed on the counter substrate together with the counter electrode. Therefore, the same operation as the liquid crystal display device according to the second aspect is achieved.

According to a seventh aspect of the present invention, in order to solve the above-mentioned problems, in addition to the constitution of the fifth or sixth aspect, after forming the first insulating layer, the resist is removed from the first insulating layer. It is characterized in that dry etching is performed by coating and forming on almost the entire surface of the layer.

According to the above configuration, in addition to the function of the fifth or sixth aspect, the surface of the first insulating layer can be easily flattened with less variation in mass production.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising:
The resist has an initial viscosity of 20 to 200 cPs.

According to the above configuration, in addition to the effect of the seventh aspect, by using a resist having an initial viscosity in the range of 20 to 200 cPs, it is possible to easily control the thickness of the resist. Moreover, the initial viscosity of the resist is 20
If the initial step of forming the first insulating layer is about 200 to 500 nm due to the range of about 200 cPs, the surface step of the formed resist film (resin layer) is eliminated and almost flat (the step is 100 nm or less). Can be. Accordingly, the surface of the first insulating film can be flattened to about 100 nm or less by facilitating design, material selection, condition setting, and the like. Prototype experiments confirmed that if the surface step of the first insulating film was 100 nm, disconnection defects and the like on the gate electrode portion could be suppressed to less than 1% and production could be performed at a high yield.

According to a ninth aspect of the present invention, in order to solve the above-mentioned problems, in addition to the configuration of the seventh or eighth aspect, the etching rate of the resist is one of the etching rate of the first insulating layer. It is characterized in that it is about double to 1.3 times.

According to the above configuration, in addition to the function of claim 7 or 8, the etching rate of the resist is, for example, about 1 to 1.3 times the etching rate of the first insulating layer. The film thickness can be controlled well. Thereby, the step on the final surface of the first insulating layer is reduced to zero.
To about 100 nm or more, so that there is no practical problem.

[0088]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
It is as follows.

As shown in FIG. 2, a transmission type liquid crystal display device 1 according to the present embodiment has a structure in which liquid crystal (not shown) is injected between a pixel substrate 2 and a counter substrate 3. .

The counter substrate 3 has several hundred transparent conductive films of the same material and the same width on the surface facing the pixel substrate 2. As described above, it is formed in a substantially stripe shape.

On the pixel substrate 2, a plurality of scanning lines 5 and reference signal lines 6 are formed in a stripe shape in parallel with each other on the surface facing the counter substrate 3. The plurality of reference signal lines 6 are connected to each other by a common wiring 7.

The scanning lines 5 and the reference signal lines 6 are formed of aluminum or the like as described later. Between the scanning lines 5 and the reference signal lines 6, three-terminal switching elements 8 composed of a thin film transistor or the like are arranged in a matrix, and a pixel electrode 9 driven by each switching element 8 is arranged.

As shown in FIG. 1, the switching element 8 has three terminals: a gate electrode 18, a source electrode 19a, and a drain electrode 19b.

The gate electrode 18 has a two-layer structure, and is electrically connected to the scanning line 5 through an electric path S1. The gate electrode 18 is not limited to a two-layer structure, but may have a single-layer structure.

The source electrode 19a is electrically connected to the pixel electrode 9 made of the same material as the source electrode 19a.

Further, the drain electrode 19b is electrically connected to the reference signal line 6 through the electric path S2.

The source electrode 19a and the drain electrode 1
9b may be interchanged with each other.

In the pixel substrate 2 on which the switching elements 8 are formed, a scanning line 5, a reference signal line 6, and a gate electrode 18 are formed on a translucent substrate 10, and the scanning line 5, the reference signal A gate insulating film 16 for insulating and protecting the line 6 and the gate electrode 18 is formed. On the gate insulating film 16, the pixel electrode 9, the source electrode 19 a and the drain electrode 19 b of the switching element 8, and the like are formed.

The gate insulating film 16 includes a first insulating layer 16 a formed at least partially on the scanning line 5, the reference signal line 6, and the gate electrode 18 so as to be thinner than the periphery thereof, and an upper surface of the first insulating layer 16 a. Second insulating layer 16b formed on the side
It has a two-layer structure.

The first insulating layer 16a is formed on the transparent substrate 1
The surface is formed substantially flat so as to cover the scanning line 5, the reference signal line 6, and the gate electrode 18 formed on the zero. The second insulating layer 16b is formed of the first insulating layer 1
6b is formed so that the layer thickness is substantially uniform.

As described above, since the surface of the first insulating layer 16a is formed substantially flat, the surface of the second insulating layer 16b formed thereon is also formed substantially flat.
As a result, the surface of the gate insulating film 16 of the pixel substrate 2 is in a state where there is no practical problem due to the steps caused by the scanning lines 5, the reference signal lines 6, and the gate electrodes 18 formed on the translucent substrate 10.

On the second insulating layer 16b, in addition to the source electrode 19a and the drain electrode 19b, a semiconductor layer 22 made of amorphous silicon or the like, and a source electrode contact layer 28 in contact with the source electrode 19a
a, a drain electrode contact layer 28b in contact with the drain electrode 19b is laminated in a predetermined pattern.

The source electrode 19 a is electrically connected to the pixel electrode 9. When the switching element 8 is turned on, that is, when displaying an image, the source electrode 19 a is connected to the drain electrode 19 b via the semiconductor layer 22. Is electrically connected. That is, an electric signal from the reference signal line 6 is supplied to the pixel electrode 9 via the drain electrode 19b, the semiconductor layer 22, and the source electrode 19a.

The reference signal line 6 is provided at a substantially intermediate position between the pixel electrode 9 and the light-transmitting substrate 10, and has a configuration overlapping the pixel electrode 9. Similarly, the pixel electrode 9
Has a configuration in which the end of the source electrode 19a opposite to the connection end is overlapped with the scanning line 5.

As a result, in the conventional liquid crystal display device, the scanning lines and the reference signal lines are arranged without overlapping the pixel electrodes, so that the scanning lines 5 and the reference signal lines 6 are connected to the pixel electrodes as described above. 9, the area of the pixel electrode 9 can be increased, and as a result, the aperture ratio can be improved.

Even if the pixel electrode 9 made of ITO is superposed on at least the reference signal line 6 or the like, light leakage due to short-circuit or chipping near the step portion of the pixel electrode 9 is almost zero.

Although the scanning line 5 is overlapped on the end of the pixel electrode 9 opposite to the connection end of the source electrode 19a, the present invention is not limited to this. They may be superimposed in the vicinity of the end or in a region corresponding to the display region.

Further, the source electrode 1 of the switching element 8
9a and the reference signal line 6, as shown in FIG.
1 connected. The connection line 11 is formed of an ITO film, and is arranged so as to connect the switching element 8 and the reference signal line 6 with a straight line (not shown) at a substantially shortest distance of 15 μm to 25 μm. As a result, the wiring resistance due to the connection line 11 is suppressed, the effective use area of the pixel electrode 9 is increased, and the aperture ratio is improved.

Since the connection line 11 is made of an ITO film, a new wiring material for connecting the source electrode 19a of the switching element 8 and the reference signal line 6 is not required. Depending on the design, the connection line 11 may be superimposed on the gate insulating film 16, but even in such a case, there is almost no defect such as disconnection.

Further, in the liquid crystal display device 1 having the above configuration, as shown in FIG. 2, the counter electrode 4 and the display signal line (not shown) are continuously formed of the same material and the same width on the counter substrate 3. It is formed integrally. That is, since the scanning line 5 and the display signal line are not formed on the same substrate, the scanning line 5 and the display signal line are separately provided on the pixel substrate 2 and the counter substrate 3, respectively. Do not overlap. This can solve various problems that occur when the scanning line 5 and the display signal line overlap.

For example, unlike the case where the scanning line 5 and the display signal line are overlapped, there is no disconnection of the display signal line or short circuit between the two lines. I do.

Further, since there is no defect caused by the generation of cracks in the gate insulating film 16 with the lapse of time due to the influence of residual stress in film formation at the portion where the scanning line 5 and the display signal line overlap, reliability can be improved. .

Furthermore, there is no large step at the intersection between the scanning line 5 and the display signal line, and it is possible to suppress the occurrence of light leakage due to defective alignment processing or the like.

Further, since the scanning lines 5 and the display signal lines are formed on different substrates, the yield can be improved by combining only non-defective products of the respective substrates, as compared with the case where they are formed on the same substrate. For example, assuming that the yield of the forming process up to the scanning line 5 and the subsequent forming process of the display signal line are 80% and 90%, the total yield is limited to a lower one and becomes 80%. This indicates that the case shown in the prior art is improved by 8%, and the number of non-defective products is increased by more than 10%. On the other hand, when the display signal line is formed on the counter substrate 3 side, the yield is improved from 90% to nearly 100% because there is no lower step.

Further, since the scanning lines 5 and the display signal lines are formed on separate substrates, each process can be performed separately in parallel, shortening the manufacturing time or the number of days, shortening the delivery date, and saving wasteful production and storage. (Or in-process inventory) is also reduced.

Further, since the scanning line 5 and the display signal line are not close to each other, the load capacitance added to each wiring can be reduced, and the signal delay can be reduced. This load capacitance is not limited only by the capacitance between the scanning line 5 and the display signal line, but is 1/6 or less on the scanning line 5 side and 1 on the display signal line side as compared with the conventional structure. Simulations have confirmed that the delay time can be significantly reduced to / 4 or less. This means that a material having a specific resistance one rank higher can be used as a wiring material, and the degree of freedom in design increases.

Further, the gate insulating film 16 comprises at least the first insulating layer 16a and the second insulating layer 1 provided thereon.
6b, and the first insulating layer 16a is
Since at least part of the upper, upper, and lower portions of the scanning line 5 and the reference signal line 6 are formed thinner than their surroundings, there is little undulation of the upper surface.

As described above, since the step at the edge portion is reduced, the process of forming the anodic oxide film, which was conventionally required, can be reduced and the entire process can be simplified. As a result, the first insulating layer for the planarization process can be obtained. The thickness of laminating 16a can be smaller than before, the throughput is small, the residual stress (or crack remaining) can be reduced, the reliability is improved,
Dry etching conditions such as a gas partial pressure ratio and power for adjusting an etching rate selection ratio with the first insulating layer 16a, a resist film type, viscosity selection, and a coating film thickness are easily determined by mass production. Processing can be performed with little variation.

Further, the orientation treatment is further improved, and the disconnection failure at the step portion is reduced. Furthermore, since the uniformity of the etching rate of the ITO material is improved, the yield is further improved, and the pixel electrode 9 is brought closer to the scanning line 5 or the like or stacked to increase the aperture ratio without lowering the yield. 9 can be increased.

Although the counter electrode 4 and the display signal line are formed continuously and integrally with the same material and the same width, the counter electrode composed of a plurality of ITO arranged in a matrix is replaced with a display electrode composed of a thin metal wire. A configuration in which signal lines are connected for each row may be employed.

In the liquid crystal display device 1 having the above configuration, the gate insulating film 16 is formed on almost the entire surface of the pixel substrate 2 including the scanning lines 5, the gate electrodes 18, the reference signal lines 6, and the like. However, it is not limited to this,
For example, it is only necessary to apply the structure of the present invention to a part of the scanning line 5, the gate electrode 18, and the reference signal line 6, and in this case, there is an effect of improving the above-described conventional problem.

The scanning line 5 and the reference signal line 6
It is formed by stacking a Ti (titanium) film on an l (aluminum) film (each film thickness is 50 nm / 20 nm, a total thickness of 250 nm). That is, the scanning line 5 is made of a lower scanning line material 5 made of an Al film formed on the translucent substrate 10.
a and an upper scanning line material 5b composed of a Ti film laminated on the lower scanning line material 5a.
The reference signal line 6 also has a two-layer structure including a lower scanning line material 6a made of an Al film and an upper scanning line material 6b made of a Ti film. In addition, the gate electrode 18 also
Similarly to the reference signal line 6, the lower scanning line material 18a made of an Al film and the upper scanning line material 18b made of a Ti film have a two-layer structure.

Generally, since Al is a low resistance wiring,
The line width can be reduced as compared with other materials. Therefore, the aperture ratio can be improved by forming the scanning lines 5 and the reference signal lines 6 from the Al film. Moreover, Al can be made thinner than other materials, and the first insulating layer 16a can be made thinner to improve the throughput.

The metal film formed on Al may be a metal film formed on an upper layer of the scanning line 5 and the reference signal line 6 to reduce the contact resistance with the pixel electrode 9 made of an ITO film.
Prevention of ITO corrosion by electrolytic corrosion reaction between TO-Al, 1st
Ti is used because it has relatively good adhesion to Al for protecting Al at the time of over-etching of the insulating layer 16a.

Here, the steps of manufacturing the gate insulating film 16 of the pixel substrate 2 having the above configuration will be described with reference to FIGS.
This will be described below with reference to FIG. Here, a case where the gate insulating film 16 is formed over the scanning line 5 will be described. Since the gate insulating film 16 on the reference signal line 6 is formed in the same manner, the description is omitted.

First, the lower scanning line material 5a made of A1 is formed on the pixel substrate 2 by a sputtering device or the like, and Ti is formed thereon.
Is formed, and a scanning line 5 having a two-layer structure is formed on the light-transmitting substrate 10 by photolithography.

Next, as shown in FIG. 3A, the first insulating layer 16a made of silicon nitride is
Is laminated on the entire surface of the light-transmitting substrate 10 to a thickness of, for example, about 300 nm. At this time, the first insulating layer 16a follows the surface shape of the scanning line 5 formed on the translucent substrate 10.
A step d1 (almost 250 nm) is formed on the surface of the substrate.

Then, as shown in FIG. 3B, a resin layer 15 is applied to the entire surface of the first insulating layer 16a by a spin coater, a roll coater, or the like.
It is formed to a thickness of about 3 μm. At this time, of the resin layer 15,
The thickness t2 of the resin film 15a on the scanning line 5 is changed to the peripheral thickness t1.
Smaller and the surface step d2 is 0 (almost no state)
〜100 nm. In this case, the surface step d2
When the value is closer to 0, the etching conditions can be easily set, and the flatness of the processed first insulating layer (16a in FIG. 3D) can be easily obtained. However, if the resin layer 15 is made too thick, for example, 5 μm or more for flattening, the throughput decreases and the control of the film thickness starts to deteriorate. In the case of spin coating, the rotation speed is about 800 to 1500 rpm, and a substantially appropriate shape of the resin film 15a of 1 to 3 μm can be obtained.

Further, as the resin layer 15, it is preferable to use a resist having an initial viscosity in the range of 20 to 200 cPs in order to easily control the film thickness. Since the initial viscosity of the resist is in the range of 20 to 200 cPs, the step at the initial stage of film formation of the first insulating layer 16 a is 200 to 500 cPs.
If it is about nm, the resist film (resin layer 1
5) It is possible to eliminate the surface step and to make it almost flat (step 100 nm or less) and obtain the resin layer 15 having an appropriate thickness of 1 to 3 μm.

Note that the initial viscosity of the resist is 200 c
In the case of Ps or more, a volatile solvent such as acetone or xylene is mixed with the resist before the application of the first insulating layer 16a, and the volatile solvent is evaporated after the application. The same effect as in the case of being in the range of 200 cPs is obtained.

It is preferable to use a photosensitive photoresist as the resin layer 15 for reasons such as improvement in throughput. Furthermore, the positive type is more preferable because unnecessary first insulating layers at the peripheral edge can be removed with high accuracy by batch processing. In the present embodiment, TFR-790 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used. However, a thermosetting resin may be used.

Then, as shown in FIG. 3C, the surface of the resin layer 15 is
To be removed. At this time, the first insulating layer 1 on the scanning line 5
Etching is continued even if the surface of 6a is exposed. In addition,
At this point, the etching may be terminated, and the resin film 15b remaining around the scanning line 5 may be peeled off. However, by continuing the etching, the flatness of the surface of the first insulating layer 16a is improved and the upper layer is removed. It is possible to reduce the residual stress of the laminated film and improve the adhesion.

As a dry etching apparatus, MEA-
600R (manufactured by Tokyo Electron Limited) using O ₂ + CF
Although such a suitable structure was obtained using the system ₄ gas, it is not limited to these devices and materials, however,
It is preferable that the etching rate is equal between the resin layer 15 and the first insulating layer 16a or slightly higher in the resin layer 15 because the film thickness control is better. When the partial pressure of O ₂ gas is 10 to 30% and the gas pressure is set to 150 to 350 Torr,
It has been confirmed that such good etching can be performed, but the conditions are not limited to this.

The surface step d ₁ of the first insulating layer 16 a is 250 nm to 430 nm, and the surface step d _{2 of the} resin film 15 a is
In order to favorably control the film thickness when is 0, the resin layer 1
5, the first insulating layer 16a, for example.
About 1 to 1.3 times the etching rate. Thereby, the step on the final surface of the first insulating layer 16a is reduced to a practically problematic level of 0 nm to 100 nm. Also in terms of suitable throughput and characteristics condition, the first insulating layer 16a step d ₁ of the gate electrode 18 near the initial stage of deposition is from 250 to 380
When designed to be about nm, the surface step d of the resin layer 15
_{Even if 2} is set to 15 nm or less under the worst conditions, the etching rate of the resin layer 15 is set to be about 1 to 1.3 times the etching rate of the first insulating layer 16a, so that the final rate of the first insulating layer 16a is reduced. The surface step can be easily adjusted to a condition of about 100 nm or less. Surface step is 100
At nm, it is confirmed at the prototype level that there is no disconnection of the upper layer such as ITO.

Subsequently, as shown in FIG. 3D, the above etching is continued, and the thickness t3 of the first insulating layer 16a 'on the scanning line 5 is about 10 to 40 nm on average in the substrate. When the etching is completed, there is almost no extra resin layer remaining, and a good state can be obtained.

At this time, when the cross section of the translucent substrate 10 was observed, a crack C as shown in FIG. In this portion, since the residual stress remaining on the surface layer is released, the crack C
If there is no missing part, it is considered that the state is rather stable in terms of stress.

Thereafter, as shown in FIG.
A second insulating layer 16 made of silicon nitride having a thickness of about 0 nm;
By laminating b, the possibility of the above-mentioned loss can be prevented, and the insulation of the scanning line 5 can be stably protected.

Further, the second insulating layer 16a having a substantially flat
Since the insulating layer 16b is formed, the second insulating layer 1
The in-plane variation over the entire surface of the light-transmitting substrate 10 in 6b is also reduced. For this reason, conventionally, an insulating film having a thickness of 200 to 300 nm or more is laminated on the scanning line 5 and the residual stress surface is increased and deteriorated, and there is a fear that the reliability may be reduced. Even if the thickness t4 of the gate insulating film 16 on the substrate 5 is 100 or more tens of nanometers or less, the insulating protection is possible with sufficiently high reliability.

Although the second insulating layer 16b is made of silicon nitride, the present invention is not limited to this. The second insulating layer 16b may be made of silicon oxide or an organic film made of resin. When an organic film is used, the throughput and the like can be further improved by a spin coating method or the like. Conventionally, for the purpose of withstanding the residual stress of the first insulating layer 16a, a thickness of 2 to 3 μm is used.
Although the above organic film was necessary, such a structure requires 1
An organic film having a thickness of about μm may be used, and material costs can be reduced as in the case of an inorganic film.

In this embodiment, an example of a two-layer structure of Ti / A1 is shown as the scanning line 5. However, the present invention is not limited to this, and the total thickness is 460 nm. The film thickness is 50 nm / 340 nm / 7
0 nm), and without using an anodic oxide film.
Even when the first insulating layer 16a having a thickness of 0 nm was formed, the yield and the like were improved.

Further, 50 nm of silicon nitride was
As described above, it is difficult to form the second insulating layer 16b with a thickness of 0 nm or more, but the second insulating layer 16b can be made thicker according to the present invention.

According to the method for manufacturing the pixel substrate 2 as described above, the yield can be significantly improved as compared with the conventional method.
In addition, the number of manufacturing days can be reduced. In particular, since the yield has been improved, a plurality of inspection steps provided so far can be simplified, and profitability can be improved even if a defect is removed in a later step. In addition, due to the reduction in the number of inspection devices, the footprint and the like are improved, and the line design in the manufacturing process of the liquid crystal display device is easier than before.

[Embodiment 2] Another embodiment of the present invention is described below with reference to FIGS. 4 (a) and 4 (b). For convenience of explanation, the first embodiment is described.
The members having the same functions as the members used in are denoted by the same reference numerals, and the description thereof will be omitted.

The liquid crystal display device 1 according to the present embodiment is
Instead of the pixel substrate 2 of the first embodiment, FIG.
As shown in (b), a pixel substrate 32 is provided.

The pixel substrate 32 is obtained by the same manufacturing process as in the first embodiment. The difference from the pixel substrate 2 shown in FIG.
The difference is that the connection line 11 is used in the first embodiment to connect the reference signal line 6 to the reference signal line 6, and the connection line 25 is used in the present embodiment.

That is, the pixel substrate 3 according to the present embodiment
Reference numeral 2 denotes a first insulating layer in which a gate electrode 18 and a reference signal line 6 are formed in parallel with each other on a light-transmitting substrate 10 and cover these, and are planarized in the same manner as in the first embodiment. 16a and a second insulating layer 16b are further laminated.

A semiconductor layer 22 made of amorphous silicon or the like is formed on the second insulating layer 16b formed with good flatness, and a source electrode 19a and a drain electrode 19b made of microcrystalline n + silicon or the like are separated from each other. Are formed.

The source electrode 19a is connected to the reference signal line 6 via a connection line 25 made of ITO or the like, through a through hole 26 penetrating both the first insulating layer 16a and the second insulating layer 16b. . On the other hand, the pixel electrode 9 made of ITO is connected to the drain electrode 19b.

As in the first embodiment, the first insulating layer 1
Cracks D may occur in some places of 6a, and in some cases, the crack D portion shown in FIG. Although not shown, in this embodiment, the scanning line (not shown) and the gate electrode 18 are formed on the same line (sharing the gate electrode function with the scanning line) so that the aperture ratio can be improved.

FIG. 4B shows a cross section of another portion parallel to the cross section of the pixel substrate 32 shown in FIG.

As shown in FIG. 4B, the gate electrode 18
Other than the part, the reference signal line 6 corresponding to the adjacent pixel
A portion 9a of the pixel electrode 9 is superimposed, and the pixel electrode 9 is enlarged near the adjacent reference signal line 6 to improve the aperture ratio. In this case, there was no occurrence of disconnection in the vicinity of the adjacent reference signal line 6 or formation of a constricted pattern due to a difference in etching rate from the periphery.

[0152]

As described above, according to the liquid crystal display device of the present invention, the three-terminal switching element provided in a matrix, the scanning line connected to the gate electrode of the switching element, and the switching element A pixel electrode connected to a drain electrode of the element, a reference signal line connected to a source electrode of the switching element, and a gate insulating film for insulating and protecting the scanning line or the reference signal line from the gate electrode; A first insulating layer formed on the gate electrode, on the scanning line, and on at least a part of the reference signal line so as to be thinner than its periphery, and an upper surface of the first insulating layer. And a second insulating layer formed on the side.

Therefore, since the step at the edge of each electrode is reduced, the alignment process is further improved, and the disconnection failure at the step where each electrode intersects is reduced. Thereby, the yield can be improved.

Therefore, the thickness for laminating the first insulating layer for the flattening process can be smaller than before, the throughput can be reduced, the residual stress (or crack remains) can be reduced, the reliability can be improved, and the dryness can be improved. Etching conditions (selecting several conditions such as gas partial pressure ratio and power for adjusting the etching rate selectivity with the first insulating layer, resist film type, viscosity selection, and coating film thickness) are easy, and processing can be performed with less variation in mass production. This has the effect.

As described above, in the liquid crystal display device according to the second aspect of the present invention, in addition to the configuration of the first aspect, the display signal line connected to the counter electrode of the counter substrate facing the pixel substrate is provided with the counter electrode. And a structure formed on the counter substrate.

Therefore, in addition to the effect of the structure of claim 1, the scanning lines and the display signal lines are separately provided on the pixel substrate and the counter substrate, respectively, and do not overlap on the same substrate. Thereby, there is an effect that various problems that occur when the scanning line and the display signal line are overlapped can be solved.

As described above, in the liquid crystal display device according to the third aspect of the present invention, in addition to the configuration of the first or second aspect, a part of the pixel electrode is connected to at least one of the scanning line and the reference signal line. This is a configuration that is superimposed in a plane.

Therefore, in addition to the effects of the first and second aspects, the pixel electrode is partially superimposed on at least one of the scanning line and the reference signal line in a planar manner. The size of the electrode can be increased, and as a result, the aperture ratio of the liquid crystal display device can be improved.

As described above, in the liquid crystal display device according to the fourth aspect of the invention, in addition to any one of the first to third aspects, the pixel electrode directly connected to the drain electrode of the switching element is made of ITO (Indium Tin). Oxide), and the source electrode of the switching element is connected to the reference signal line via a connection wiring made of ITO.

Therefore, in addition to the effect of any one of the first to third aspects, the source electrode and the reference signal line are connected by the material used for the pixel electrode. There is an effect that it can be produced by a simple process without adding.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, wherein three terminals of a switching element provided in a matrix and a scanning electrode connected to a gate electrode of the switching element are provided. A line, a pixel electrode connected to the drain electrode of the switching element, a reference signal line connected to the source electrode of the switching element, and gate insulation for insulating and protecting the gate electrode and the scanning line or the reference signal line. And a pixel substrate having at least a film, a first insulating layer constituting a gate insulating film thinner than at least a part thereof on the gate electrode, the scanning line, and at least a part of the reference signal line. And a step of forming a second insulating layer constituting the gate insulating film on the upper surface of the first insulating layer. It is.

Therefore, as in the case of the liquid crystal display device of the first aspect of the present invention, a flat two-layer gate insulating film is formed, so that the same effects as those of the first aspect can be obtained.

According to a sixth aspect of the present invention, in addition to the structure of the fifth aspect, in addition to the configuration of the fifth aspect, the display signal line connected to the counter electrode of the counter substrate facing the pixel substrate is provided. The method includes a step of forming on the counter substrate together with the counter electrode.

Therefore, in addition to the effect of the structure of claim 5, the display signal line connected to the counter electrode of the counter substrate facing the pixel substrate is formed on the counter substrate together with the counter electrode. The same effect as that of the liquid crystal display device according to the second aspect is obtained.

As described above, the method of manufacturing the liquid crystal display device according to the seventh aspect of the present invention provides, in addition to the configuration of the fifth or sixth aspect,
After the first insulating layer is formed, a resist is applied to almost the entire surface of the first insulating layer, and dry etching is performed.

Therefore, in addition to the effect of the structure of claim 5 or 6, there is an effect that the surface of the first insulating layer can be easily flattened with less variation in mass production.

The method of manufacturing a liquid crystal display device according to the invention of claim 8 has a structure in which the initial viscosity of the resist is 20 to 200 cPs in addition to the structure of claim 7 as described above.

Therefore, in addition to the effect of the structure of claim 7, by using a resist having an initial viscosity in the range of 20 to 200 cPs, it is possible to easily control the thickness of the resist. .

According to the ninth aspect of the present invention, a method of manufacturing a liquid crystal display device according to
The etching rate of the resist is about 1 to 1.3 times the etching rate of the first insulating layer.

Therefore, in addition to the effect of the structure of claim 7 or 8, the etching rate of the resist is set to, for example, about 1 to 1.3 times the etching rate of the first insulating layer, so that the film thickness is increased. Control can be performed well. Thereby, there is an effect that the step on the final surface of the first insulating layer can be practically eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a configuration of a pixel substrate included in a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a perspective sectional view showing a configuration of a liquid crystal display device including the pixel substrate shown in FIG.

FIGS. 3A to 3E are explanatory views showing a process for manufacturing a gate insulating film on the pixel substrate.

FIGS. 4A and 4B are schematic cross-sectional views illustrating a configuration of a pixel substrate included in a liquid crystal display device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration of a liquid crystal display device including a conventional pixel substrate.

FIG. 6 is a cross-sectional view of a TFT portion of a pixel substrate in a liquid crystal display device.

FIGS. 7A to 7G are explanatory views showing a process of manufacturing a gate insulating film on a pixel substrate provided in a conventional liquid crystal display device.

FIG. 8 is a perspective sectional view showing the configuration of another conventional liquid crystal display device.

[Description of Signs] 5 scanning line 6 reference signal line 8 switching element 9 pixel electrode 16 gate insulating film 16a first insulating layer 16b second insulating layer 18 gate electrode 19a source electrode 19b drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 617U F term (Reference) 2H092 JA21 JA24 JA34 JA37 JB22 JB31 JB69 KB25 MA05 MA07 MA13 MA19 NA07 NA15 NA16 NA19 NA26 NA27 NA29 NA30 PA02 PA08 5C094 AA10 AA22 AA24 AA32. GG15 HK09 HK15 NN12 QQ19 5G435 AA03 AA14 AA16 AA17 BB12 CC09 HH12 HH14 KK05

Claims (9)

[Claims] 1. A three-terminal switching element provided in a matrix, a scanning line connected to a gate electrode of the switching element, a pixel electrode connected to a drain electrode of the switching element, A pixel substrate having at least a reference signal line connected to a source electrode, and a gate insulating film that insulates and protects the scanning line or the reference signal line from the gate electrode, wherein the gate insulating film is formed on the gate electrode; A first insulating layer formed on the scanning line and at least a portion on the reference signal line so as to be thinner than a periphery thereof, and a second insulating layer formed on an upper surface side of the first insulating layer. Liquid crystal display device. 2. The liquid crystal display according to claim 1, wherein a display signal line connected to a counter electrode of the counter substrate facing the pixel substrate is formed on the counter substrate together with the counter electrode. apparatus. 3. The liquid crystal display device according to claim 1, wherein a part of said pixel electrode is planarly overlapped with at least one of said scanning line and said reference signal line. 4. A pixel electrode directly connected to a drain electrode of the switching element is formed of ITO (Indium Tin).
4. The liquid crystal display device according to claim 1, wherein a source electrode of the switching element is connected to the reference signal line via a connection line made of ITO. 5. A switching element having three terminals provided in a matrix, a scanning line connected to a gate electrode of the switching element, a pixel electrode connected to a drain electrode of the switching element, and a switching element of the switching element. A method for manufacturing a liquid crystal display device comprising: a reference signal line connected to a source electrode; and a pixel substrate having at least a gate insulating film for insulating and protecting the gate electrode and the scanning line or the reference signal line. Forming a first insulating layer constituting a gate insulating film thinner than at least a portion thereof on the scanning line and the reference signal line, and forming the gate insulating film on an upper surface of the first insulating layer. Forming a second insulating layer to form a liquid crystal display device. 6. The method according to claim 5, further comprising the step of forming a display signal line connected to a counter electrode of the counter substrate facing the pixel substrate together with the counter electrode on the counter substrate.
The manufacturing method of the liquid crystal display device according to the above. 7. The method according to claim 1, wherein after forming said first insulating layer, a resist is applied and formed on substantially the entire surface of said first insulating layer, and dry etching is performed until the surface of said resist becomes substantially flat. Item 7. The method for manufacturing a liquid crystal display device according to item 5 or 6. 8. The resist has an initial viscosity of 20 to 200.
The method for manufacturing a liquid crystal display device according to claim 7, wherein cPs is used. 9. The method according to claim 1, wherein the etching rate of the resist is the first.
9. The method for manufacturing a liquid crystal display device according to claim 7, wherein the etching rate is about 1 to 1.3 times the etching rate of the insulating layer.