JP2000156373A - Method of forming cvd film - Google Patents
Method of forming cvd filmInfo
- Publication number
- JP2000156373A JP2000156373A JP10329785A JP32978598A JP2000156373A JP 2000156373 A JP2000156373 A JP 2000156373A JP 10329785 A JP10329785 A JP 10329785A JP 32978598 A JP32978598 A JP 32978598A JP 2000156373 A JP2000156373 A JP 2000156373A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- film
- cvd
- electrostatic chuck
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、静電チャックによ
りウエハを保持する形式のＣＶＤ装置を使って、ＣＶＤ
膜を成膜する方法に関し、更に詳細には、パーティクル
がウエハ裏面に付着しないような対策を施した、ＣＶＤ
膜の成膜方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CVD apparatus in which a wafer is held by an electrostatic chuck.
More specifically, the method for forming a film is a CVD method in which particles are prevented from adhering to the back surface of the wafer.
The present invention relates to a method for forming a film.
【０００２】[0002]
【従来の技術】０．２５μm 世代以降の半導体装置で
は、埋め込み能力に優れたＨＤＰ−ＣＶＤ（High Densi
ty Plasma-ＣＶＤ）酸化膜が、配線の層間絶縁膜、特に
シャロー・トレンチ素子分離（Shallow Trench Isolati
on（ＳＴＩ））の埋め込み酸化膜として、採用され始め
ている。2. Description of the Related Art In semiconductor devices of the 0.25 .mu.m or later generation, HDP-CVD (High Density
ty Plasma-CVD) oxide film is used as an interlayer insulating film for wiring, especially for shallow trench isolation (Shallow Trench Isolati).
It has begun to be adopted as an on (STI) buried oxide film.
【０００３】ここで、図１及び図２を参照して、ＨＤＰ
−ＣＶＤ酸化膜を成膜するＨＤＰ−ＣＶＤ装置の構成を
説明する。図１はＨＤＰ−ＣＶＤ成膜装置の構成を示す
模式的断面図、図２はウエハをＨＤＰ−ＣＶＤ成膜装置
から取り出すために、ウエハを静電チャックから離間さ
せたときのＨＤＰ−ＣＶＤ成膜装置の様子を示す模式的
断面図である。ＨＤＰ−ＣＶＤ成膜装置１０は、図１に
示すように、プラズマを生成させる半球状の反応室１２
と、反応室１２の下部に設けられ、ウエハＷを保持する
静電チャック１４を有するウエハステージ１６とを備え
ている。反応室１２の外側半球面には、Ｃｕコイルから
なるＩＣＰソース１８が配置されている。また、反応室
１２の下部には、ＳｉＨ4ガス導入管２０、Ｏ2 ガス導
入管２２、及びＡｒガス導入管２４等が接続され、更
に、真空吸引装置（図示せず）に接続された排気管２６
が接続されている。静電チャック１４には、静電チャッ
ク１４上のウエハＷに低温Ｈｅガスを接触させてウエハ
Ｗを冷却する手段（図示せず）が設けてある。また、静
電チャック１４は、静電チャック１４からウエハＷを上
方に離間させるウエハ昇降機構２８を備えている。図１
中、３０は、装置全体を収容するハウジングである。Here, referring to FIGS. 1 and 2, HDP
The configuration of an HDP-CVD apparatus for forming a CVD oxide film will be described. FIG. 1 is a schematic cross-sectional view showing the configuration of an HDP-CVD film forming apparatus, and FIG. 2 is an HDP-CVD film forming apparatus when the wafer is separated from an electrostatic chuck in order to take out the wafer from the HDP-CVD film forming apparatus. FIG. 3 is a schematic cross-sectional view showing a state of the device. As shown in FIG. 1, the HDP-CVD film forming apparatus 10 includes a hemispherical reaction chamber 12 for generating plasma.
And a wafer stage 16 provided below the reaction chamber 12 and having an electrostatic chuck 14 for holding the wafer W. An ICP source 18 made of a Cu coil is disposed on the outer hemisphere of the reaction chamber 12. Further, a SiH 4 gas introduction pipe 20, an O 2 gas introduction pipe 22, an Ar gas introduction pipe 24, and the like are connected to a lower portion of the reaction chamber 12, and further, an exhaust connected to a vacuum suction device (not shown). Tube 26
Is connected. The electrostatic chuck 14 is provided with a unit (not shown) for cooling the wafer W by bringing a low-temperature He gas into contact with the wafer W on the electrostatic chuck 14. In addition, the electrostatic chuck 14 includes a wafer elevating mechanism 28 that separates the wafer W upward from the electrostatic chuck 14. FIG.
Reference numeral 30 denotes a housing that houses the entire apparatus.
【０００４】ウエハ昇降機構２８は、図２に示すよう
に、静電チャック１４に組み込まれたアクチュエータ
（図示せず）によって駆動されて上下に昇降する３本以
上のロッド３２を静電チャック１４のウエハ保持面に離
隔して備えている。ロッド３２は、セラミクス製の径の
数ｍｍ程度の棒状体である。ウエハＷを静電チャック１
４上に載せる際には、先ず、ウエハ昇降機構２８を動作
させて、ロッド３２を上昇させ、ウエハＷをロッド３２
上に載せる。次いでロッド３２を下降させることによ
り、ウエハＷを静電チャック１４上に載置させることが
できる。また、ウエハＷを静電チャック１４から取り出
す際には、先ず、ウエハ昇降機構２８を動作させて、ロ
ッド３２を上昇させて、ウエハＷを静電チャック１４か
ら上方に離間させる。そして、ウエハＷを反応室１２か
ら取り出す。As shown in FIG. 2, a wafer elevating mechanism 28 drives three or more rods 32, which are driven up and down by an actuator (not shown) incorporated in the electrostatic chuck 14, to move the rod 32 upward and downward. It is provided separately from the wafer holding surface. The rod 32 is a rod-shaped body made of ceramics and having a diameter of about several mm. Wafer W to electrostatic chuck 1
When placing the wafer W on the rod 32, the wafer lifting mechanism 28 is first operated to raise the rod 32.
Put on top. Next, the wafer W can be mounted on the electrostatic chuck 14 by lowering the rod 32. When removing the wafer W from the electrostatic chuck 14, first, the wafer elevating mechanism 28 is operated to raise the rod 32 and separate the wafer W upward from the electrostatic chuck 14. Then, the wafer W is taken out of the reaction chamber 12.
【０００５】次いで、図３（ａ）及び（ｂ）を参照し
て、上述のＨＤＰ−ＣＶＤ成膜装置を使って行うＨＤＰ
−ＣＶＤ・ＳｉＯ2 膜を成膜する際の従来の成膜シーケ
ンスを説明する。図３（ａ）及び（ｂ）は、それぞれ、
従来のＨＤＰ−ＣＶＤ膜の成膜方法を実施した際のＨＤ
Ｐ−ＣＶＤ成膜装置の内部状況を説明するためのＨＤＰ
−ＣＶＤ成膜装置の模式的断面図である。 １）先ず、ウエハを反応室１２に送入する。ウエハの送
入に要する時間は５秒である。 ２）真空吸引装置（図示せず）を駆動して排気管２６を
介して反応室１２を排気し、反応室１２内の圧力を所定
の圧力に減圧にする。減圧に要する時間は１０秒であ
る。 ３）次いで、反応室１２内に１００sccmの流量でＡｒガ
スを導入し、３０００ＷのＲＦ出力でＲＦ電圧を印加し
て、プラズマ放電を開始する。プラズマ放電開始ステッ
プに要する時間は２秒である。Next, referring to FIGS. 3A and 3B, the HDP performed by using the above-described HDP-CVD film forming apparatus
A description will be given of a conventional film forming sequence for forming a CVD / SiO 2 film. FIGS. 3A and 3B respectively show:
HD when a conventional HDP-CVD film forming method is performed
HDP for explaining the internal state of the P-CVD film forming apparatus
FIG. 2 is a schematic sectional view of a CVD film forming apparatus. 1) First, a wafer is fed into the reaction chamber 12. The time required to transfer the wafer is 5 seconds. 2) The vacuum chamber (not shown) is driven to exhaust the reaction chamber 12 through the exhaust pipe 26, and the pressure in the reaction chamber 12 is reduced to a predetermined pressure. The time required for decompression is 10 seconds. 3) Next, Ar gas is introduced into the reaction chamber 12 at a flow rate of 100 sccm, an RF voltage is applied at an RF output of 3000 W, and plasma discharge is started. The time required for the plasma discharge start step is 2 seconds.
【０００６】４）１２０sccmの流量でＯ2 ガスを反応室
１２に導入して、プラズマを安定させ、安定したプラズ
マを反応室１２内に維持する。プラズマを安定させるこ
のステップに要する時間は５秒である。 ５）次いで、８０sccmの流量でＳｉＨ4ガスを反応室１
２に導入すると共にウエハに低温Ｈｅガスを接触させて
ウエハの冷却を開始する。Ｈｅ冷却開始ステップに要す
る時間は１秒である。 ６）続いて、２０００ＷのバイアスＲＦ出力でバイアス
ＲＦ電圧を印加させて静電チャック１４を動作させる。
静電チャック動作開始ステップに要する時間は３秒であ
る。この時点で、ＨＤＰ−ＣＶＤ成膜装置１０の内部
は、図３（ａ）に示すように、ウエハＷは静電チャック
１４に吸引され、反応室１２内には成膜プラズマが安定
して維持されている。4) O 2 gas is introduced into the reaction chamber 12 at a flow rate of 120 sccm to stabilize the plasma and maintain stable plasma in the reaction chamber 12. The time required for this step to stabilize the plasma is 5 seconds. 5) Next, SiH 4 gas was supplied at a flow rate of 80 sccm to the reaction chamber 1.
2 and a low-temperature He gas is brought into contact with the wafer to start cooling the wafer. The time required for the He cooling start step is one second. 6) Subsequently, a bias RF voltage is applied with a bias RF output of 2000 W to operate the electrostatic chuck 14.
The time required for the electrostatic chuck operation start step is 3 seconds. At this point, the wafer W is sucked into the electrostatic chuck 14 in the HDP-CVD film forming apparatus 10 and the film forming plasma is stably maintained in the reaction chamber 12 as shown in FIG. Have been.
【０００７】７）次いで、バイアスＲＦ出力を３５００
Ｗに上げて、ＨＤＰ−ＣＶＤ膜をウエハ上に堆積させ
る。ＨＤＰ−ＣＶＤ膜の成膜ステップに所要時間は、１
００秒である。 ８）成膜後、ＲＦ電圧の出力を２０００Ｗに下げ、Ｓｉ
Ｈ4ガスの導入を停止すると共に、バイアスＲＦ電圧の
印加を停止して、静電チャック１４の動作を停止する。
静電チャックの動作停止ステップに要する時間は２秒で
ある。 ９）次いで、除電ステップに移行する。除電ステップで
は、ＳｉＨ4ガスの導入を停止して、Ｏ2 ガス及びＡｒ
ガスのみの除電プラズマを生成させ、静電チャック１４
の動作を停止した状態で静電チャック１４及びウエハＷ
を一体的に除電プラズマに接触させ、静電チャック１４
及びウエハＷに蓄積した電荷を放電させる。除電ステッ
プの時間は４秒である。このプロセスは、除電プラズマ
プロセスと呼ばれている。この時点で、ＨＤＰ−ＣＶＤ
成膜装置１０の内部は、図３（ｂ）に示すように、ウエ
ハＷは静電チャック１４に吸引されておらず、反応室１
２内にはＯ2 ガス及びＡｒガスのみの除電プラズマが維
持されている。 １０）最後に、Ｏ2 ガス及びＡｒガスの導入を停止し、
ＲＦ電圧の印加を停止する。 １１）次いで、ウエハを反応室１２から取り出す。7) Then, the bias RF output is set to 3500
Raise W to deposit HDP-CVD film on wafer. The time required for the HDP-CVD film forming step is 1
00 seconds. 8) After the film formation, the output of the RF voltage was reduced to 2000 W
The introduction of the H 4 gas is stopped, the application of the bias RF voltage is stopped, and the operation of the electrostatic chuck 14 is stopped.
The time required for the operation stop step of the electrostatic chuck is 2 seconds. 9) Next, the process proceeds to the charge removal step. In the charge removal step, the introduction of the SiH 4 gas is stopped, and the O 2 gas and Ar
The discharge plasma is generated only by the gas, and the electrostatic chuck 14 is generated.
The operation of the electrostatic chuck 14 and the wafer W
Are brought into contact with the static elimination plasma, and the electrostatic chuck 14 is
Then, the electric charges accumulated in the wafer W are discharged. The time of the neutralization step is 4 seconds. This process is called a static elimination plasma process. At this point, HDP-CVD
As shown in FIG. 3B, inside the film forming apparatus 10, the wafer W is not sucked by the electrostatic chuck 14 and the reaction chamber 1
In 2, a discharge plasma of only O 2 gas and Ar gas is maintained. 10) Finally, stop the introduction of O 2 gas and Ar gas,
The application of the RF voltage is stopped. 11) Next, the wafer is taken out of the reaction chamber 12.
【０００８】上述の各ステップの条件を示す一覧表を表
１に示す。従来のＨＤＰ−ＣＶＤ膜の成膜方法のシーケ
ンスでは、高いスループットを目標として成膜シーケン
ス全体のタクトタイムの短時間化を図るために、成膜後
の除電ステップでは、上述のように、プラズマ照射時間
として数秒程度しか確保されていない。Table 1 shows a list showing the conditions of each of the above-mentioned steps. In the sequence of the conventional HDP-CVD film forming method, in order to shorten the takt time of the entire film forming sequence with the goal of high throughput, in the charge removal step after film formation, plasma irradiation is performed as described above. Only a few seconds are secured.
【表１】 [Table 1]
【０００９】[0009]
【発明が解決しようとする課題】しかし、従来のＨＤＰ
−ＣＶＤ膜の成膜方法では、ウエハの裏面に粒径０．２
μm 以上のパーティクルが多数、例えば数百個のレベル
でパーティクルが付着し、後の工程の支障となることが
多かった。このパーティクル付着のために、ＨＤＰ−Ｃ
ＶＤ膜を使用した半導体装置の製品歩留りが低く、生産
性の向上が難しかった。以上の説明では、ＨＤＰ−ＣＶ
Ｄ・ＳｉＯ2 膜の成膜を例にしてパーティクル付着の問
題を説明したが、ＨＤＰ−ＣＶＤ膜の成膜に限らず、静
電チャックによりウエハを保持する形式のＣＶＤ装置を
使って、ＣＶＤ膜を成膜する際には、同じ問題があっ
た。However, the conventional HDP
-In the method of forming a CVD film, a particle size of 0.2
Many particles having a particle size of μm or more, for example, several hundred particles adhere at a level, which often hinders subsequent steps. Because of this particle adhesion, HDP-C
The product yield of the semiconductor device using the VD film is low, and it is difficult to improve the productivity. In the above description, HDP-CV
Although the problem of particle adhesion has been described using the example of forming a D · SiO 2 film as an example, the present invention is not limited to the formation of an HDP-CVD film, and a CVD film of a type in which a wafer is held by an electrostatic chuck is used. The same problem was encountered when forming a film.
【００１０】そこで、本発明の目的は、静電チャックに
よりウエハを保持する形式のＬＰＣＶＤ装置を使って、
ＣＶＤ膜を成膜する際、ウエハ裏面へのパーティクル付
着を低減できるＣＶＤ膜の成膜方法を提供することであ
る。Accordingly, an object of the present invention is to provide an LPCVD apparatus of a type in which a wafer is held by an electrostatic chuck,
An object of the present invention is to provide a method of forming a CVD film, which can reduce the adhesion of particles to the back surface of the wafer when forming the CVD film.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、本発明に係るＣＶＤ膜の成膜方法は、静電チャック
によりウエハを保持する形式のＣＶＤ装置を使って、Ｃ
ＶＤ膜を成膜する方法であって、ウエハを反応室内に送
入し、減圧して反応室内の圧力を安定化するステップ
と、プラズマ放電を開始し、反応室内に安定したプラズ
マを維持するステップと、静電チャックでウエハを保持
し、反応ガスを導入してＣＶＤ膜を成膜するステップ
と、反応ガスの導入を停止すると共に静電チャックのウ
エハ保持動作を停止するステップと、成膜プラズマに代
えて、反応室内に除電プラズマを発生させ、静電チャッ
クの残留電荷を放電させるステップとを備えるＣＶＤ膜
の成膜方法において、残留電荷の放電ステップに続い
て、ウエハを静電チャックから上方に離間させて、除電
プラズマ中にウエハを放置するステップを備え、ウエハ
の残留電荷を放電させることを特徴としている。In order to achieve the above object, a method of forming a CVD film according to the present invention uses a CVD apparatus of a type in which a wafer is held by an electrostatic chuck.
A method for forming a VD film, wherein a step of feeding a wafer into a reaction chamber and stabilizing the pressure in the reaction chamber by reducing the pressure, and a step of starting plasma discharge and maintaining a stable plasma in the reaction chamber Holding a wafer with an electrostatic chuck and introducing a reaction gas to form a CVD film; stopping the introduction of the reaction gas and stopping the wafer holding operation of the electrostatic chuck; Generating a charge-removing plasma in the reaction chamber and discharging the residual charges of the electrostatic chuck, wherein the wafer is lifted from the electrostatic chuck following the discharging step of the residual charges. A step of leaving the wafer in the static elimination plasma to discharge residual charges on the wafer.
【００１２】本発明方法では、ウエハを静電チャックか
ら離間させて、除電プラズマ中に放置することにより、
ウエハから静電気が完全に放電され、ウエハ裏面へのパ
ーティクル付着が十分に抑制される。従来のＣＶＤ膜の
成膜方法では、この放置ステップを設けていないため
に、ウエハ直下の静電気によってウエハの裏面にパーテ
ィクルが付着する。本発明方法では、静電チャックから
ウエハを十分に離間してウエハを除電することにより、
ウエハ裏面へのパーティクル付着を有効に抑制すること
ができる。本発明方法を適用することにより、例えばＨ
ＤＰ−ＣＶＤ・ＳｉＯ2 膜の成膜時に、ウエハ裏面に付
着する粒径０．２μm 以上のパーティクルの数を数個レ
ベルに低減することができる。In the method of the present invention, the wafer is separated from the electrostatic chuck and left in the static elimination plasma.
Static electricity is completely discharged from the wafer, and adhesion of particles to the back surface of the wafer is sufficiently suppressed. In the conventional method of forming a CVD film, since the leaving step is not provided, particles adhere to the back surface of the wafer due to static electricity immediately below the wafer. In the method of the present invention, by sufficiently separating the wafer from the electrostatic chuck and removing the charge on the wafer,
Particle adhesion to the back surface of the wafer can be effectively suppressed. By applying the method of the present invention, for example, H
During the formation of the DP-CVD SiO 2 film, the number of particles having a particle diameter of 0.2 μm or more attached to the back surface of the wafer can be reduced to several levels.
【００１３】ウエハを静電チャックから離間させる際に
は、ＣＶＤ装置の静電チャックに通常設けられているウ
エハ昇降機構を使用して、ウエハを静電チャックから離
間させる。好適には、ウエハの放置ステップでは、ウエ
ハを静電チャックから少なくとも３mm上方に離間させ
て、除電プラズマ中に少なくとも４秒間放置する。本発
明方法は、静電チャックによりウエハを保持する形式の
ＣＶＤ装置を使って、ＣＶＤ膜を成膜する限り制約無く
適用でき、例えばＨＤＰ−ＣＶＤ膜として成膜するＳｉ
Ｏ2 膜、ＳｉＯＦ膜、ＳｉＯＮ膜、ＳｉＮ膜等の成膜に
好適に適用できる。When the wafer is separated from the electrostatic chuck, the wafer is separated from the electrostatic chuck by using a wafer elevating mechanism usually provided in the electrostatic chuck of the CVD apparatus. Preferably, in the leaving step of the wafer, the wafer is left at least 3 mm above the electrostatic chuck and left in the neutralized plasma for at least 4 seconds. The method of the present invention can be applied without limitation as long as a CVD film is formed by using a CVD apparatus of a type in which a wafer is held by an electrostatic chuck, for example, a Si film formed as an HDP-CVD film.
It can be suitably applied to the formation of an O 2 film, a SiOF film, a SiON film, a SiN film, or the like.
【００１４】[0014]
【発明の実施の形態】以下に、実施形態例を挙げ、添付
図面を参照して、本発明の実施の形態を具体的かつ詳細
に説明する。実施形態例 本実施形態例は、ＨＤＰ−ＣＶＤ・ＳｉＯ2 膜の成膜に
本発明に係るＣＶＤ膜の成膜方法を適用した実施形態の
一例であって、図４は、本実施形態例のＨＤＰ−ＣＶＤ
膜の成膜方法を実施した際のＨＤＰ−ＣＶＤ装置の内部
状況を説明するＨＤＰ−ＣＶＤ装置の模式的断面図であ
る。以下のように、除電ステップまで、従来のＨＤＰ−
ＣＶＤ膜の成膜方法と同様にして一連の成膜ステップを
実施する。 １）ウエハＷを反応室１２に送入した後、従来の成膜方
法と同様にしてＨＤＰ−ＣＶＤ・ＳｉＯ2 膜を成膜し、
次いで、ＰＲ出力を低減して、プラズマパワーを減少さ
せる。 ２）静電チャック１４に対するＲＦバイアス電圧の印加
を停止し、静電チャック１４によるウエハ保持を停止さ
せる。その後、成膜プラズマに代えて、反応室１４内に
除電プラズマを発生させ、除電プラズマ中に静電チャッ
ク１４を放置して、静電チャック１４に残留する電荷を
プラズマ中に放電させる。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment Example This embodiment is an example of an embodiment in which the method of forming a CVD film according to the present invention is applied to the formation of an HDP-CVD SiO 2 film, and FIG. HDP-CVD
FIG. 2 is a schematic cross-sectional view of the HDP-CVD apparatus for explaining an internal state of the HDP-CVD apparatus when a method of forming a film is performed. As shown below, the conventional HDP-
A series of film forming steps are performed in the same manner as the CVD film forming method. 1) After transferring the wafer W into the reaction chamber 12, an HDP-CVD SiO 2 film is formed in the same manner as in the conventional film forming method.
Next, the PR power is reduced to reduce the plasma power. 2) The application of the RF bias voltage to the electrostatic chuck 14 is stopped, and the wafer holding by the electrostatic chuck 14 is stopped. Thereafter, instead of the film forming plasma, static elimination plasma is generated in the reaction chamber 14, and the electrostatic chuck 14 is left in the static elimination plasma to discharge the electric charge remaining in the electrostatic chuck 14 into the plasma.
【００１５】次いで、本実施形態例では、 ３）除電プラズマを維持したまま、図４に示すように、
ウエハ昇降機構２８を動作させて、ウエハＷを静電チャ
ック１４から３mmから１cm程度上方に離した状態で、反
応室１２内に１０秒程度放置する。これにより、ウエハ
Ｗに残留する電荷が、除電プラズマ中に放電される。従
来のＨＤＰ−ＣＶＤ膜の成膜方法では、この放置ステッ
プを備えていなかったために、ウエハ直下の静電気によ
ってウエハの裏面にパーティクルが付着していた。本実
施形態例では、静電チャック１４から十分に距離を離し
たウエハＷを離間させ、除電することにより、ウエハＷ
から静電気が完全に放電され、ウエハ裏面へのパーティ
クル付着が抑制される。 ４）その後、ウエハを反応室１２から取り出す。Next, in this embodiment, 3) While maintaining the static elimination plasma, as shown in FIG.
By operating the wafer elevating mechanism 28, the wafer W is left in the reaction chamber 12 for about 10 seconds with the wafer W separated from the electrostatic chuck 14 by about 3 mm to 1 cm above. Thereby, the electric charge remaining on the wafer W is discharged into the static elimination plasma. Since the conventional HDP-CVD film forming method does not include this leaving step, particles adhere to the back surface of the wafer due to static electricity immediately below the wafer. In the present embodiment, the wafer W is separated from the electrostatic chuck 14 by a sufficient distance, and the wafer W is removed by discharging electricity.
Static electricity is completely discharged from the substrate, and the adhesion of particles to the back surface of the wafer is suppressed. 4) Thereafter, the wafer is taken out of the reaction chamber 12.
【００１６】上述の本実施形態例のＨＤＰ−ＣＶＤ膜の
成膜方法の各成膜ステップの条件を表２に示す。本実施
形態例のＨＤＰ−ＣＶＤ膜の成膜方法に従ってＨＤＰ−
ＣＶＤ・ＳｉＯ2 膜を成膜したところ、ウエハ裏面に付
着した粒径０．２μm 以上のパーティクルは数個レベル
であって、従来に比べて大幅に低減できた。Table 2 shows the conditions of each film forming step of the method of forming an HDP-CVD film according to this embodiment. According to the HDP-CVD film forming method of the embodiment, HDP-
When a CVD SiO 2 film was formed, the number of particles having a particle diameter of 0.2 μm or more attached to the back surface of the wafer was at a level of several particles, which was significantly reduced as compared with the conventional case.
【表２】 [Table 2]
【００１７】表１と表２との比較から判るように、本発
明によるウエハの放置ステップの所要時間は、僅かに１
０秒〜２０秒程度であり、成膜工程の全体に対して約１
０％のタクトタイムの増加に止まっている。従って、本
発明の効果を考慮した場合、十分に許容できる時間の追
加であり、本発明方法の適用によってスループットの低
下が懸念されるようなことは生じない。As can be seen from the comparison between Table 1 and Table 2, the time required for the step of leaving the wafer according to the present invention is only 1 unit.
0 to 20 seconds, and about 1 to the entire film forming process.
The tact time has only increased by 0%. Therefore, when the effects of the present invention are taken into consideration, a sufficiently allowable time is added, and there is no possibility that the application of the method of the present invention may lower the throughput.
【００１８】以上、ＨＤＰ−ＣＶＤ成膜法によってＳｉ
Ｏ2 膜を形成する場合に関して述べてきたが、本発明方
法は、ＨＤＰ−ＣＶＤ・ＳｉＯ2 膜の成膜に限らず、例
えばＳｉＯＦ膜、ＳｉＯＮ膜、ＳｉＮ膜等を形成する場
合にもＳｉＯ2 膜同様に適用が可能である。また、ＨＤ
Ｐ−ＣＶＤ膜の成膜に限らず、静電チャックによりウエ
ハを保持する形式のＣＶＤ装置を使ったＣＶＤ膜全般の
成膜に適用できる。As described above, SiP is formed by the HDP-CVD film forming method.
Has been described for the case of forming the O 2 film, the method of the present invention is not limited to the deposition of the HDP-CVD · SiO 2 film, for example an SiOF film, SiON film, SiO 2 even in the case of forming a SiN film or the like It can be applied similarly to the membrane. Also, HD
The present invention can be applied not only to the formation of a P-CVD film but also to the formation of a general CVD film using a CVD apparatus of a type in which a wafer is held by an electrostatic chuck.
【００１９】[0019]
【発明の効果】本発明によれば、残留電荷の放電ステッ
プでは、静電チャックを除電した後、ウエハを静電チャ
ックから離間させて、除電プラズマ中にウエハを放置す
ることにより、スループットの低減を最小限にとどめな
がら、ＨＤＰ−ＣＶＤ酸化膜成膜時に付着する粒径０．
２μm 以上のパーティクルを低減できる。本発明方法を
適用することにより、ＨＤＰ−ＣＶＤ膜を成膜する半導
体装置の製品歩留り及び品質が向上する。According to the present invention, in the step of discharging residual charges, after the electrostatic chuck is neutralized, the wafer is separated from the electrostatic chuck, and the wafer is left in the neutralizing plasma to reduce the throughput. While keeping the minimum, the particle diameter of 0.1 when the HDP-CVD oxide film is formed.
Particles of 2 μm or more can be reduced. By applying the method of the present invention, the product yield and quality of a semiconductor device for forming an HDP-CVD film are improved.
【図１】ＨＤＰ−ＣＶＤ装置の構成を示す模式的断面図
である。FIG. 1 is a schematic sectional view showing a configuration of an HDP-CVD apparatus.
【図２】ウエハを静電チャックから離間させたときのＨ
ＤＰ−ＣＶＤ装置の様子を示す模式的断面図である。FIG. 2 shows the H when the wafer is separated from the electrostatic chuck.
FIG. 2 is a schematic cross-sectional view illustrating a state of a DP-CVD apparatus.
【図３】図３（ａ）及び（ｂ）は、それぞれ、従来のＨ
ＤＰ−ＣＶＤ膜の成膜方法を実施した際のＨＤＰ−ＣＶ
Ｄ装置の内部状況を説明するＨＤＰ−ＣＶＤ装置の模式
的断面図である。FIGS. 3 (a) and 3 (b) show conventional H
HDP-CV when a method for forming a DP-CVD film is performed
It is a typical sectional view of the HDP-CVD apparatus explaining the internal situation of D apparatus.
【図４】実施形態例のＨＤＰ−ＣＶＤ成膜方法を実施し
た際のＨＤＰ−ＣＶＤ装置の内部状況を説明するＨＤＰ
−ＣＶＤ装置の模式的断面図である。FIG. 4 is an HDP illustrating an internal state of the HDP-CVD apparatus when the HDP-CVD film forming method of the embodiment is performed.
FIG. 3 is a schematic cross-sectional view of a CVD apparatus.
１０……ＨＤＰ−ＣＶＤ装置、１２……反応室、１４…
…静電チャック、１６……ウエハステージ、１８……Ｉ
ＣＰソース、２０……ＳｉＨ4ガス導入管２２……Ｏ2
ガス導入管、２４……Ａｒガス導入管、２６……排気
管、２８……ウエハ昇降機構、３０……ハウジング、３
２……ロッド。10 HDP-CVD apparatus, 12 Reaction chamber, 14
... Electrostatic chuck, 16 ... Wafer stage, 18 ... I
CP source, 20: SiH 4 gas inlet tube 22: O 2
Gas introduction pipe, 24 Ar gas introduction pipe, 26 Exhaust pipe, 28 Wafer elevating mechanism, 30 Housing, 3
2 ... Rod.
フロントページの続き Ｆターム(参考） 4M104 DD44 HH20 5F031 CA02 HA16 MA28 NA05 PA26 5F045 AA08 AB31 AB32 AB33 AB34 AC01 AC11 AC16 BB14 DP04 EH11 EJ02 EJ10 EM05 EM10 HA11 5F058 BA20 BC02 BC04 BC08 BC11 BF07 BF23 BF29 BG04 BH16 BJ01 Continued on the front page F term (reference) 4M104 DD44 HH20 5F031 CA02 HA16 MA28 NA05 PA26 5F045 AA08 AB31 AB32 AB33 AB34 AC01 AC11 AC16 BB14 DP04 EH11 EJ02 EJ10 EM05 EM10 HA11 5F058 BA20 BC02 BC04 BC08 BC11 BF07 BF23 BF23 BF23
Claims (4)
式のＣＶＤ装置を使って、ＣＶＤ膜を成膜する方法であ
って、 ウエハを反応室内に送入し、減圧して反応室内の圧力を
安定化するステップと、プラズマ放電を開始し、反応室
内に安定したプラズマを維持するステップと、静電チャ
ックでウエハを保持し、反応ガスを導入してＣＶＤ膜を
成膜するステップと、反応ガスの導入を停止すると共に
静電チャックのウエハ保持動作を停止するステップと、
成膜プラズマに代えて、反応室内に除電プラズマを発生
させ、静電チャックの残留電荷を放電させるステップと
を備えるＣＶＤ膜の成膜方法において、 残留電荷の放電ステップに続いて、ウエハを静電チャッ
クから上方に離間させて、除電プラズマ中にウエハを放
置するステップを備え、 ウエハの残留電荷を放電させることを特徴とするＣＶＤ
膜の成膜方法。1. A method for forming a CVD film by using a CVD apparatus of a type in which a wafer is held by an electrostatic chuck, wherein the wafer is fed into a reaction chamber and decompressed to stabilize the pressure in the reaction chamber. And starting plasma discharge to maintain a stable plasma in the reaction chamber; holding a wafer with an electrostatic chuck; introducing a reaction gas to form a CVD film; Stopping the introduction and stopping the wafer holding operation of the electrostatic chuck,
Generating a discharge plasma in the reaction chamber in place of the deposition plasma, and discharging the residual charge of the electrostatic chuck. A step of leaving the wafer in the charge-removing plasma by separating the wafer upward from the chuck, and discharging the residual charge of the wafer.
Film formation method.
電チャックから少なくとも３mm上方に離間させて、除電
プラズマ中に少なくとも４秒間放置することを特徴とす
る請求項１に記載のＣＶＤ膜の成膜方法。2. The CVD film forming method according to claim 1, wherein, in the step of leaving the wafer, the wafer is left at least 3 mm above the electrostatic chuck and left in the static elimination plasma for at least 4 seconds. Method.
Ｄ）膜であることを特徴とする請求項１に記載のＣＶＤ
膜の成膜方法。3. The method according to claim 1, wherein the CVD film is P-CVD (Plasma-CV).
D) The film according to claim 1, wherein the film is a film.
Film formation method.
ＯＦ膜、ＳｉＯＮ膜及びＳｉＮ膜のいずれかを成膜する
ことを特徴とする請求項３に記載のＣＶＤ膜の成膜方
法。4. A P-CVD film comprising a SiO 2 film and a Si
4. The method according to claim 3, wherein one of an OF film, a SiON film and a SiN film is formed.
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| JP2021108339A (en) * | 2019-12-27 | 2021-07-29 | パナソニックＩｐマネジメント株式会社 | Plasma treatment apparatus, plasma treatment method, and manufacturing method of element chip |
| JP7450512B2 (en) | 2020-10-07 | 2024-03-15 | 東京エレクトロン株式会社 | Substrate processing method and substrate processing apparatus |
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