JP2000156339A - Manufacture of semiconductor device and photolithography method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and photolithography method by which a resist film can be removed without leaving residues in the edge sections of a substrate, at the time of patterning the resist film on the substrate through silylation. SOLUTION: When a resist film is formed in a prescribed pattern in at least the first area of a substrate having the first area and a second area around the first area through silylation, the formation of a silylated product-containing layer on the surfaces of the side walls of a resist film 40 in the second area is prevented by forming crosslinking sections 41 in the surface layers of the side walls by performing exposure treatment LE or, even when the silylated product-containing layers are formed, by removing the layers before forming a silicon oxide-containing layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device and a photolithography method, and more particularly to a method for manufacturing a miniaturized semiconductor device and a photolithography method for transferring a fine pattern.

[0002]

2. Description of the Related Art In recent years, the miniaturization and high integration of semiconductor integrated circuits have progressed to the next generation in three years, and the design rules have been reduced by 70% of the previous generation. Has also been realized. In order to process a semiconductor device finely, for example, the gate width of a gate electrode of a transistor or the DR
It is necessary to reduce the area occupied by capacitors in AM, etc., and also to make the wiring part a multi-layer wiring structure. Is becoming important. As devices such as transistors and capacitors have a complicated structure and become three-dimensional, an interlayer insulating film has become thicker.

[0003] The above miniaturization has advanced the fine processing technology in the manufacturing process of semiconductor devices, and in particular, the technology of transferring a circuit pattern to a photosensitive organic film (photoresist) coated on a wafer surface using light. Has been achieved by increasing the resolution in the photolithography process.

In a photolithography process, the minimum dimension of a pattern that can be exposed and transferred is about the exposure wavelength. Further, when performing exposure transfer, a defocus margin is required due to a step of the substrate, aberration of a lens of the exposure apparatus, etc., but when a pattern is miniaturized to about an exposure wavelength, a defocus amount allowable for pattern formation, that is, a depth of focus. (DOF; De
pth Of Focus) sharply decreases. Further, when the pattern is miniaturized, the contrast of the pattern optical image decreases, and the margin, that is, the exposure margin, for the fluctuation of the exposure amount (effective exposure amount including the reflected light from the underlying substrate) decreases. Therefore, as the miniaturization of semiconductor integrated circuits progresses, it is the current trend that exposure light sources with shorter wavelengths are used.

[0005] Specifically, as the above-mentioned exposure light source,
For pattern transfer of a semiconductor integrated circuit of the 1.0 to 0.5 μm rule, g-line (436 nm) of a mercury lamp or i
Line (365 nm) is used, and i-line is mainly used for pattern transfer according to the 0.35 μm rule. In addition, a technique of exposing using a KrF excimer laser (248.8 nm) has been developed for manufacturing a semiconductor integrated circuit having a rule of 0.25 μm or later. In the future, Ar
An F excimer laser (193 nm) or X-ray may be used.

However, equipment and development investment are required to introduce a new exposure apparatus with a short exposure wavelength. Further, in the short wavelength region after the ArF excimer laser, an exposure light source, a glass material used for the exposure apparatus, and a resist are required. Such devices and materials are currently in the development stage, and there are many issues to be overcome in shortening the wavelength of the above-mentioned exposure light source, for example, there is no device having performance that can withstand production. Therefore, in order to achieve high resolution in the photolithography process, not only the wavelength of the exposure light source is shortened, but also a method of forming a pattern having a wavelength equal to or shorter than the exposure wavelength while securing the depth of focus has been researched and developed.

As a method of forming a pattern having a wavelength equal to or less than the exposure wavelength while securing the above-mentioned depth of focus, a silylation process for resolving only the surface layer of a resist film has been proposed. As an example, a method for processing a gate electrode of a transistor into a gate pattern using a positive silylation process in a method for manufacturing a semiconductor device having a MOS transistor will be described below with reference to the drawings.

FIG. 13 shows (a) a plan view of a semiconductor substrate and (b) a cross-sectional view of a region near an edge of the semiconductor substrate after a transistor forming step of the above-described method for manufacturing a semiconductor device having a MOS transistor. The area A is the main pattern area where the above-mentioned MOS transistor is formed. For example, STI (Shallow Tr) on the semiconductor substrate 10
A gate insulating film 21 made of, for example, silicon oxide is formed on an active region separated by an element isolation insulating film 20 of an (ench isolation) type, and a gate electrode 30a made of, for example, polysilicon is formed thereon. In the semiconductor substrate 10 on both sides of the gate electrode 30a, source / drain regions 11, which are diffusion layers of conductive impurities, are formed. The MOS transistor is configured as described above.

On the other hand, the region B is an edge portion of the semiconductor substrate and corresponds to an outer peripheral portion of the region A. The region B is a region that does not have a complete circuit pattern, and it is not necessary to form a semiconductor element in this region. However, a polysilicon layer 30b is formed in the manufacturing process. Is formed with a diffusion layer 12 of a conductive impurity.

The manufacturing steps of the manufacturing method up to the structure shown in FIG. 13 will be described. First, FIG.
As shown in (1), for example, an STI type element isolation insulating film is formed in a region A (the present pattern region) of the silicon semiconductor substrate 10.

Next, as shown in FIG. 14B, a silicon oxide film 21 is formed on the entire surface of the region A and the region B (edge portion) by, for example, a thermal oxidation method. In the region A, the silicon oxide film 21 becomes a gate insulating film of the transistor.

Next, as shown in FIG. 14C, the region A is formed by, for example, a CVD (Chemical Vapor Deposition) method.
And in the region B, for example, a polysilicon layer 30
Is deposited. In the region A, the polysilicon layer 30 is a layer serving as a gate electrode of the transistor.

Next, FIG. 15D is a perspective view and FIG.
As shown in the cross-sectional view, a resist film 40 for a polyvinylphenol-based silylation process is formed by spin coating on the entire surface of the polysilicon layer 30 in the regions A and B.

Next, FIG. 16 (f) is a perspective view and FIG.
As shown in the cross-sectional view, in the region B, the resist film 40 having a thickness of several mm from the outer peripheral portion is removed with a thinner S1. Next, the semiconductor substrate 10 is heated on a hot plate to evaporate the solvent in the resist, and the resist film 40 is cured.

Next, as shown in FIG.
Then, the resist film 40 is irradiated with a pattern light LP of a positive image using a positive type mask (a mask that leaves unexposed portions as a pattern) MP as a mask. Molecules in the exposed surface layer of the resist film 40 undergo a crosslinking reaction to form a crosslinked portion 41. On the other hand, the region B is not exposed because there is no need to form a pattern.

Next, as shown in FIG.
And in the region B, the surface of the resist film 40 (41) is exposed to the gas-phase silylating agent S. Although the diffusion of the silylating agent is prevented in the crosslinked portion 41, the non-crosslinked portion (crosslinked portion 4
The silylating agent is diffused from the surface of the resist film 40 except for (1), and the silylated compound-containing layer 42
Is formed. This step of diffusing the silylating agent can be performed by dipping in the silylating agent in a liquid phase. At this time, area B
In the above, the silylated compound-containing layer 42 is formed on the surface layer portion including the side wall surface of the resist film. Although the silylating agent diffuses only in one direction from the upper surface of the resist film,
At the side wall surface portion of the resist film, the silylating agent diffuses in all directions. As a result, the thickness T2 of the silyl compound-containing layer 42 formed on the side wall surface is formed to be larger than the film thickness T1 of the silyl compound-containing layer 42 formed on the upper surface of the resist film.

Next, as shown in FIG. 17 (j), by performing a plasma treatment (O ₂ plasma treatment) containing oxygen in the raw material gas as a dry development treatment, a surface layer portion of the silylated compound-containing layer 42 is formed. A silicon oxide (SiO _x ) -containing layer 42b is formed on the substrate, and a region excluding the silicon oxide-containing layer 42b becomes a silylated compound-containing layer 42a. At the same time, the resist film 40 including the bridging portion 41 is etched by the O ₂ plasma treatment using the silicon oxide-containing layer 42b as a mask to form a positive pattern that leaves the unexposed portion of the resist film 40a.

Next, as shown in FIG. 18 (k), the polysilicon layer 3b is formed using the silicon oxide-containing layer 42b as a mask.
0 is etched to form a polysilicon gate electrode 30a in the region A. At this time, since the positive pattern is also left in the region B, the polysilicon layer 30
b is formed.

Next, as shown in FIG. 18 (l), the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a are etched away by plasma treatment containing fluorine in the source gas, and oxygen is further added to the source gas. The bulk resist film 40a is removed by ashing by plasma processing. Alternatively, the silicon oxide-containing layer 42 may be
b, the silyl compound-containing layer 42a, and the bulk resist film 40a are removed.

Next, as shown in FIG.
In, for example, conductive impurities of a conductivity type different from the conductivity type of the semiconductor substrate 10 (an n-type impurity such as phosphorus when the substrate is a p-type, and a p-type impurity such as boron when the substrate is an n-type) Is implanted using the gate electrode 30a as a mask, and the semiconductor substrate 1 on both sides of the gate electrode 30a is implanted.
In step 0, source / drain regions 11, which are diffusion layers of conductive impurities, are formed. At this time, the diffusion layer 12 of the conductive impurity is also formed in the region B. The region B may be masked with a resist film or the like, and ions may be selectively implanted into the region A. This leads to the structure shown in FIG.

In the above-described method of manufacturing a semiconductor device, a positive silylation process (a step of forming a pattern in an unexposed portion) has been described. By forming a silicon oxide-containing layer on a portion to form a pattern, a negative silylation process can be performed.

In the method of manufacturing a semiconductor device using the above silylation process, only the surface layer portion of the resist film is resolved. A high-resolution pattern can be formed while securing a wide depth of focus. Also,
Since a resist having a high light absorptivity can be used, reflected light from the underlying substrate can be suppressed, and a standing wave effect can be reduced, so that pattern dimensional accuracy can be improved.

[0023]

However, the method of manufacturing a semiconductor device using the above-described silylation process involves a silicon oxide-containing layer 42b and a silylate-containing layer 42a.
In the step of removing, there is a problem that residues of the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a are generated at the edge portion (region B) of the substrate when the stripping time is insufficient.

The above problem will be described with reference to the drawings. As shown in FIG. 19 (k ′), the thickness of the silylated compound-containing layer 42 on the side wall surface of the resist film was larger than that of the silylated compound-containing layer 42 formed on the upper surface of the resist film. From the above, the thickness of the silicon oxide-containing layer 42b 'and the thickness of the silylide-containing layer 42a' on the side wall surface of the resist film formed when the O ₂ plasma processing is performed are different from those of the silicon oxide-containing layer 42a 'formed on the upper surface of the resist film. It is formed thicker than the film thickness of the layer 42b and the silylated material-containing layer 42a.
Therefore, in the region b, the silicon oxide-containing layer 42b '
In addition, extra time is required for peeling off the silylated material-containing layer 42a '. If the peeling time is insufficient, FIG.
As shown in FIG. 9 (l ′), the silicon oxide-containing layer 42b and the silyl compound-containing layer 42 at the edge (region B) of the substrate.
The residue 42c of a will be generated.

The residue 42c is converted to CV in a subsequent step.
When various layers are formed by the method D or the like, the film may be peeled off. Therefore, it is necessary to completely remove the residue 42c without leaving the residue 42c even in the region B which is originally unnecessary.

In the above method for manufacturing a semiconductor device,
Although the O ₂ plasma treatment is not performed as a dry development treatment, the surface silylide-containing layer may be thinly etched by a plasma treatment containing fluorine in the raw material gas before etching with the O ₂ plasma (this step). Is also called breakthrough). This means that, ideally, the silylated material-containing layer should not be formed on the exposed portion of the resist film, but the silylated material-containing layer having a thickness of several nm is formed on the surface layer of the exposed portion as well. This is because the silylated compound-containing layer in the exposed portion may be removed in some cases. Alternatively, the reason is to reduce the edge roughness of the pattern by etching and removing the silylated material-containing layer formed so as to protrude from the edge of the pattern. In this break-through, since the anisotropic etching is used, the silicon oxide-containing layer and the silyl compound-containing layer formed on the side wall surface of the resist film in the region B (edge portion) of the substrate are hardly etched.
Therefore, when a break-through is performed, the silicon oxide-containing layer and the silyl compound-containing layer on the side wall surface of the resist film at the edge portion (region B) of the substrate are more and more relative to the main pattern region (region A) of the substrate. Becomes thick, and the residue is likely to be left in the region B.

Since the silicon oxide-containing layer and the silylide-containing layer on the resist film side wall surface at the edge portion (region B) of the substrate are formed directly on a substrate such as a base layer of polysilicon or the like, In the case where the adhesiveness with such a material is good, peeling becomes more difficult. One of the silylating agents is HMDS (hexamethyldisilan), which is used as an adhesive between the resist and the underlying substrate. In this case, the silicon oxide-containing layer and the silylated compound-containing layer Adhesive strength with such as increases, it becomes difficult to peel.

A silicon oxide-containing layer and a silyl compound-containing layer are formed on a bulk resist film (in FIG. 19 (k '), a resist film 40a below the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a). In this case, the lower resist film 40a is removed first by the lift-off method, so that the upper silylide-containing layer and the silicon oxide-containing layer are separated and removed. If the silicon oxide-containing layer and the silicon oxide-containing layer are in close contact with each other, they are not separated by the lift-off method, so that the separation becomes difficult.

Actually, in order to remove a resist pattern formed on silicon nitride using a silylation process, a commercially available stripping solution (EKC-270 (EKC Tech) is used.
nology, Inc. )), The main pattern region (region A) of the substrate could be removed within 10 minutes of immersion, but the edge portion (region B) of the substrate could not be removed even after immersion for 60 minutes, and residues remained. Was.

The gas flow rate CHF ₃ / O ₂ = 20/7
0 sccm, substrate temperature 20 ° C, bias power 50W
When the silicon oxide-containing layer and the silyl compound-containing layer were removed using ECR (electron cycrotron resonance) plasma etching, the pattern region (region A) of the substrate could be removed in 30 seconds. The residue in the portion (region B) could not be removed even by etching for 120 seconds.

The present invention has been made in view of the above circumstances. Therefore, the present invention provides a method of patterning a resist film on a substrate by a silylation process without leaving a residue at the edge of the substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device and a photolithography method capable of removing a resist film.

[0032]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising: forming a first region on a substrate having at least a first region; A method of manufacturing a semiconductor device, comprising processing a layer to be processed formed on the substrate into a predetermined pattern in a region, wherein the first region and the second region are formed on a layer to be processed formed on the substrate. Forming a resist film on the entire surface, and exposing the resist film along a predetermined pattern in the first region to form a cross-linked portion and a non-cross-linked portion on the surface portion of the resist film along the pattern. A step of forming a crosslinked portion in a surface layer portion including a side wall surface of the resist film in the second region; and a step of forming a crosslinked portion in at least the surface layer portion of the non-crosslinked portion in the first region. Forming a silicon oxide-containing layer on at least a surface portion of the silylated material-containing layer in the first region; and masking the silicon oxide-containing layer in the first region and the second region. Processing the resist film along the pattern, and processing the processed layer in the first region and the second region using the silicon oxide-containing layer or the patterned resist film as a mask And

The method for manufacturing a semiconductor device of the present invention described above
A first substrate having a first region and a second region that is an outer peripheral portion thereof;
A resist film is formed on the entire surface of the layer to be processed formed on the substrate in the region and the second region. Next, the resist film is exposed along a predetermined pattern in the first region,
A crosslinked portion and a non-crosslinked portion are formed on the surface layer portion of the resist film along the pattern, and a crosslinked portion is formed on the surface layer portion including the side wall surface of the resist film in the second region. Next, in the first region, a silylated compound-containing layer is formed on at least the surface layer of the non-crosslinked portion, and a silicon oxide-containing layer is formed on at least the surface layer of the silylated compound-containing layer. Next, in the first region and the second region, the resist film is processed along the pattern using the silicon oxide-containing layer as a mask, and further, the processed layer is processed using the silicon oxide-containing layer or the patterned resist film as a mask.

According to the method of manufacturing a semiconductor device of the present invention described above, when a resist film is patterned on a substrate by a silylation process, at least a surface layer of a non-crosslinked portion formed in the resist film has a silylated compound. Before forming the containing layer, a crosslinked portion is formed in the surface layer portion including the side wall surface of the resist film in the second region, so that the silylated material-containing layer is not formed here, and therefore, the silicon oxide-containing layer is not formed. . Therefore, the resist film can be easily removed without leaving a residue in the second region (edge portion) of the substrate.

The method of manufacturing a semiconductor device according to the present invention described above includes:
Preferably, a step of using a resist film that forms a crosslinked portion in a portion to be exposed as the resist film, and forming a crosslinked portion and a non-crosslinked portion along the pattern in a surface portion of the resist film in the first region. In the step of exposing the resist film along a predetermined pattern, a bridge portion is formed in a surface layer portion of the exposed portion of the resist film, and the surface layer portion of the resist film excluding the bridge portion is the surface layer portion. As a non-crosslinked portion, in the step of forming a crosslinked portion on the surface layer portion including the side wall surface of the resist film in the second region, the step of exposing the resist film may include forming the crosslinked portion on the surface layer portion including the side wall surface of the resist film. Form a bridge.
As a result, a positive silylation process that leaves a pattern on the unexposed portion of the resist film can be achieved.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, a resist film that forms a non-crosslinked portion in a portion to be exposed when subjected to exposure and crosslinking treatment as the resist film, and forms a crosslinked portion in an unexposed portion, is used in the first region. In the step of forming a crosslinked portion and a non-crosslinked portion on the surface layer portion of the film along the pattern, a step of exposing the resist film along a predetermined pattern and a step of performing a crosslinking process include a step of covering the resist film. A non-crosslinked portion is formed in a surface layer portion of the exposed portion, a crosslinked portion is formed in a surface layer portion of the resist film other than the non-crosslinked portion, and a surface layer portion including a side wall surface of the resist film in the second region. In the step of forming a crosslinked portion, a crosslinked portion is formed in a surface layer portion including a side wall surface of the resist film by performing a crosslinking process on the resist film. Thereby, a negative silylation process that leaves a pattern on the exposed portion of the resist film can be achieved.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming a silicon oxide-containing layer on at least a surface layer portion of the silylide-containing layer in the first region, while forming a silicon oxide-containing layer on at least the surface layer portion of the silylide-containing layer, At the same time, in the first region and the second region, the resist film is processed along the pattern using the silicon oxide-containing layer as a mask. For example, by performing a plasma treatment containing oxygen in the raw material gas, a dry development process is performed in which a silicon oxide-containing layer is formed on at least a surface portion of the silylide-containing layer, and oxidation is performed in the first region and the second region. The step of processing the resist film along the pattern using the silicon-containing layer as a mask is performed at the same time, so that the step can be simplified.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized in that at least a first region of a substrate having a first region and a second region which is an outer peripheral portion of the first region is provided. A method of manufacturing a semiconductor device, wherein a processing target layer formed on a substrate is processed into a predetermined pattern, wherein a resist film is formed on an entire surface of the processing target layer formed on the substrate in the first region and the second region. Forming a cross-linked portion and a non-cross-linked portion in the first region along the pattern by exposing the resist film along a predetermined pattern, and Forming a non-crosslinked portion in a surface layer portion including a side wall surface of the resist film in the second region;
Forming a silylated compound-containing layer on at least a surface layer portion of the non-crosslinked portion in the region and the second region;
Removing the silylated compound-containing layer formed on the surface layer portion including at least the side wall surface of the resist film in the second region; and oxidizing at least the surface layer portion of the silylated compound-containing layer in at least the first region. Forming a silicon-containing layer, processing the resist film along the pattern in the first region and the second region using the silicon oxide-containing layer as a mask, and forming the first region and the second region. In the area
Processing the layer to be processed using the silicon oxide-containing layer or the patterned resist film as a mask.

The method of manufacturing a semiconductor device according to the present invention described above
A first substrate having a first region and a second region that is an outer peripheral portion thereof;
A resist film is formed on the entire surface of the layer to be processed formed on the substrate in the region and the second region. Next, the resist film is exposed along a predetermined pattern in the first region,
A cross-linked portion and a non-cross-linked portion are formed on the surface portion of the resist film along the pattern, and a non-cross-linked portion is formed on the surface portion including the side wall surface of the resist film in the second region. Next, the first
In the region and the second region, a silylated material-containing layer is formed on at least the surface portion of the non-crosslinked portion. Next, in the second region, the silyl compound-containing layer formed on the surface layer portion including at least the side wall surface of the resist film is removed. next,
Forming a silicon oxide-containing layer at least in a surface layer portion of the silylated material-containing layer in at least the first region, processing a resist film along the pattern using the silicon oxide-containing layer as a mask in the first region and the second region; The layer to be processed is processed using the silicon oxide-containing layer or the patterned resist film as a mask.

According to the method of manufacturing a semiconductor device of the present invention, when a resist film is patterned on a substrate by a silylation process, a silicon oxide is formed on a surface layer of a silylide-containing layer formed in the resist film. Before the formation of the containing layer, the silicide-containing layer formed on the surface layer portion including the side wall surface of the resist film in the second region is removed. Therefore, no silicon oxide-containing layer is formed here. Therefore, the resist film can be easily removed without leaving a residue in the second region (edge portion) of the substrate.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, a step of using a resist film that forms a crosslinked portion in a portion to be exposed as the resist film, and forming a crosslinked portion and a non-crosslinked portion along the pattern in a surface portion of the resist film in the first region. In the step of exposing the resist film along a predetermined pattern, a bridge portion is formed in a surface layer portion of the exposed portion of the resist film, and the surface layer portion of the resist film excluding the bridge portion is the surface layer portion. A non-crosslinked part. As a result, a positive silylation process that leaves a pattern on the unexposed portion of the resist film can be achieved.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, a resist film that forms a non-crosslinked portion in a portion to be exposed when subjected to exposure and crosslinking treatment as the resist film, and forms a crosslinked portion in an unexposed portion, is used in the first region. In the step of forming a crosslinked portion and a non-crosslinked portion on the surface layer portion of the film along the pattern, a step of exposing the resist film along a predetermined pattern and a step of performing a crosslinking process include a step of covering the resist film. A non-crosslinked portion is formed in a surface layer portion of the exposed portion, a crosslinked portion is formed in a surface layer portion of the resist film other than the non-crosslinked portion, and a surface layer portion including a side wall surface of the resist film in the second region. In the step of forming the non-crosslinked portion, a non-crosslinked portion is formed in a surface layer portion including a side wall surface of the resist film by exposing the resist film and performing a crosslinking process. Thereby, a negative silylation process that leaves a pattern on the exposed portion of the resist film can be achieved.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming a silicon oxide-containing layer on at least a surface layer portion of the silylide-containing layer in the first region, while forming a silicon oxide-containing layer on at least the surface layer portion of the silylide-containing layer, At the same time, in the first region and the second region, the resist film is processed along the pattern using the silicon oxide-containing layer as a mask. For example, by performing a plasma treatment containing oxygen in the raw material gas, a dry development process is performed in which a silicon oxide-containing layer is formed on at least a surface portion of the silylide-containing layer, and oxidation is performed in the first region and the second region. The step of processing the resist film along the pattern using the silicon-containing layer as a mask is performed at the same time, so that the step can be simplified.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, in the step of removing the silylated material-containing layer formed on a surface layer portion including at least a side wall surface of the resist film in the second region, at least a side wall surface of the resist film in the second region is removed. A resist film stripper is dropped on the surface layer containing the resist. This makes it possible to easily remove the silylated compound-containing layer formed on the surface layer including at least the side wall surface of the resist film.

In order to achieve the above object, a photolithography method according to the present invention is characterized in that a predetermined region is formed on at least a first region of a substrate having a first region and a second region which is an outer peripheral portion of the first region. A photolithography method for forming a resist film having a pattern, comprising: forming a resist film on the entire surface of a substrate in the first region and the second region; and forming the resist film in a predetermined pattern in the first region. Forming a cross-linked portion and a non-cross-linked portion along the pattern in the surface layer portion of the resist film, and forming a cross-linked portion in the surface layer portion including the side wall surface of the resist film in the second region. Forming, in the first region, forming a silylated compound-containing layer on at least a surface layer portion of the non-crosslinked portion; and in the first region, Forming a silicon oxide-containing layer on at least a surface portion of the silylide-containing layer, and processing the resist film along the pattern in the first region and the second region using the silicon oxide-containing layer as a mask And a process.

In order to achieve the above object, a photolithography method according to the present invention provides a photolithography method comprising the steps of: providing at least a first region of a substrate having a first region and a second region which is an outer peripheral portion of the first region; A photolithography method for forming a resist film having a predetermined pattern, comprising: forming a resist film on the entire surface of a substrate in the first region and the second region; Forming a crosslinked portion and a non-crosslinked portion in the surface layer portion of the resist film along the pattern, and exposing the surface layer portion including the side wall surface of the resist film in the second region. A step of forming a crosslinked portion, and a step of forming a silylated compound-containing layer at least in a surface layer portion of the non-crosslinked portion in the first region and the second region. Removing the silylated compound-containing layer formed on the surface layer portion including at least the side wall surface of the resist film in the second region; and at least in the first region, removing the silylated compound-containing layer from at least the surface layer portion of the silylated compound layer. Forming a silicon oxide-containing layer; and processing the resist film along the pattern in the first region and the second region using the silicon oxide-containing layer as a mask.

In the photolithography method of the present invention, when a resist film is patterned on a substrate by a silylation process, a silyl compound-containing layer is previously formed on the side wall surface of the resist film in the second region by exposure treatment. If not formed, or even if formed, the silylated material-containing layer on the side wall surface of the resist film in the second region is removed before forming the silicon oxide-containing layer on the surface of the silylated material-containing layer. Therefore, no silicon oxide-containing layer is formed in the second region. Therefore, the resist film can be easily removed without leaving a residue in the second region (edge portion) of the substrate.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 shows (a) a plan view of a semiconductor substrate and (b) a region near an edge of the semiconductor substrate after a transistor forming step in a method of manufacturing a semiconductor device having a MOS transistor according to the present embodiment. FIG. Region A, which is the first region, is the main pattern region in which the above-described MOS transistor is formed. For example, STI on the semiconductor substrate 10
(Shallow Trench Isolation) type element isolation insulating film 20
A gate insulating film 21 made of, for example, silicon oxide is formed on the active region separated by the above, and a gate electrode 30a made of, for example, polysilicon is formed thereon.
The semiconductor substrate 1 on both sides of the gate electrode 30a
In 0, a source / drain region 11 which is a diffusion layer of a conductive impurity is formed. As described above, MO
An S transistor is configured.

On the other hand, the region B, which is the second region, is the edge of the semiconductor substrate and corresponds to the outer periphery of the region A. Area B
Is a region that does not have a complete circuit pattern, and it is not necessary to form a semiconductor element in this region. However, due to the manufacturing process, the conductive impurity diffusion layer 1 is formed in the semiconductor substrate 10.
2 are formed.

The manufacturing steps of the manufacturing method up to the structure shown in FIG. 1 will be described. First, as shown in FIG. 2A, for example, an STI-type element isolation insulating film is formed in a region A (this pattern region) of the silicon semiconductor substrate 10.

Next, as shown in FIG. 2B, a silicon oxide film 21 having a thickness of 3 nm is formed on the entire surface of the region A and the region B (edge portion) by, for example, a thermal oxidation method.
In the region A, the silicon oxide film 21 becomes a gate insulating film of the transistor.

Next, as shown in FIG.
A polysilicon layer 30 having a thickness of 150 nm is deposited on the entire surface of the region A and the region B by a VD (Chemical Vapor Deposition) method. In the region A, the polysilicon layer 30 is a layer serving as a gate electrode of the transistor.

In the subsequent steps, a resist film serving as a mask for a gate pattern is formed by a positive silylation process. First, as shown in FIG. 3D, in a region A and a region B, a polysilicon layer 30 is formed.
On the entire surface of the upper layer, a resist film 40 for a polyvinylphenol-based silylation process is formed with a thickness of 700 nm by, for example, spin coating. Next, for example, at 100 ° C., 60
Perform pre-bake processing under the condition of seconds.

Next, as shown in FIG. 3E, a light LE (wavelength region of 190 nm or more) emitted from a deuterium lamp provided in the resist coating device is used to expose 5 mm from the outer periphery in the region B. A crosslinked portion 41 is formed by a photocrosslinking reaction in a portion to be exposed, which is a surface portion including the side wall surface of the resist film 40.

Next, as shown in FIG. 3F, in region A, a mask of a positive type gate layer composed of Cr (a mask that leaves unexposed portions as a gate pattern) MP is used as a mask. The pattern light LP of the positive image is sequentially and repeatedly exposed and transferred to the entire surface of the resist film 40 using an ArF excimer laser and an exposure light source (exposure wavelength: 193 nm) using a projection exposure apparatus having a reduction ratio of 1/4. Molecules in the surface layer portion of the resist film 40 in the exposed portion undergo a crosslinking reaction to form a crosslinked portion 41. As described above, in the region A, a crosslinked portion and a non-crosslinked portion are formed along the pattern in the surface layer portion of the resist film, while in the region B, a bridged portion is formed in the surface layer portion including the side wall surface of the resist film. I do.

Next, as shown in FIG. 4 (g), the gaseous DMSDMA (dimethyl
Exposure to silylated compound S such as silyldimethylamine) for 60 seconds. At this time, the silylated compound S is selectively diffused in the surface layer portion of the resist film 40 which is the non-crosslinked portion, and the silylated compound-containing layer 42 is formed. This step of diffusing the silylating agent can be performed by dipping in the silylating agent in a liquid phase.

Next, as shown in FIG.
Using a CP (transformer coupled plasma) type plasma etching apparatus, (processing temperature = 10 ° C., processing pressure =
5 mTorr, flow rate of O ₂ / SO ₂ = 160/30 sc
cm, TCP power = 500 W, bias power = 10
Anisotropic etching is performed by O ₂ —SO ₂ based plasma etching under the condition of 0 W). At this time, the silicon in the silicide-containing layer 42 and the oxygen in the etching gas E1 are combined, and the silicon oxide (SiO _x ) -containing layer 42b is selectively formed on the surface of the silylide-containing layer 42 to a thickness of, for example, 20 nm. The region formed and excluding the silicon oxide-containing layer 42b becomes the silylated material-containing layer 42a. In the above-described plasma etching, the resist film (40, 41) in the exposed portion is etched using the silicon oxide-containing layer 42b as a mask to form a resist film 40a having a gate pattern.

In the above plasma etching step,
If the gate length is out of the standard or the overlay accuracy with the underlying layer is out of the standard, the resist film is peeled off, and the above-described steps of forming the resist film and thereafter are repeated. The resist film is stripped by using, for example, a TCP type plasma etching apparatus (processing temperature = 0 ° C., processing pressure = 5 mTorr, CHF ₃ / O _2).
Flow rate = 10/50 sccm, TCP power = 500
W, bias power = 100 W) under the condition of CHF ₃ -O ₂
Anisotropic etching is performed for 15 seconds by system plasma etching to peel off the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a. Next, the remaining bulk resist film 40a is removed by ashing by O ₂ plasma processing,
Further, it is post-treated with an H ₂ SO ₂ / H ₂ O ₂ solution.

When the resist pattern is properly formed, as shown in FIG. 4 (i), for example, using an ECR type plasma etching apparatus, the silicon oxide containing layer 4 is formed.
2b or the resist film 40a as a mask, a Cl ₂ —O ₂ plasma etching process is performed as a first step, and an HBr—O ₂ plasma etching process is performed as a second step. Gate electrode 30a and silicon oxide gate insulating film 21
Is etched. The etching conditions include, for example, (substrate temperature = 20 ° C., processing pressure = 0.5 P
a, Flow rate of Cl ₂ / O ₂ / HBr = 15/5/95 sc
cm, bias RF power = 25 W).

Next, as shown in FIG.
Using a CP type plasma etching apparatus, CHF ₃ − under conditions of (processing temperature = 0 ° C., processing pressure = 5 mTorr, flow rate of CHF ₃ / O ₂ = 10/50 sccm, TCP power = 500 W, bias power = 100 W). Anisotropic etching is performed for 15 seconds by O ₂ -based plasma etching to peel off the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a. Next, the remaining bulk resist film 40a is removed by ashing by O ₂ plasma treatment, and further post-treated with a H ₂ SO ₂ / H ₂ O ₂ solution.

Next, as shown in FIG. 5 (k), in the region A, for example, conductive impurities of a conductivity type different from the conductivity type of the semiconductor substrate 10 (or n such as phosphorus when the substrate is p-type).
Type impurity, or a p-type impurity such as boron when the substrate is n-type) is ion-implanted using the gate electrode 30a as a mask, and the semiconductor substrate 10 on both sides of the gate electrode 30a is ion-implanted.
A source / drain region 11 which is a diffusion layer of a conductive impurity is formed therein. At this time, the diffusion layer 12 of the conductive impurity is also formed in the region B. The region B may be masked with a resist film or the like, and ions may be selectively implanted into the region A. This leads to the structure shown in FIG.

In the method of manufacturing a semiconductor device according to the present embodiment, when a resist film is patterned on a substrate by a positive silylation process, at least a surface layer portion of a non-crosslinked portion formed in the resist film is formed. Before the formation of the silylated compound-containing layer, a crosslinked portion is formed in the surface layer portion including the side wall surface of the resist film in the region B, so that the silylated compound-containing layer is not formed here, and therefore, the silicon oxide-containing layer is not formed. Not formed. Therefore, the resist film can be easily removed without leaving a residue in the region B (edge portion) of the substrate.

In the method of manufacturing a semiconductor device according to the present embodiment, instead of using the deuterium lamp provided in the resist coating apparatus, the exposure in the area B of the substrate is replaced by the ArF excimer which is the exposure light source of the exposure apparatus. Exposure is performed by using a laser beam that has been branched, or an exposure apparatus dedicated to edge exposure of a substrate equipped with a deuterium lamp can be used. Instead of using a polyvinylphenol-based resist, a chemically amplified resist composed of an acid generator, a crosslinker of a melamine derivative crosslinked by an acid, and a novolak resin can be used. In this case, the substrate is heated at a processing temperature of 110 ° C. for 60 seconds to diffuse the acid generated in the exposed portion, and the cross-linking agent cross-links the novolak resin by reaction with the acid. In this case, instead of using a deuterium lamp for exposing the edge portion of the substrate, a mercury xenon lamp (wavelength range of 220 nm to 440 nm) used for an edge exposure function of an existing coater developer may be used. it can.
Since the acid in the resist is also generated by irradiation with a mercury xenon lamp light, the resist can be cross-linked by irradiation with a mercury xenon lamp light.

Second Embodiment The method of manufacturing a semiconductor device according to this embodiment is substantially the same as that of the first embodiment except that a negative silylation process is used. First, as shown in FIG.
For example, an STI type element isolation insulating film 20 is formed on a silicon semiconductor substrate 10, and 3 nm is entirely formed in a region A (this pattern region) and a region B (edge portion) by a thermal oxidation method.
Is formed, and a polysilicon layer 30 is deposited to a thickness of 150 nm on the entire surface in the regions A and B by the CVD method. Next, over the entire surface of the polysilicon layer 30, for example,
A resist film 40 made of naphthoquinonediazide and a novolak resin is formed to a thickness of 00 nm. Next, for example, a pre-bake treatment is performed at 100 ° C. for 60 seconds.

Next, as shown in FIG. 6B, in a region A, a mask of a negative type gate layer in which a portion other than the pattern is a shielding film made of Cr (the exposed portion is formed by a gate). Using a projection exposure apparatus with a reduction ratio of 1/5 using a KrF excimer laser with an exposure light source (exposure wavelength: 248 nm) using MN as a mask, a negative image pattern light LN is applied to the entire surface of the resist film 40. Exposure transfer is performed successively and repeatedly. The area to be exposed is
As shown in FIG. 6B, a region B which is an edge portion of the substrate
Avoid getting stuck.

By the above exposure, naphthoquinonediazide is decomposed into indene ketene in the exposed portion, and becomes indene carboxylic acid in the presence of water. Next, the substrate is
By performing the heat treatment at 10 ° C. for 90 seconds, a decarboxylation reaction of indenecarboxylic acid occurs. On the other hand, in the unexposed portion, naphthoquinonediazide becomes ketene and crosslinks with the novolak resin. As a result, as shown in FIG. 6C, a crosslinked portion 41 is formed in the unexposed portion, and a non-crosslinked portion 43 is formed in the exposed portion. In the region B, the entire portion including the side wall surface of the resist film becomes a crosslinked portion.

Next, as shown in FIG. 7D, the substrate is exposed to a silylated compound S such as DMSDMA in the gas phase at 30 Torr at a temperature of 90 ° C. for 60 seconds. At this time, the silylated compound S is selectively diffused in the surface layer portion of the non-crosslinked portion 43 of the resist film, and the silylated compound-containing layer 42 is formed. This step of diffusing the silylating agent can be performed by dipping in the silylating agent in a liquid phase.

Next, as shown in FIG.
Using a CP type plasma etching apparatus, (processing temperature = 10 ° C., processing pressure = 5 mTorr, O ₂ / SO ₂ flow rate = 160/30 sccm, TCP power = 500 W,
Anisotropic etching is performed by O ₂ —SO ₂ plasma etching under the condition of (bias power = 100 W). At this time, the silicon in the silicide-containing layer 42 and the oxygen in the etching gas E1 are combined, and the silicon oxide (SiO _x ) -containing layer 42b is selectively formed on the surface of the silylide-containing layer 42 to a thickness of, for example, 20 nm. The region formed and excluding the silicon oxide-containing layer 42b becomes the silylated material-containing layer 42a.
Further, in the above-described plasma etching, the cross-linked portion 41, which is the unexposed portion of the resist film, is etched using the silicon oxide-containing layer 42b as a mask to form a resist film 41a having a gate pattern.

Next, as shown in FIG.
Using a CR-type plasma etching apparatus and using the silicon oxide-containing layer 42b or the resist film 40a as a mask, a Cl ₂ —O ₂ -based plasma etching process is performed as the first stage, and an HBr-O ₂ -based plasma etching process is performed as the second stage. Then, an etching gas E2 is applied to the substrate surface to etch the gate electrode 30a of polysilicon and the gate insulating film 21 of silicon oxide. The etching conditions include, for example, (substrate temperature = 20 ° C., processing pressure =
_{0.5Pa, Cl 2 / O 2 /} HBr flow rate = 15/5 /
95 sccm, bias RF power = 25 W).

Next, as shown in FIG.
Using a CP type plasma etching apparatus, CHF ₃ − under conditions of (processing temperature = 0 ° C., processing pressure = 5 mTorr, flow rate of CHF ₃ / O ₂ = 10/50 sccm, TCP power = 500 W, bias power = 100 W). Anisotropic etching is performed for 15 seconds by O ₂ -based plasma etching to peel off the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a. Next, the remaining bulk resist film 40a is removed by ashing by O ₂ plasma treatment, and further post-treated with a H ₂ SO ₂ / H ₂ O ₂ solution.

Next, as shown in FIG. 8H, in the region A, for example, a conductive impurity of a conductivity type different from the conductivity type of the semiconductor substrate 10 (or an n-type impurity such as phosphorus when the substrate is a p-type).
Type impurity, or a p-type impurity such as boron when the substrate is n-type) is ion-implanted using the gate electrode 30a as a mask, and the semiconductor substrate 10 on both sides of the gate electrode 30a is ion-implanted.
A source / drain region 11 which is a diffusion layer of a conductive impurity is formed therein. At this time, the diffusion layer 12 of the conductive impurity is also formed in the region B. The region B may be masked with a resist film or the like, and ions may be selectively implanted into the region A. Thus, the structure shown in FIG. 1 similar to the first embodiment is obtained.

In the method of manufacturing a semiconductor device according to the present embodiment, at the time of patterning a resist film on a substrate by a negative silylation process, at least a surface layer portion of a non-crosslinked portion formed in the resist film. Before the formation of the silylated compound-containing layer, a crosslinked portion is formed in the surface layer portion including the side wall surface of the resist film in the region B, so that the silylated compound-containing layer is not formed here, and therefore, the silicon oxide-containing layer is not formed. Not formed. Therefore, the resist film can be easily removed without leaving a residue in the region B (edge portion) of the substrate.

Third Embodiment FIG. 9 shows (a) a plan view of a semiconductor substrate and (b) a region near an edge of the semiconductor substrate after a transistor forming step in a method of manufacturing a semiconductor device having a MOS transistor according to this embodiment. FIG. Region A is the above M
This is the main pattern area where the OS transistor is formed. For example, a gate insulating film 21 made of, for example, silicon oxide is formed on an active region separated by an STI type element isolation insulating film 20 on the semiconductor substrate 10, and a gate electrode 30a made of, for example, polysilicon is formed thereon. Have been. In the semiconductor substrate 10 on both sides of the gate electrode 30a, a source / diffusion layer serving as a diffusion layer of conductive impurities is provided.
A drain region 11 is formed. The MOS transistor is configured as described above.

On the other hand, the region B is the edge of the semiconductor substrate and corresponds to the outer periphery of the region A. The region B is a region that does not have a complete circuit pattern, and it is not necessary to form a semiconductor element in this region. However, a polysilicon layer 30b is formed in the manufacturing process. Is formed with a diffusion layer 12 of a conductive impurity.

The manufacturing steps of the manufacturing method up to the structure shown in FIG. 9 will be described. First, as shown in FIG. 10A, for example, an STI type element isolation insulating film 20 is formed on a silicon semiconductor substrate 10, and the region A is formed by a thermal oxidation method.
A silicon oxide film 21 having a thickness of 3 nm is formed on the entire surface of the (pattern region) and the region B (edge portion), and a polysilicon layer 30 is formed on the entire surface of the region A and the region B to a thickness of 150 nm by the CVD method. Deposit.
Next, a resist film 40 for a polyvinylphenol-based silylation process is formed on the entire surface of the polysilicon layer 30 by, for example, spin coating to a thickness of 700 nm. Next, for example, a pre-bake treatment is performed at 100 ° C. for 60 seconds.

Next, as shown in FIG.
, Using a mask of a positive type gate layer in which the pattern portion is made of Cr (a mask that leaves an unexposed portion as a gate pattern) MP as a mask and using an ArF excimer laser as an exposure light source (exposure wavelength is 193 nm), The pattern light LP of the positive image is sequentially and repeatedly exposed and transferred to the entire surface of the resist film 40 using a 投影 projection exposure apparatus. Molecules in the surface layer portion of the resist film 40 in the exposed portion undergo a crosslinking reaction to form a crosslinked portion 41. As described above, in the region A, the crosslinked portion and the non-crosslinked portion are formed along the pattern on the surface layer portion of the resist film. On the other hand, the region B has not been exposed yet, and the entire resist film including the side wall portion is a non-crosslinked portion.

Next, as shown in FIG.
30 Torr gas phase DMSDMA (dimeth
Exposure to silylated compound S such as ylsilyldimethylamine) for 60 seconds. At this time, the resist film 40 which is a non-crosslinked portion
The silylated compound S is selectively diffused in the surface layer portion of the above, and the silylated compound-containing layer 42 is formed. This step of diffusing the silylating agent can be performed by dipping in the silylating agent in a liquid phase. At this time, in the region B, the silyl compound-containing layer 42 is formed on the surface layer portion including the side wall surface of the resist film. Although the silylating agent diffuses only in one direction from the upper surface of the resist film, the silylating agent diffuses in all directions on the side wall surface portion of the resist film. As a result, the film thickness T2 of the silylated material-containing layer 42 formed on the side wall surface is obtained.
Is formed to be thicker than the film thickness T1 of the silicide-containing layer 42 formed on the upper surface of the resist film.

Next, as shown in FIG.
While rotating 0, an organic stripping solution Sl (for example, trade name EK) is applied to a region (region B) 5 mm from the outer peripheral portion of the substrate.
C-270 (EKC Technology, Inc.
In the region B, the silylated compound-containing layer formed on the surface layer portion including at least the side wall surface is removed. The silylated material-containing layer 42 can be removed with an organic stripping solution as described above. At this time, the resist film 40 in the dropping region of the stripping solution Sl is also removed, and the structure shown in FIG.

Next, as shown in FIG. 11 (f), for example, using a TCP (transformer coupled plasma) type plasma etching apparatus, (processing temperature = 10 ° C., processing pressure = 5 mTorr, O ₂ / SO ₂ ) Flow rate = 160 / 30s
ccm, TCP power = 500 W, bias power = 1
Anisotropic etching is performed by O ₂ —SO ₂ plasma etching under the condition of (00 W). At this time, the silicon in the silicide-containing layer 42 and the oxygen in the etching gas E1 are combined, and the silicon oxide (SiO _x ) -containing layer 42b is selectively formed on the surface of the silylide-containing layer 42 to a thickness of, for example, 20 nm. The region formed and excluding the silicon oxide-containing layer 42b becomes the silylated material-containing layer 42a. In the above-described plasma etching, the resist film (40, 41) in the exposed portion is etched using the silicon oxide-containing layer 42b as a mask to form a resist film 40a having a gate pattern.

Next, as shown in FIG. 12 (g), using a silicon oxide-containing layer 42b or a resist film 40a as a mask, for example, using an ECR type plasma etching apparatus, a Cl ₂ -O ₂ system is used as a first step. A plasma etching process is performed, and as a second step, an HBr-O ₂ -based plasma etching process is performed, and an etching gas E2 is applied to the substrate surface to etch the gate electrode 30a of polysilicon and the gate insulating film 21 of silicon oxide. The etching conditions include, for example, (substrate temperature = 20 ° C., processing pressure =
_{0.5Pa, Cl 2 / O 2 /} HBr flow rate = 15/5 /
95 sccm, bias RF power = 25 W).

Next, as shown in FIG. 12H, for example, using a TCP type plasma etching apparatus, (processing temperature = 0 ° C., processing pressure = 5 mTorr, flow rate of CHF ₃ / O ₂ = 10/50 sccm) , TCP power = 500W,
Anisotropic etching is performed for 15 seconds by CHF ₃ —O ₂ -based plasma etching under the condition of (bias power = 100 W) to separate the silicon oxide-containing layer 42b and the silyl compound-containing layer 42a. Next, the remaining bulk resist film 40a is removed by ashing by O ₂ plasma treatment, and further post-treated with a H ₂ SO ₂ / H ₂ O ₂ solution.

Next, as shown in FIG.
In, for example, conductive impurities of a conductivity type different from the conductivity type of the semiconductor substrate 10 (an n-type impurity such as phosphorus when the substrate is a p-type, and a p-type impurity such as boron when the substrate is an n-type) Is implanted using the gate electrode 30a as a mask, and the semiconductor substrate 1 on both sides of the gate electrode 30a is implanted.
In step 0, source / drain regions 11, which are diffusion layers of conductive impurities, are formed. At this time, the diffusion layer 12 of the conductive impurity is also formed in the region B. The region B may be masked with a resist film or the like, and ions may be selectively implanted into the region A. This leads to the structure shown in FIG.

In the method of manufacturing a semiconductor device according to the present embodiment described above, the resist film is formed in the region B before the silicon oxide-containing layer is formed on the surface portion of the silylide-containing layer formed in the positive resist film. Since the silylated material-containing layer formed on the surface layer portion including the side wall surface is removed, no silicon oxide-containing layer is formed here. Therefore, the resist film can be easily removed without leaving a residue in the region B (edge portion) of the substrate.

In the method of manufacturing a semiconductor device according to the present embodiment, an aqueous solution of hydrofluoric acid can be used instead of an organic stripping solution to strip the resist film in the region B of the substrate. In this case, only the silyl compound-containing layer is peeled off, leaving the resist film, but the O ₂ plasma treatment of the next step removes the resist film formed under the removed silyl compound-containing layer. Therefore, the same structure as the above embodiment can be obtained.

The present invention relates to a semiconductor device having a process of patterning a photoresist film by a photolithography process, such as a semiconductor device of a MOS transistor such as a DRAM, a bipolar semiconductor device, or an A / D converter. It can be applied to any manufacturing method. Further, the present invention can be applied not only to a method for manufacturing a semiconductor device but also to a photolithography method for transferring a fine pattern.

The present invention is not limited to the above embodiment. For example, in the embodiment, a resist film is formed by a silylation process as a mask for processing a gate electrode, but the present invention can be applied to processing of a conductive layer other than the gate electrode, the substrate itself, or an insulating film. . In addition, various changes can be made without departing from the spirit of the present invention.

[0088]

According to the present invention, when a resist film is patterned on a substrate by a silylation process, a silyl compound-containing layer is not previously formed on the side wall surface of the resist film in the second region by an exposure treatment, or Even if it is formed, the silylide-containing layer on the side wall surface of the resist film in the second region is removed before forming the silicon oxide-containing layer on the surface layer of the silylide-containing layer. It is possible to provide a method of manufacturing a semiconductor device and a method of photolithography that can easily remove a resist film without leaving a residue at an edge portion).

[Brief description of the drawings]

FIGS. 1A and 1B are (a) a plan view of a semiconductor substrate and (b) a cross-sectional view of a region near an edge of the semiconductor substrate after a transistor forming step of the semiconductor device according to the first embodiment.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 2A illustrates a process up to a step of forming an element isolation insulating film, and FIG. 2B illustrates a gate insulating film. (C) shows up to the step of forming a polysilicon layer to be a gate electrode.

FIG. 3 is a sectional view showing a step subsequent to that of FIG. 2;
(D) shows up to the step of forming a resist film, (e) shows up to the exposure step in the area B, and (f) shows up to the pattern exposure step in the area A.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(G) shows up to the step of forming a silylide-containing layer, (h) shows up to the step of forming a silicon oxide-containing layer and pattern processing of a resist film, and (i) shows up to the step of patterning a gate electrode.

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;
(J) shows the process until the resist film is removed, and (k) shows the source
The steps up to the step of forming the drain region are shown.

FIGS. 6A and 6B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a second embodiment, in which FIG. 6A illustrates up to a step of forming a resist film, and FIG. And (c) show the steps up to the step of forming a crosslinked portion in the exposed region.

FIG. 7 is a sectional view showing a step subsequent to that of FIG. 6;
(D) shows the process up to the formation of the silyl compound-containing layer, (e) shows the process up to the formation of the silicon oxide-containing layer and the patterning of the resist film, and (f) shows the process up to the patterning of the gate electrode.

FIG. 8 is a sectional view showing a step subsequent to that of FIG. 7;
(G) until the step of removing the resist film, (h) the source
The steps up to the step of forming the drain region are shown.

9A is a plan view of a semiconductor substrate after a transistor forming step of a semiconductor device according to a third embodiment, and FIG. 9B is a cross-sectional view of a region near an edge of the semiconductor substrate.

FIGS. 10A and 10B are cross-sectional views illustrating manufacturing steps of a method of manufacturing a semiconductor device according to a third embodiment. FIG. 10A illustrates up to a resist film forming step, and FIG. 10B illustrates a pattern exposing step in a region A. And (c) show the steps up to the step of forming the silylated material-containing layer.

11 is a cross-sectional view showing a step subsequent to that of FIG. 10; (d) and (e) show steps up to a step of removing a silylated compound-containing layer in a region B; and (f) shows formation of a silicon oxide-containing layer. And the steps up to the step of patterning the resist film.

12 is a cross-sectional view showing a step that follows the step shown in FIG. 11; FIG.
(H) shows the process up to the resist film removal step, and (i) shows the source
The steps up to the step of forming the drain region are shown.

FIGS. 13A and 13B are (a) a plan view of a semiconductor substrate and (b) a cross-sectional view of a region near an edge of the semiconductor substrate after a transistor forming step of a semiconductor device according to a conventional example.

14A and 14B are cross-sectional views showing a manufacturing process of a method of manufacturing a semiconductor device according to a conventional example, in which FIG. 14A shows up to a step of forming an element isolation insulating film, and FIG. (C) shows up to the step of forming a polysilicon layer to be a gate electrode.

FIG. 15 is a perspective view (d) and a sectional view (e) showing up to the step of forming a resist film subsequent to FIG. 14;

16 (f) is a perspective view and FIG. 16 (g) is a sectional view showing up to the step of removing the resist film on the outer peripheral portion of the substrate following FIG.

17 is a cross-sectional view showing a step that follows the step shown in FIG. 16; FIG. 17 (h) shows a pattern exposure step; FIG. 17 (i) shows a step of forming a silylated compound-containing layer; Up to the formation of the resist film and the patterning process of the resist film.

FIG. 18 is a cross-sectional view showing a step subsequent to that of FIG. 17; (k) shows a step until a gate electrode pattern processing step;
(L) shows the process until the resist film is removed, and (m) shows the source
The steps up to the step of forming the drain region are shown.

FIG. 19 is a cross-sectional view for explaining a problem in a manufacturing process of a conventional semiconductor device, in which (k ′) shows a process up to a gate electrode patterning process, and (l ′) shows a removal of a resist film. The process is shown.

[Explanation of symbols]

10: semiconductor substrate, 11: source / drain region, 12
... Diffusion layer of conductive impurity, 20 ... Element isolation insulating film, 21
... Gate insulating film, 30, 30b ... Polysilicon layer, 30
a: gate electrode, 40, 40a: resist film, 41, 4
1a: crosslinked portion, 42, 42a, 42a ': silylated compound-containing layer, 42b, 42b': silicon oxide-containing layer, 42c
... residue, 43 ... non-crosslinked part, LE ... light for edge part exposure,
LP, LN: light for pattern exposure, MP, MN: mask, S: silylating agent, E1, E2: etching gas, D
... conductive impurities, Sl: stripping solution.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/30 577 21/302 HF term (Reference) 2H096 AA25 BA01 EA02 FA04 FA10 HA23 5F004 AA09 BA20 CA06 DA00 DA04 DA16 DA26 DB02 DB26 EA04 EA06 EA26 EA28 EA32 EB02 FA02 5F046 AA28 BA04 CA01 CA04 JA04 LB01 LB09 MA12

Claims (13)

[Claims] 1. A semiconductor device for processing a processing target layer formed on a substrate into a predetermined pattern in at least a first region of the substrate having a first region and a second region which is an outer peripheral portion of the first region. In the manufacturing method, a step of forming a resist film on the entire surface of a layer to be processed formed on a substrate in the first region and the second region; Exposure along a pattern to form a cross-linked portion and a non-cross-linked portion along the pattern in the surface layer portion of the resist film; Forming a silylated compound-containing layer at least in a surface layer portion of the non-crosslinked portion in the first region; and reducing the amount of the silylated compound-containing layer in the first region. Forming a silicon oxide-containing layer on a surface layer portion, and processing the resist film along the pattern in the first region and the second region using the silicon oxide-containing layer as a mask; Processing the layer to be processed in the region and the second region using the silicon oxide-containing layer or the patterned resist film as a mask. 2. A resist film for forming a crosslinked portion in a portion to be exposed is used as the resist film, and a crosslinked portion and a non-crosslinked portion are formed along the pattern in a surface layer portion of the resist film in the first region. In the step, a step of exposing the resist film along a predetermined pattern forms a crosslinked portion in a surface portion of the exposed portion of the resist film, and a surface layer portion of the resist film excluding the crosslinked portion is formed. In the step of forming a crosslinked portion in the second region, the surface region including the side wall surface of the resist film in the second region, by exposing the resist film, the surface layer portion including the side wall surface of the resist film is exposed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a bridge portion is formed in the semiconductor device. 3. A resist film which forms a non-crosslinked portion in a portion to be exposed when exposed and crosslinked as a resist film, and forms a crosslinked portion in an unexposed portion, In the step of forming a crosslinked portion and a non-crosslinked portion in the surface layer portion of the resist film along the pattern, a step of exposing the resist film along a predetermined pattern, and a step of performing a crosslinking treatment, A non-crosslinked portion is formed in a surface layer portion of the exposed portion, a crosslinked portion is formed in a surface layer portion of the resist film other than the non-crosslinked portion, and a surface layer portion including a sidewall surface of the resist film in the second region. 2. The semiconductor device according to claim 1, wherein, in the step of forming a cross-linking portion, a cross-linking process is performed on the resist film to form a cross-linking portion in a surface layer portion including a side wall surface of the resist film. The method of production. 4. In the step of forming a silicon oxide-containing layer on at least a surface portion of the silylated material-containing layer in the first region, forming a silicon oxide-containing layer on at least the surface portion of the silylated material-containing layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the resist film is processed along the pattern in the first region and the second region at the same time using the silicon oxide-containing layer as a mask. 5. The semiconductor according to claim 4, wherein, in the step of forming a silicon oxide-containing layer at least in a surface layer portion of the silylated compound-containing layer in the first region, a plasma treatment is performed in which a source gas contains oxygen. Device manufacturing method. 6. A semiconductor device for processing a layer to be processed formed on a substrate into a predetermined pattern in at least a first region of the substrate having a first region and a second region which is an outer peripheral portion of the first region. In the manufacturing method, a step of forming a resist film on the entire surface of a layer to be processed formed on a substrate in the first region and the second region; Exposing along the pattern to form a cross-linked portion and a non-cross-linked portion in the surface portion of the resist film along the pattern; and in the second region, non-cross-linked to the surface portion including the side wall surface of the resist film. Forming a portion, forming a silylated compound layer on at least a surface portion of the non-crosslinked portion in the first region and the second region, and forming the resist in the second region. Removing the silylated material-containing layer formed on the surface layer portion including at least the side wall surface of the film, and forming a silicon oxide-containing layer on at least the surface layer portion of the silylated material-containing layer in at least the first region. Processing the resist film along the pattern using the silicon oxide-containing layer as a mask in the first region and the second region; and forming the silicon oxide-containing layer in the first region and the second region. Processing the layer to be processed using the layer or the patterned resist film as a mask. 7. A resist film for forming a crosslinked portion in a portion to be exposed as said resist film, wherein a crosslinked portion and a non-crosslinked portion are formed along the pattern in a surface layer portion of the resist film in the first region. In the step, a step of exposing the resist film along a predetermined pattern forms a crosslinked portion in a surface portion of the exposed portion of the resist film, and a surface layer portion of the resist film excluding the crosslinked portion is formed. The method for manufacturing a semiconductor device according to claim 6, wherein the non-crosslinked portion is used. 8. A resist film that forms a non-crosslinked portion in a portion to be exposed when exposed and crosslinked as a resist film and forms a crosslinked portion in an unexposed portion, In the step of forming a crosslinked portion and a non-crosslinked portion in the surface layer portion of the resist film along the pattern, a step of exposing the resist film along a predetermined pattern, and a step of performing a crosslinking treatment, A non-crosslinked portion is formed in a surface layer portion of the exposed portion, a crosslinked portion is formed in a surface layer portion of the resist film other than the non-crosslinked portion, and a surface layer portion including a sidewall surface of the resist film in the second region. In the step of forming a non-crosslinked portion on the surface of the resist film, a step of exposing the resist film and a step of performing a cross-linking treatment are performed to form a non-crosslinked portion in a surface layer portion including a side wall surface of the resist film. The method of manufacturing a semiconductor device of claim 6, wherein. 9. In the step of forming a silicon oxide-containing layer on at least a surface portion of the silylide-containing layer in the first region, forming a silicon oxide-containing layer on at least a surface portion of the silylide-containing layer. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the resist film is processed along the pattern in the first region and the second region at the same time using the silicon oxide-containing layer as a mask. 10. The semiconductor according to claim 9, wherein, in the step of forming a silicon oxide-containing layer at least in a surface layer portion of the silylated compound-containing layer in the first region, a plasma treatment is performed in which a source gas contains oxygen. Device manufacturing method. 11. In the step of removing the silylated compound-containing layer formed in a surface layer portion including at least a side wall surface of the resist film in the second region,
7. The method for manufacturing a semiconductor device according to claim 6, wherein a resist film stripper is dropped on a surface layer portion including at least a side wall surface of the resist film in a region. 12. At least a first region of a substrate having a first region and a second region which is an outer peripheral portion of the first region,
A photolithography method for forming a resist film having a predetermined pattern on the substrate, comprising: forming a resist film on the entire surface of the substrate in the first region and the second region; Exposing the film along a predetermined pattern to form a crosslinked portion and a non-crosslinked portion in the surface layer portion of the resist film along the pattern; and a surface layer including a sidewall surface of the resist film in the second region. A step of forming a crosslinked portion in a portion; a step of forming a silylated compound-containing layer in at least a surface portion of the non-crosslinked portion in the first region; and at least a surface layer portion of the silylated compound layer in the first region. Forming a silicon oxide-containing layer in the first region and the second region, using the silicon oxide-containing layer as a mask. Photolithographic method and a step of processing along the resist layer on the pattern. 13. At least in a first region of a substrate having a first region and a second region which is an outer peripheral portion of the first region,
A photolithography method for forming a resist film having a predetermined pattern on the substrate, comprising: forming a resist film on the entire surface of the substrate in the first region and the second region; Exposing the film along a predetermined pattern to form a cross-linking portion and a non-cross-linking portion along the pattern in a surface layer portion of the resist film; and a surface layer including a side wall surface of the resist film in the second region. Forming a non-crosslinked portion in a portion; forming a silylated compound-containing layer in at least a surface portion of the non-crosslinked portion in the first region and the second region; and forming the resist film in the second region. Removing the silylated material-containing layer formed on the surface layer portion including at least the side wall surface of at least the first region. Forming a silicon oxide-containing layer on at least a surface portion of the oxide-containing layer, and processing the resist film along the pattern in the first region and the second region using the silicon oxide-containing layer as a mask And a photolithography method comprising: