JP2012178394A - Method of manufacturing semiconductor device, semiconductor device and exposure apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with no bump, the semiconductor device and an exposure apparatus.SOLUTION: A photosensitive negative resist material that becomes a lower layer resist film is applied onto a film 2 to be processed. Acid is generated by irradiating the lower layer resist material film with exposure light. A lower layer resist film 3b is formed by applying bake processing. By applying development processing, a portion of a non-crosslinked lower layer resist material film is removed while leaving the crosslinked lower layer resist film 3b. By applying a photosensitive negative resist material that becomes an intermediate layer resist film and applying similar exposure processing and development processing, a portion of a non-crosslinked intermediate layer resist material film is removed while leaving the crosslinked intermediate layer resist film 4b.

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and an exposure apparatus, and more particularly to a semiconductor device manufacturing method to which a multilayer resist process is applied, a semiconductor device manufactured by the manufacturing method, and a manufacturing method thereof. The present invention relates to an exposure apparatus.

  When manufacturing a semiconductor device including a semiconductor integrated circuit, as in an ion implantation process to a predetermined region in a semiconductor substrate or the like, an etching process to a film to be processed formed on the surface of the semiconductor substrate, etc. Selective processing (processing) is performed. In such a process, for the purpose of selectively protecting a film to be processed, a pattern of a composition sensitive to actinic rays such as ultraviolet rays, X-rays and electron beams, a so-called photosensitive photoresist film (photoresist film) is formed. Lithography is performed on the film to be processed. In this lithography, in particular, pattern formation by a photoresist film using ultraviolet rays is most widely used.

  As the integration and performance of semiconductor integrated circuits progress, miniaturization of circuit patterns and advanced dimensional control are required. In the exposure apparatus, the wavelength of the exposure light source is shortened from g-line (wavelength = 436 nm) of mercury lamp to i-line (wavelength = 365 nm), KrF excimer laser (wavelength = 248 nm), and ArF excimer laser (wavelength = 193 nm). Has been promoted. Recently, an immersion exposure technique has also appeared that can improve the resolution by filling water (pure water) between the reduction projection lens of the exposure apparatus and the photoresist film applied on the semiconductor substrate. The life of optical lithography has been extended.

  On the other hand, in the photoresist film, in order to ensure the resolution of the pattern, the film thickness of the photoresist film has been reduced, and recently, a photoresist film having a thickness of about 100 nm has been applied. . However, in lithography using an antireflection film such as an organic BARC (Bottom Anti Reflection Coating) film and a photoresist film by miniaturizing the pattern and reducing the thickness of the photoresist film, etching resistance to the film to be processed is ensured. Things are getting harder. Examples of the film to be processed include various film types such as a silicon oxide film or a polysilicon film.

  In order to ensure such etching resistance, a multilayer resist process has recently been introduced. A typical multi-layer resist process is a three-layer resist process. In the three-layer resist process, an upper layer resist film, an intermediate layer resist film, and a lower layer resist film are formed. The upper resist film is a resist film in which a pattern is formed by exposure and development, and is a photosensitive resist film. The lower resist film is a resist film that serves as a dry etching mask for the film to be processed. The intermediate layer resist film is a resist film having a role of transferring the pattern of the upper layer resist film to the lower layer resist film.

  In order to use the lower resist film as a mask for dry etching, a material having a high etching resistance and a function of flattening the step of the base or preventing reflection is used as the material of the lower resist film. In addition, in order to give the intermediate layer resist film etching selectivity with respect to the upper layer resist and the lower layer resist, a material containing high-concentration silicon (Si) atoms is used as the material of the intermediate layer resist film. By adopting such a multilayer resist process, high etching resistance (etching selection ratio) is ensured, and a fine pattern can be formed with high accuracy. Patent Document 1 is an example of a document that discloses a multilayer resist process.

Japanese Patent Publication No. 04-30740 JP 2010-93049 A

  However, the multilayer resist process has the following problems in the lower layer resist film or the intermediate layer resist film. In the step of forming the lower layer resist film or the intermediate layer resist film, first, a predetermined lower layer (intermediate layer) resist material is first applied on the surface of the wafer (semiconductor substrate). Next, the lower layer (intermediate layer) resist material film having a uniform thickness is formed on the wafer by rotating the wafer at a predetermined number of rotations. Next, while rotating the wafer, by spraying a predetermined organic solvent that dissolves the lower layer (intermediate layer) resist material onto the portion of the lower layer (intermediate layer) resist material film located at the edge of the wafer, the edge rinse is performed. Done. Thereafter, baking is performed at a predetermined temperature to crosslink the lower layer (intermediate layer) resist material, thereby forming a lower layer (intermediate layer) resist film.

  Among the steps of forming the series of lower layer (intermediate layer) resist films, in the step of performing edge rinse, the lower layer (intermediate layer) resist material located on the outer peripheral portion of the wafer is dissolved. The dissolved lower layer (intermediate layer) resist material is blown outward from the rotating wafer. On the other hand, the dissolved lower layer (intermediate layer) resist material remaining on the wafer without being blown may swell and rise when the lower layer (intermediate layer) resist material is dried. For this reason, the film thickness of the lower layer (intermediate layer) resist material film located on the outermost periphery is thicker than the film thickness of the lower layer (intermediate layer) resist material film located on the inner side. The portion where the lower layer (intermediate layer) resist material film swells and rises is called “hump”.

  If processing such as etching is performed on the film to be processed in a state where humps are generated in the lower layer (intermediate layer) resist film, a resist residue of the lower layer resist film or the intermediate layer resist film may be generated. In addition, a residue of the processed film (processed film residue) may be generated. These residues cause generation of foreign matters. Note that Patent Document 2 is an example of a document that discloses a phenomenon in which a hump occurs and a problem that occurs with the occurrence of a hump.

  The present invention has been made to solve the above problems, and one object is to provide a method for manufacturing a semiconductor device without humps, and another object is a method for manufacturing such a semiconductor device. It is another object of the present invention to provide an exposure apparatus used in a method for manufacturing such a semiconductor device.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps. A film to be processed is formed on the main surface of the semiconductor substrate. A first resist material is applied so as to cover the film to be processed. A first film is formed by a first resist material applied on the film to be processed. Of the first film covering the film to be processed, except for the portion of the first film located in the outer peripheral area extending along the outer edge up to a predetermined distance from the outer edge of the semiconductor substrate to the inner side, Exposure light is irradiated to the entire surface of the first film portion located inside. Heat treatment is performed at the first temperature. By performing development processing with a predetermined developer, a portion of the first film located in the outer peripheral region where the exposure light is not irradiated is removed. By applying at least a second resist material so as to cover the first film, a second film made of the second resist material is formed on the first film. A predetermined pattern is formed by subjecting the second film to a predetermined photolithography process. By removing a portion of the first film exposed from the predetermined pattern of the second film, a pattern of the first film corresponding to the predetermined pattern is formed on the first film. The portion of the film to be processed that is exposed from the pattern of the first film is removed.

  A semiconductor device according to another embodiment of the present invention is a semiconductor device manufactured by the semiconductor device manufacturing method.

  An exposure apparatus according to still another embodiment of the present invention includes a stage for holding a semiconductor substrate, a light source unit, and a blind. The light source unit is arranged at a predetermined position spaced from the stage so as to face the semiconductor substrate held on the stage. The blind is disposed between the light source unit and the stage and blocks exposure light emitted from the light source unit from irradiating a predetermined outer peripheral region extending along the outer edge of the semiconductor substrate held on the stage.

  According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, no hump is generated in the first film, thereby reducing a resist residue or a processed film residue. As a result, it is possible to suppress a decrease in yield of the semiconductor device due to the generation of foreign matter. In addition, deterioration of the reliability of the semiconductor device due to film peeling can be suppressed.

  According to the semiconductor device according to another embodiment of the present invention, a decrease in yield or a deterioration in reliability is suppressed.

  According to the exposure apparatus according to still another embodiment of the present invention, a resist film without hump can be formed as a resist film for patterning a film to be processed.

It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG. 1 in the same embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. In the same embodiment, it is a figure which shows the image of the crosslinking reaction of the base polymer in lower layer resist material. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. In the same embodiment, it is a figure which shows the image of the crosslinking reaction of the base polymer in intermediate | middle layer resist material. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on a comparative example. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24. FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29. FIG. 4 is a partial cross-sectional view showing respective outer edges of a lower layer resist film, an intermediate layer resist film, and an upper layer resist film in the three-layer resist process in the same embodiment. It is a fragmentary sectional view showing each outer edge of a lower layer resist film, an intermediate layer resist film, and an upper layer resist film in a three layer resist process concerning a comparative example. It is a perspective view which shows the concept of the exposure apparatus which concerns on Embodiment 2 of this invention. FIG. 34 is a cross sectional view taken along a cross sectional line XXXIV-XXXIV shown in FIG. 33 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the same embodiment. FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the same embodiment. FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the same embodiment. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is a cross-sectional view showing a process performed after the process shown in FIG. 40 in the same embodiment. FIG. 42 is a cross-sectional view showing a process performed after the process shown in FIG. 41 in the same Example. FIG. 43 is a cross-sectional view showing a step performed after the step shown in FIG. 42 in the same embodiment. FIG. 44 is a cross-sectional view showing a step performed after the step shown in FIG. 43 in the same embodiment.

Embodiment 1
Here, the main part of the manufacturing method of the semiconductor device to which the multilayer resist process is applied will be described. As a multilayer resist process, a three-layer resist process of a lower layer resist film, an intermediate layer resist film, and an upper layer resist film is taken as an example.

  First, a film to be processed to be subjected to predetermined processing is formed on the surface of a semiconductor substrate. Next, a lower resist film is formed in contact with the film to be processed. As the resist material to be the lower resist film, for example, a photosensitive negative resist material is used. This resist material is composed of a base polymer, a photoacid generator, a crosslinking agent and a solvent. An example of the base polymer is polyhydroxystyrene as shown in (Chemical Formula 1), for example.

  The photoacid generator has a function of generating an acid by irradiation with exposure light, and examples thereof include triphenylsulfonium trifluoromethanesulfonate as shown in (Chemical Formula 2).

  The cross-linking agent has a function of enabling a cross-linking reaction under the generated acid. For example, as shown in (Chemical Formula 3), hexamethoxymethyl melamine can be mentioned.

  First, the lower layer resist material is applied onto the film to be processed by a resist coating apparatus, and the semiconductor substrate is rotated at a predetermined rotational speed, whereby the surface of the semiconductor substrate 1 (the film to be processed 2 as shown in FIG. 1). The lower resist material film 3 having a uniform film thickness is formed on the surface of the substrate.

  Next, an acid is generated by irradiating the lower resist material film 3 with exposure light. At this time, as shown in FIG. 2, first, the annular blind 53 is arranged so as to cover the outer peripheral region extending along the outer edge of the semiconductor substrate 1. Next, by irradiating the exposure light 54 in that state, the exposure light is irradiated to the portion of the lower resist material film 3 located inside the outer peripheral region, and as shown in the following (Chemical Formula 4), the lower resist The photoacid generator contained in the material film 3 is decomposed to generate an acid (proton). On the other hand, the portion of the lower resist material film 3 located in the outer peripheral region is not irradiated with the exposure light blocked by the blind 53. For this reason, the photoacid generator is not decomposed and no acid is generated.

  Next, as shown in FIG. 3, for example, a lower resist film 3b is formed by performing a baking process (heat 61) under a temperature condition of about 150 ° C. to 200 ° C. At this time, as shown in FIG. 4, the cross-linking reaction by the acid generated in the lower resist material film 3 is promoted by the baking treatment, and the base polymer 41 is cross-linked through the cross-linking agent 42, thereby forming the cross-linked polymer 43 (the lower layer). A resist film 3b) will be formed.

  On the other hand, the portion of the lower resist material film which is located in the outer peripheral region and where no acid is generated is left as an uncrosslinked lower resist material film 3. Next, as shown in FIG. 5, a developing process is performed with a predetermined organic solvent 62 as a developing solution, thereby removing a portion of the uncrosslinked lower layer resist material film 3 as shown in FIG. 6. The lower resist film 3b is left. By removing the portion of the lower resist material film 3 located in a predetermined outer peripheral region of the semiconductor substrate, the hump seen in the conventional three-layer resist process does not occur. Note that the peripheral region in the semiconductor substrate is not a peripheral region that is uniquely determined, but a region that is determined corresponding to each of the lower layer resist (material) film, the intermediate layer resist (material) film, and the upper layer resist (material) film.

  Here, depending on the lower layer resist material, instead of the organic solvent, for example, an alkaline aqueous solution such as an aqueous tetramethylammonium hydroxide solution may be applied as the developer. Further, in order to further promote the crosslinking reaction in the lower resist film 3b, the baking process is added under a temperature condition higher than the above-described baking temperature condition (about 150 ° C. to 200 ° C.). Also good.

  Next, an intermediate layer resist film is formed in contact with the lower layer resist film. The resist material used as the intermediate layer resist film is a photosensitive negative resist material similar to the resist material used as the lower layer resist film, and this resist material is composed of at least a base polymer, a photoacid generator and a solvent. Has been. Moreover, you may contain the crosslinking agent in addition to these. An example of the base polymer is an organic polysiloxane as shown in (Chemical Formula 5). Examples of the photoacid generator, the crosslinking agent, and the solvent are the same as the photoacid generator, the crosslinking agent, and the solvent of the resist material that becomes the lower resist film.

  First, a predetermined intermediate layer resist material is applied onto the lower resist film by a resist coating apparatus, and the semiconductor substrate is rotated at a predetermined rotational speed so as to cover the lower resist film 3b as shown in FIG. An intermediate layer resist material film 4 is formed. Next, an acid is generated by irradiating the intermediate layer resist material film 4 with exposure light. At this time, as shown in FIG. 8, the annular blind 53 is arranged so as to cover the outer peripheral region from the outer edge of the semiconductor substrate to a predetermined position inside the outer edge of the lower resist film 3b.

  Next, by irradiating the exposure light 54 in this state, the exposure light is irradiated to the portion of the intermediate layer resist material film 4 located inside the outer peripheral region, and the photoacid contained in the intermediate layer resist material film 4 is irradiated. The generator is decomposed to generate an acid (proton). On the other hand, the exposure light is blocked by the blind 53 and is not irradiated onto the portion of the intermediate layer resist material film 4 located in the outer peripheral region. For this reason, the photoacid generator is not decomposed and no acid is generated.

  Next, as shown in FIG. 9, for example, an intermediate layer resist film 4b is formed by performing a baking process (heat 61) under a temperature condition of about 150 ° C. to 200 ° C. At this time, as shown in FIG. 10, the cross-linking reaction by the acid generated in the intermediate layer resist material film 4 is promoted by baking, and the base polymer 41 is cross-linked to form the cross-linked polymer 43 (intermediate layer resist film 4 b). Will be formed.

  Note that the reference code of the base polymer and the reference code of the cross-linked polymer in the case of the intermediate layer resist film 4b are the same as the reference code of the base polymer and the reference code of the cross-linked polymer in the case of the lower layer resist film 3b, respectively. Is not intended.

  On the other hand, the portion of the intermediate layer resist material film which is located in the outer peripheral region and where no acid is generated remains as the uncrosslinked intermediate layer resist material film 4. Next, as shown in FIG. 11, as a developing solution, a development process is performed with a predetermined organic solvent 62, thereby removing the portion of the uncrosslinked intermediate layer resist material film 4 as shown in FIG. 12. The cross-linked intermediate layer resist film 4b is left. The organic solvent 62 for developing the intermediate layer resist material film 4 may be different from the organic solvent for developing the lower layer resist material film 3. By removing the portion of the intermediate layer resist material film 4 located in the predetermined outer peripheral region of the semiconductor substrate 1, the hump seen in the conventional three-layer resist process does not occur.

  Next, an upper resist film is formed in contact with the intermediate resist film. First, a predetermined upper layer resist material is applied by a resist coating apparatus, and the semiconductor substrate is rotated at a predetermined number of rotations, so that the upper layer resist material film 5 covers the intermediate layer resist film 4b as shown in FIG. It is formed.

  Next, by performing a predetermined photoengraving process on the upper resist material film 5, a predetermined pattern (not shown) is photoengraved on the upper resist material film located in the region where the chip is formed. Next, as shown in FIG. 14, peripheral exposure processing is performed by irradiating the portion of the upper resist material film 5 located in a predetermined outer peripheral region of the semiconductor substrate 1 with exposure light 54. Next, an upper resist film 5b (see FIG. 15) is formed by subjecting the upper resist material film 5 subjected to the photoengraving process and the like to baking under a predetermined temperature condition.

  Next, by performing development processing with a predetermined developer, a predetermined pattern is formed on the upper resist film 5b in the chip formation region CR as shown in FIG. On the other hand, at the outer periphery PR of the semiconductor substrate, the portion of the upper resist film 5b is removed, and the surface of the lower resist film 3b and the surface of the intermediate resist film 4b that are not humped are exposed. Thus, as shown in FIG. 16, a lower resist film 3b, an intermediate resist film 4b, and an upper resist film 5b for patterning the film to be processed 2 are formed. The outer peripheral portion PR in the semiconductor substrate refers to a region including the outer edge of the lower layer resist film 3b, the outer edge of the intermediate layer resist film 4b, and the upper layer resist film 5b.

Next, the processed film 2 is patterned by the lower resist film 3b, the intermediate resist film 4b, and the upper resist film 5b. First, as shown in FIG. 17, the upper resist film 5b is used as a mask to etch the intermediate resist film 4b, whereby the pattern of the upper resist film 5b is transferred to the intermediate resist film 4b. In this case, a material containing silicon (Si) element is applied as the intermediate layer resist material, and etching is performed using, for example, a fluorine-based gas such as CF ₄ , so that a high etching selectivity with respect to the upper layer resist film 5b. Can be obtained.

Next, as shown in FIG. 18, by etching the lower resist film 3b using the intermediate resist film 4b as a mask, the pattern of the upper resist film 5b is changed to the lower resist film 3b via the intermediate resist film 4b. Transcribed. In this case, for example, etching is performed using a gas such as oxygen (O ₂ ) or nitrogen (N ₂ ) / hydrogen (H ₂ ) to obtain a high etching selectivity with respect to the intermediate layer resist film 4 b. Can do.

  Next, as shown in FIG. 19, the processed film 2 is patterned by etching the processed film 2 using the lower resist film 3b as a mask. Thereafter, as shown in FIG. 20, by performing an oxygen plasma ashing process, the lower resist film 3b and the like remaining on the semiconductor substrate 1 are removed, and the patterning of the film to be processed 2 is completed.

  In the semiconductor device manufacturing method described above, the portion of the lower resist material film 3 and the portion of the intermediate layer resist material film 4 that are respectively located in predetermined outer peripheral regions of the semiconductor substrate are removed, and the outer peripheral portion PR of the semiconductor substrate 1 is removed. No hump is formed on the lower resist material film 3 or the intermediate resist material film 4. Thereby, resist residues or processed film residues can be reduced. This will be described with a comparative example.

  In the method of manufacturing a semiconductor device according to the comparative example, first, a lower layer resist material is applied onto a film to be processed formed on the surface of the semiconductor substrate by a resist coating apparatus, and the semiconductor substrate is rotated at a predetermined rotational speed. Thus, as shown in FIG. 21, a lower resist material film 103 having a uniform thickness is formed on the surface of the semiconductor substrate 101.

  Next, as shown in FIG. 22, edge rinsing is performed by discharging the solvent 165 from the solvent discharge nozzle 154 and spraying it on the lower resist material film 103. Next, the lower resist material film 103 is dried. At this time, as shown in FIG. 23, the components of the lower resist material film dissolved and left on the semiconductor substrate 101 may swell and rise to generate a hump 103a. Next, as shown in FIG. 24, the lower resist material film 103 is cross-linked by performing a baking process 166 on the semiconductor substrate 101 at a predetermined temperature, and as shown in FIG. It is formed.

  Next, an intermediate layer resist film 104b is formed through a process similar to the process of applying an intermediate layer resist material to the surface of the semiconductor substrate 101 and forming the lower layer resist film. In the intermediate layer resist film 104b, a hump 104a may be generated when the intermediate layer resist material layer is dried (see FIG. 26). Next, an upper resist material is applied to the surface of the semiconductor substrate 101, and the upper resist film 105b is formed through a process similar to the process of forming the upper resist film in the above-described embodiment. In this way, as shown in FIG. 26, the lower resist film 103b, the intermediate resist film 104b, and the upper resist film 105b for patterning the film to be processed 102 are formed. Humps 103a and 104a are observed in the lower resist film 103b or the intermediate resist film 104b exposed on the outer periphery of the semiconductor substrate 101.

  Next, the processing target film 102 is patterned by the lower resist film 103b, the intermediate resist film 104b, and the upper resist film 105b. First, as shown in FIG. 27, the upper resist film 105b is used as a mask to etch the intermediate resist film 104b, whereby the pattern of the upper resist film 105b is transferred to the intermediate resist film 104b. At this time, since the intermediate layer resist film 104b has a high etching selectivity with respect to the upper layer resist film 5b, the portion of the intermediate layer resist film 104b where the hump 104a is generated may become a resist residue 104c. Many. Further, the hump 103a of the lower resist film 103b often remains without being etched.

  Next, as shown in FIG. 28, by etching the lower resist film 103b using the intermediate resist film 104b as a mask, the pattern of the upper resist film 105b is changed to the lower resist film 103b via the intermediate resist film 104b. Transcribed. At this time, since the lower resist film 103b has a high etching selectivity with respect to the intermediate resist film 104b, a hump 103a is generated at the outer peripheral portion of the semiconductor substrate 101 that should be removed to the lower resist film 103b. In many cases, the portion of the lower resist film 103b that is being formed becomes a resist residue 103c. Further, at the position where the resist residue 104c is located, the resist residue 104c may serve as a mask, and the portion of the lower resist film 103b located immediately below the resist residue 104c may become the resist residue 103d.

  As described above, in the method for manufacturing a semiconductor device according to the comparative example, at the time when a resist mask (such as the lower layer resist film 103b) for patterning the film to be processed 102 is formed, the resist residue is formed on the outer periphery of the semiconductor substrate 101. In many cases, 103c, 103d, and 104c exist.

  Next, as shown in FIG. 29, the processed film 102 is patterned by etching the processed film 102 using the lower resist film 103b and the like as a mask. At this time, where the resist residues 104c and 103d are located, the resist residue serves as a mask, and the portion of the processed film 102 becomes the processed film residue 102b. Further, even in the place where the resist residue 103c is located, the portion of the film to be processed 102 becomes the film residue 102a to be processed.

  Thereafter, as shown in FIG. 30, an oxygen plasma ashing process is performed to remove the lower resist film 103b and the like. At this time, the resist residue 103d may not be completely removed. Further, the processed film residues 102a and 102b are not removed and are left on the outer peripheral portion of the semiconductor substrate 101.

  In the manufacturing method of the semiconductor device according to the comparative example, when the manufacturing process proceeds in a state where the processed film residues 102a and 102b and the like exist on the outer peripheral portion of the semiconductor substrate, the processed film residues 102a and 102b and the like become foreign matters. There is a risk of decreasing the yield of the semiconductor device. In addition, the reliability of the semiconductor device may be lowered due to film peeling.

  In addition, after patterning the upper resist film, if it is necessary to perform a regeneration process (rework process) due to defects such as dimensions and overlay accuracy, the intermediate resist film is etched back using a fluorine-based gas, The lower resist film is ashed using oxygen gas. For this reason, the portion of the intermediate layer resist film or the lower layer resist film cannot often be completely removed at the place where the hump is generated, which becomes a cause of generation of foreign matters.

  On the other hand, there is a method of removing the processed film residues 102a, 102b and the like remaining on the outer peripheral portion of the semiconductor substrate 101, and bevel etching or bevel CMP (Chemical Mechanical Polishing) is generally known. By performing this bevel etching after performing a predetermined etching process and regeneration process, the processed film residues 102a, 102b, etc. are removed. However, when these processes are performed, the underlying semiconductor substrate 101 is damaged, which may affect the yield and reliability of the semiconductor device, and limit the number of times the regeneration process is performed. There is also a need.

  On the other hand, in the method for manufacturing a semiconductor device described above, a resist material having photosensitivity is applied as the lower layer resist film and the intermediate layer resist film, and lower layer resists (materials) located in predetermined outer peripheral regions of the semiconductor substrate, respectively. ) The film portion and the intermediate layer resist (material) film portion are removed. As a result, unlike the conventional three-layer resist process, hump does not occur in the outer peripheral portion of the semiconductor substrate, and the decrease in the yield of the semiconductor device due to the generation of foreign matters can be suppressed. In addition, deterioration of the reliability of the semiconductor device due to film peeling can be suppressed.

  In addition, after patterning the upper resist film, all resists can be used without damaging the underlying layer (film, semiconductor substrate, etc.) even if it is necessary to perform a regeneration process due to defects such as dimensions or overlay accuracy. The film can be completely removed, and then a resist pattern can be formed again. Further, since there is no damage to the underlying semiconductor substrate due to the regeneration process, there is no need to limit the number of times the regeneration process is performed.

  Furthermore, in the semiconductor device manufacturing method described above, each resist film is removed by performing an exposure process on a portion of the resist (material) film located in each outer peripheral region of the semiconductor substrate, thereby removing the edge rinse. The position accuracy (controllability of dimensions) of the outer edge can be improved. This will be described.

  When the exposure process is performed on the resist (material) film portions located in the respective outer peripheral regions of the semiconductor substrate, as shown in FIG. 31, the variation width L1 of the outer edge position of the lower resist film 3b and the outer edge of the intermediate resist film 4b The position variation width L2 and the outer edge position variation width L3 of the upper resist film 5b are both about 0.1 mm (± 0.05 mm). Therefore, the outer edge of the intermediate layer resist film 4b is arranged inside the outer edge of the lower layer resist film 3b, and further, the outer edge of the upper layer resist film 5b is arranged inside the outer edge of the intermediate layer resist film 4b. For example, the distance P between the outer edge of the lower resist film 3b and the outer edge of the upper resist film 5b (the total variation width of the outer edge position) needs to be about 0.3 mm.

  On the other hand, in the comparative example in which the edge rinse is performed, as shown in FIG. 32, the variation width PL1 of the outer edge position of the lower resist film 103b and the variation width PL2 of the outer edge position of the intermediate layer resist film 104b are Also, the variation width PL3 of the position of the outer edge of the upper resist film 105b is about 0.1 mm (± 0.05 mm). Therefore, when the outer edge of the intermediate layer resist film 104b is arranged inside the outer edge of the lower layer resist film 103b, and further, the outer edge of the upper layer resist film 105b is arranged inside the outer edge of the intermediate layer resist film 104b. The distance PL between the outer edge of the lower resist film 103b and the outer edge of the upper resist film 105b (the total variation width of the outer edge positions) needs to be about 1.3 mm.

  In FIG. 32, the hump is exaggerated and does not accurately reflect its size. The height of the hump is about several times the thickness of the resist material film to be applied (several hundred nm to 1 μm), and the width of the region where the hump occurs (the length in the radial direction of the semiconductor substrate) is About 5 μm to 10 μm.

  Therefore, in the manufacturing method of the semiconductor device described above that performs the exposure process, the effective area on which the semiconductor device (chip) is formed can be increased as compared with the manufacturing method of the semiconductor device according to the comparative example that performs edge rinsing.

(Registration materials)
In the semiconductor device manufacturing method described above, examples of the base polymer, the photoacid generator, and the crosslinking agent shown in (Chemical Formula 1) to (Chemical Formula 3) are given as examples of the base polymer, the photoacid generator, and the crosslinking agent of the lower layer resist material. In addition, as a base polymer for the intermediate layer resist material, the base polymer represented by (Chemical Formula 5) has been described as an example. Here, a resist material applied as a lower layer resist film or an intermediate layer resist film in the above-described semiconductor device manufacturing method will be described.

  First, a resist material applied as a conventional general lower layer resist film or intermediate layer resist film in a three-layer resist process is composed of a base polymer, a crosslinking agent, a thermal acid generator, and a solvent. In this resist material, the thermal acid generator is decomposed by baking after spin coating, and an acid is generated in the resist material film. The generated acid causes a crosslinking reaction between the base polymer and the crosslinking agent.

  On the other hand, the resist material applied as the lower layer resist film or intermediate layer resist film used in the semiconductor device manufacturing method described above generates thermal acid in the resist material applied as the conventional lower layer resist film or intermediate layer resist film. It is a material in which the agent is replaced with a photoacid generator. Hereinafter, the resist material will be described in detail.

(About lower layer resist material)
Since the lower resist film is required to have high etching resistance, flattening of the underlying step and antireflection effect, a base polymer generally containing a high concentration of an aromatic ring such as a phenol resin is used. Also, it is necessary to crosslink the polymer so that the lower layer resist film does not dissolve in the solvent of the intermediate layer resist material so that the lower layer resist film and the intermediate layer resist (material) film applied thereon are not mixed. There is.

  Therefore, the lower layer resist material used here is composed of at least a base polymer, a crosslinking agent, a photoacid generator, and a solvent. Examples of the base polymer include polymers containing a benzene skeleton, a naphthalene skeleton, an anthracene skeleton, a fluorene skeleton, a pyrene skeleton, and the like. Examples of the crosslinking agent include compounds having at least two amino groups of melamine, urea, benzoguanamine, and glycoluril substituted with a methylol group or an alkoxymethyl group and having two or more reactive groups. The photo acid generator (PAG) may be the same as that usually used for the chemically amplified resist, and examples of the most effective photo acid generator include iodonium salts and sulfonium salts. In addition, photoacid generators such as imide sulfonates, diazomethanes, and organic halides may be used.

  The solvent is not particularly limited as long as it is an organic solvent in which the above-described base polymer, crosslinking agent, photoacid generator, and other additives are dissolved. For example, cyclohexanone, ketones, alcohols, ethers, esters, Examples include lactones. Examples of ketones include methyl-2-amyl ketone. Examples of alcohols include 3-methoxybutanol, 3-methyl-3-methoxybutanol, 1-methoxy-2-propanol, 1-ethoxy-2-propanol and the like. Examples of ethers include propylene glycol monomethyl ether, ethylene glycol monomethyl ether, propylene glycol monoethyl ether, ethylene glycol monoethyl ether, propylene glycol dimethyl ether, and diethylene glycol dimethyl ether. Esters include propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, ethyl lactate, ethyl pyruvate, butyl acetate, methyl 3-methoxypropionate, ethyl 3-ethoxypropionate, tert-butyl acetate, tert-propionic acid Examples include butyl, propylene glycol monomethyl ether acetate, and propylene glycol mono tert-butyl ether acetate. Examples of lactones include γ-butyrolactone.

  Of these solvents, one solvent or a mixture of two or more solvents may be used. Of these, diethylene glycol dimethyl ether, 1-ethoxy-2-propanol, ethyl lactate, propylene glycol monomethyl ether acetate, propylene glycol monomethyl ether, and mixed solvents thereof are preferable.

(Regarding the interlayer resist material)
A polymer containing a high concentration of silicon (Si) atoms is used for the intermediate layer resist film in order to have etching selectivity with respect to the upper layer resist film and the lower layer resist film. In addition, it is necessary to crosslink the polymer so that the intermediate layer resist film does not dissolve in the solvent of the upper layer resist material so that the intermediate layer resist film and the upper layer resist (material) film applied thereon are not mixed. There is.

  Therefore, the intermediate layer resist material used here is composed of at least a base polymer, a photoacid generator, and a solvent. Moreover, in order to further promote the crosslinking reaction of the base polymer, a crosslinking agent may be further contained. Examples of the base polymer include a siloxane polymer, a silazane polymer, a silsesquioxane polymer in which a carbonyl group, an ester group, a lactone group, or an ether group is pendant. As the crosslinking agent, photoacid generator and solvent, the same crosslinking agent, photoacid generator and solvent as in the case of the lower layer resist material can be used.

  In the semiconductor device manufacturing method described above, the case of performing the peripheral exposure process using the positive resist material as an example of the upper resist film has been described. However, the negative resist material is applied as the upper resist film. May be. In this case, the portion of the upper resist material film located in the peripheral region is not irradiated with exposure light, and the portion may be removed by development processing.

Embodiment 2
Here, an example of an exposure apparatus applied to the multilayer resist process will be described. As shown in FIGS. 33 and 34, the exposure apparatus 50 includes a stage 51 on which the semiconductor substrate 1 is placed, a light source unit 52 for exposure light, and a blind 53 for blocking exposure light. The light source unit 52 is arranged at a distance so as to face the semiconductor substrate placed on the stage 51. The light source unit 52 is preferably a high-pressure mercury lamp (i-line: wavelength = 365 nm), a KrF excimer laser (wavelength = 248 nm), or the like, and has a broad wavelength including an ultraviolet region even if it is not a single wavelength light. It may be a light source that emits light.

  As long as the blind 53 can cover a predetermined outer peripheral region extending along the outer edge of the semiconductor substrate placed on the stage 51 and can block exposure light from being irradiated to the outer peripheral region, The material is not limited. The stage 51 may be provided with a heating mechanism (not shown) for heating the mounted semiconductor substrate.

  In the exposure apparatus described above, the exposure light is blocked by the blind 53 so that the lower resist material film portion and the intermediate resist material film portion located in the respective predetermined outer peripheral regions of the semiconductor substrate are not cross-linked. Thereby, the lower resist material film portion and the intermediate resist film portion, which are respectively located in predetermined outer peripheral regions, can be dissolved in the developer and removed. As a result, a lower resist film or an intermediate resist film without hump can be formed. Even if edge rinsing is performed on the lower layer resist material film and the intermediate layer resist material film, the exposure light is blocked so as not to crosslink the resist material so as to include the portion where the hump is generated. It can be removed by dissolving in a developer.

  Note that the exposure apparatus described above may be an exposure apparatus having an aspect in which a function corresponding to a blind is provided in an original exposure apparatus for photoengraving a circuit pattern or the like. Further, the above-described exposure device (function) may be incorporated in the developing device.

Embodiment 3
Here, an example of a more specific method for manufacturing a semiconductor device to which a multilayer resist process is applied will be described. First, as shown in FIG. 35, the surface of the semiconductor substrate 1 is subjected to a thermal oxidation process, whereby the insulating film 19 is formed. On the insulating film 19, for example, a conductive film 20 including a polysilicon film and a metal silicide film thereof is formed.

  Next, a three-layer resist process is applied as a photolithography process for patterning the gate electrode. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 16 is applied to form a lower resist film 21, an intermediate resist film 22, and an upper resist film 23 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 23a of the upper resist film 23 for patterning the gate electrode is formed. On the other hand, in the outer peripheral portion PR of the semiconductor substrate 1, the intermediate layer resist film 22 and the lower layer resist film 21 without hump are exposed.

  Next, by etching the intermediate layer resist film 22 using the resist pattern 23a of the upper layer resist film 23 as a mask, the resist pattern 23a is transferred to the intermediate layer resist film 22 as a resist pattern 22a. Further, the intermediate layer resist film By etching the lower resist film 21 using the resist pattern 22a of 22 as a mask, the resist pattern 23a is transferred to the lower resist film 21 as the resist pattern 21a.

  Thus, as shown in FIG. 37, resist patterns 23a, 22a, and 21a are formed by the lower layer resist film, the intermediate layer resist film, and the upper layer resist film for patterning the gate electrode. Note that FIG. 37 shows a state where the resist pattern 23a of the upper resist film 23 is left, but it is sufficient that at least the resist pattern 21a of the lower resist film 21 is left.

  Next, the conductive film 20 is etched using the resist patterns 23a, 22a, and 21a as a mask, thereby forming the gate electrode 20a as shown in FIG. Next, using the gate electrode 20a as a mask, an n-type impurity region 24a is formed by implanting, for example, an n-type impurity at a low dose into the semiconductor substrate 1 (see FIG. 39). Next, an insulating film (not shown) is formed so as to cover the gate electrode 20a. By performing anisotropic etching on the insulating film, a sidewall insulating film 25 is formed on the side wall of the gate electrode 20a (see FIG. 39).

  Next, by using the gate electrode 20a and the sidewall insulating film 25 as a mask, an n-type impurity is implanted at a high dose, thereby forming an n-type high concentration impurity region 24b. Thus, as shown in FIG. 39, the MOS (including the gate electrode 20a, the n-type low-concentration impurity region 24a, and the n-type high-concentration impurity region 24b formed on the surface of the semiconductor substrate 1 with the gate insulating film 19a interposed therebetween. Metal Oxide Semiconductor) transistors are formed. Next, an interlayer insulating film 26 such as a silicon oxide film is formed on the semiconductor substrate 1 so as to cover the gate electrode 20a and the like (see FIG. 40).

  Next, a three-layer resist process is applied as a photoengraving process for forming contact holes in the interlayer insulating film 26. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 16 is applied to form a lower resist film 27, an intermediate resist film 28, and an upper resist film 29 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 29a of the upper resist film 29 for forming a contact hole is formed. On the other hand, in the outer peripheral portion PR of the semiconductor substrate 1, the intermediate layer resist film 28 and the lower layer resist film 27 without hump are exposed.

  Next, the resist pattern 29a of the upper resist film 29 is transferred to the intermediate resist film 28 and the lower resist film 27 to form a resist pattern (not shown) for forming contact holes. By performing anisotropic etching on interlayer insulating film 26 using the resist pattern as a mask, contact hole 30 exposing the surface of n-type high concentration impurity region 24b is formed as shown in FIG. Thereafter, the resist pattern is removed. Next, as shown in FIG. 42, a predetermined conductive film 31 including a barrier metal or the like is formed on the interlayer insulating film 26 so as to fill the contact hole.

  Next, a three-layer resist process is applied as a photolithography process for patterning the conductive film 31. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 16 is applied to form a lower resist film 32, an intermediate resist film 33, and an upper resist film 34 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 34a of the upper resist film 34 for patterning the conductive film 31 is formed. On the other hand, the intermediate layer resist film 33 and the lower layer resist film 32 without hump are exposed at the outer peripheral portion PR in the semiconductor substrate 1.

  The resist pattern 34a of the upper resist film 34 is transferred to the intermediate resist film 33 and the lower resist film 32, and a resist pattern (not shown) for patterning the conductive film is formed. By performing anisotropic etching on the conductive film 31 using the resist pattern as a mask, a wiring 31a electrically connected to the n-type high concentration impurity region 24b is formed as shown in FIG. Thereafter, the lower resist film 32 and the like are removed. Thus, a main part of the semiconductor device including the transistor is formed.

  In the semiconductor device manufacturing method to which the three-layer resist process is applied as the photoengraving process described above, the lower resist (material) film portions and intermediate portions located in predetermined outer peripheral regions of the semiconductor substrate without being exposed to exposure light. By dissolving the layer resist (material) film portion in a developing solution and removing it, a lower resist film and an intermediate resist film without humps can be formed. Thereby, the resist residue or the processed film residue is reduced in the outer peripheral portion of the semiconductor substrate 1 after patterning the processed film such as the conductive film 20, the interlayer insulating film 26, and the conductive film 31. As a result, it is possible to suppress a decrease in yield of the semiconductor device due to the generation of foreign matter, and it is possible to suppress deterioration in reliability of the semiconductor device due to film peeling.

  Note that the above-described three-layer resist process is not limited to the steps described in Embodiment 1 or Embodiment 3, and can be widely applied to the steps in which photolithography is performed. The photolithography process is not limited to the three-layer resist process, and the resist pattern transferred to the photosensitive resist has an etching resistance in relation to the etching of the film to be processed, and the photosensitive resist film. As long as it is a process for transferring to a two-layer resist, it can be applied to a two-layer resist process or a four-layer or more resist process.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a manufacturing method of a semiconductor device to which a multilayer resist process is applied.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Processed film, 3 Lower resist material film, 3b Lower resist film, 4 Intermediate resist material film, 4b Intermediate resist film, 5 Upper resist material film, 5b Upper resist film, 19 Insulating film, 19a Gate Insulating film, 20 conductive film, 20a gate electrode, 21 lower resist film, 21a resist pattern, 22 intermediate resist film, 22a resist pattern, 23 upper resist film, 23a resist pattern, 24a n-type low concentration impurity region, 24b n-type High concentration impurity region, 25 sidewall insulating film, 26 interlayer insulating film, 27 lower resist film, 28 intermediate resist film, 29 upper resist film, 29a resist pattern, 30 contact hole, 31 conductive film, 31a conductive film, 32 lower layer Resist film, 33 Intermediate layer resist film 34 upper resist film, 34a resist pattern, 41 a base polymer, 42 crosslinking agent, 43 crosslinked polymers, 50 wafer exposure apparatus, 51 stages, 52 a light source unit, 53 blind, 54 exposure light, 61 heat, 62 developer.

Claims (8)

Forming a film to be processed on the main surface of the semiconductor substrate;
Applying a first resist material so as to cover the film to be processed;
Forming a first film with a first resist material applied on the film to be processed;
Of the first film covering the film to be processed, except for the portion of the first film located in the outer peripheral region extending along the outer edge up to a predetermined distance from the outer edge of the semiconductor substrate to the inside. Irradiating the entire surface of the portion of the first film located inside the outer peripheral region with exposure light;
Applying heat treatment at a first temperature;
Removing a portion of the first film located in the outer peripheral region that is not irradiated with the exposure light by performing a development process with a predetermined developer;
Forming a second film of the second resist material on the first film by applying at least a second resist material so as to cover the first film;
Forming a predetermined pattern by subjecting the second film to a predetermined photolithography process;
By removing the portion of the first film exposed from the predetermined pattern of the second film, the pattern of the first film corresponding to the predetermined pattern is formed on the first film. Process,
And a step of removing the portion of the film to be processed exposed from the pattern of the first film.   After the step of forming the first film, before the step of forming the second film, a step of performing a heat treatment on the first film at a second temperature higher than the first temperature. A method of manufacturing a semiconductor device according to claim 1. Forming the predetermined pattern on the second film,
Performing a peripheral exposure on the second film;
The method of manufacturing a semiconductor device according to claim 1, further comprising: removing the portion of the second film located in the area where the peripheral exposure has been performed by performing the development process. Forming the predetermined pattern on the second film,
Of the second film, except for the part of the second film located in the outer peripheral area extending along the outer edge from the outer edge of the semiconductor substrate to a predetermined distance from the outer edge of the semiconductor substrate. Irradiating exposure light to a portion of the second film located inside;
The method for manufacturing a semiconductor device according to claim 1, further comprising: removing the portion of the second film located in the outer peripheral region that is not irradiated with the exposure light by performing the development process. . In the step of forming the second film, before applying the second resist material,
Applying a third resist material so as to cover the first film;
Of the third resist material covering the first film, except for the third resist material portion located in the outer peripheral region, the entire surface of the third resist material portion located inside the outer peripheral region. Irradiating with exposure light;
A step of accelerating a crosslinking reaction of a portion of the third resist material irradiated with the exposure light by performing a heat treatment at a predetermined temperature;
By performing development processing with a predetermined developer, the portion of the third resist material in which the cross-linking reaction is promoted is left, and the exposure light is not irradiated and the outer peripheral region is not cross-linked. Removing a portion of the third resist material;
Forming the predetermined pattern on the second film,
Forming the predetermined pattern on a second resist film formed of the second resist material;
By removing a portion of the third resist film formed by the third resist material exposed from the predetermined pattern formed on the second resist film, the third resist film corresponding to the predetermined pattern is removed. Forming a pattern,
The step of forming the pattern of the first film includes a step of removing at least a portion of the first film exposed from the pattern of the third resist film. Semiconductor device manufacturing method.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. A stage for holding a semiconductor substrate;
A light source unit disposed at a predetermined position spaced from the stage so as to face the semiconductor substrate held on the stage;
Exposure light emitted from the light source unit, which is disposed between the light source unit and the stage, is applied to a predetermined outer peripheral region extending along the outer edge of the semiconductor substrate held by the stage. An exposure apparatus comprising a blind for blocking.   The exposure apparatus according to claim 7, wherein the stage includes a heating unit that heats the semiconductor substrate to a predetermined temperature.

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