JP2000156048A - Semiconductor device using judgment feedback equalizer and digital signal recording and reproducing device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase further density of a magnetic disk by detecting that a different point is one bit in the prescribed block in two discrimination result groups, referring to whether total numbers of +1 of recording signals previously set are even numbers or odd numbers, and correcting this one bit. SOLUTION: Two CSE values in an eraser zone are obtained by arithmetic circuits M-10-1, M-10-2, they are compared by a comparator M-7, a less group is selected by a selector M-8 based on the compared result. As total numbers of +1 in a recording signal are set to even numbers for each prescribed block in a final result output circuit M-11, total numbers of +1s in a discriminated result are counted for each prescribed block, when they are even numbers, an output of the selector M-8 is made a final output F-out assuming that an error does not exist. When odd numbers are detected, it is judged whether they are conditions which can be corrected or not, when conditions are satisfied, they are corrected, and made the final result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a signal processing circuit for digitally recording digital data on a recording medium such as a magnetic disk at a high density, and a digital signal recording / reproducing apparatus using the same. Specific products include read channel LSIs for magnetic disks,
Digital signal recording / reproducing devices such as magnetic disk devices, magnetic tape devices, and magneto-optical recording devices using the LSI. The specific contents of the technique relate to the improvement of the decision feedback equalizer.

[0002]

2. Description of the Related Art As the operation speed of computers increases, application software that requires a large-capacity memory is used, and the demand for high-density compact magnetic disk drives is increasing. The magnetic disk device includes a magnetic head, a recording medium, a servo system for mechanically controlling them, and a signal processing system for recording digital signals on the recording medium via the magnetic head. For high-density recording, it is extremely important to improve the performance of magnetic heads and recording media and to improve signal processing techniques. For this reason, recently, partial response class 4 (hereinafter referred to as PR4) has been used as signal processing for recording and playback systems.
The PRML method that combines the equalization method and the maximum likelihood decoding and its advanced form are used. Regarding these technical features, see, for example, Journal of the Japan Society of Applied Magnetics 17-2, 4 No. 1994
In "PRML and Coding Techniques" in August. This method assumes a digital magnetic recording / reproducing system as a linear filter, and its impulse response h (D) is h (D) =
It is assumed that (1-D) (1 + D) ⁿ can be expressed. Here, D is an operator representing 1-bit delay, and n is a positive integer. As the linear recording density increases, n increases, and from n = 1 at the beginning to n = 3 recently. However, if the linear recording density becomes higher in the future, the deviation from the linear filter, which is the premise of the above signal processing, becomes a problem. The reason for this is that the ratio of the length of one bit on the recording medium to the diameter of the average magnetic particle becomes as small as 10: 1 or less, and the interaction between adjacent bits becomes stronger.

[0003] Improvements in magnetic recording media are of course considered, but it is necessary to cope with them in signal processing. That is, when information data is converted into a recording signal and recorded on the recording medium, the magnetization reversal interval corresponding to the bit length on the recording medium is lengthened to reduce the actual linear recording density.
More specifically, if a (1, 7) run-length limited recording code (hereinafter, simply referred to as a (1, 7) code) is used, the magnetization reversal width is smaller than the latest PRML recording code (16/17 code). 1.42 times wider. Note that the (1, 7) code is used before PRML, and is not particularly new. Currently being reviewed from the viewpoint of the magnetization reversal width.

On the other hand, in the read signal processing, the impulse response of the recording / reproducing system is calculated as 1 + b ₁ D + b ₂ D ² + b ₃ D
³ +. . . . Decision Feedback Equalization (hereinafter referred to as DFE) in which coefficients have a degree of freedom has been proposed. Its features are (1) a simple circuit configuration and (2) a small change in performance with respect to fluctuations in characteristics of a magnetic head, a recording medium, and the like. However, there is a problem in error propagation. For this reason, for example, Japanese Patent Application No. 10-36998 discloses one method for coping with error propagation of DFE. Recently, MDFE specialized in (1,7) code while utilizing the features of DFE
(Multilevel DFE) has been proposed. Although the circuit configuration is simple, the performance is comparable to that of PR4ML, and error propagation, which is a fundamental problem of DFE, has a strong restriction on recording codes, so that countermeasures are easy. Further, M
An M2DFE with an improved DFE has been proposed. For more information on this, see Data Storage Volume 5
No. 8 (July 1998) pages 35 to 48 or IEEE transaction on
Magnetics Vol. 34 No. 4 (1998)
It is described on pages 1919 to 1921.
M2DFE exhibits almost the same characteristics as EPRML. However, this comparison result is a comparison at a linear recording density without considering the interaction between adjacent bits. In the future, the linear recording density will be further increased, and the superiority of M2DFE based on the (1,7) code will appear.

The recording codes 1 and 0 mean that 1 is magnetization reversal and 0 is magnetization holding.
7) Code indicates that the minimum number d between a certain 1 and the next 1 is 1 and the maximum number k is 7 in the recording code sequence. Therefore, the (1, 7) code whose conversion rule is easy is d
= 1.

From the above, in consideration of the fact that the substantial linear recording density can be reduced, the recording code shifts from the d = 0 code used in the PR system to the d = 1 code. Therefore, d
The signal processing of MDFE and M2DFE suitable for = 1 code is important. Further, if the magnetic disk device is recorded at a high density also in the track width direction, a signal having a lower signal-to-noise ratio will be reproduced.
There is a need to further improve the characteristics of 2DFE. In the present invention, an improvement of the M2DFE will be described. Before that,
The configuration of DFE, MDFE, and M2DFE will be outlined.

[0007] The impulse response of the pre-equalization filter of the DFE is 1 + b1 (D) + b2, where D is a delay operator.
(D ² ) +. . . + ^Bn (D ⁿ ). b indicates a coefficient. Normally, n is set to 10 or more, which allows a longer response than signal processing of the PR system. For this reason, the frequency characteristic of the pre-equalization filter can lower the response from a lower frequency than that of the PR system. This makes the pre-equalization filter output, ie, the signal-to-noise ratio at the discrimination point, more advantageous than the PR system. At the discrimination point, a feedback signal corresponding to a response obtained by inverting the impulse response of the pre-equalization filter from the result of the discrimination already performed, that is, -b1 (D)-in the DFE.
b2 (D ²⁾ -. . . -Bn (D ⁿ⁾ is added. Therefore, at the identification point, ± 1 may be identified by a simple slicer.

In MDFE, the impulse response is set to 0.5
+ D + 0.5D ² + b3 (D ³ ) +. . . + ^Bn (D ⁿ )
Set to. Further, the feedback signal is changed to −b3 (D ³ )
−. . . −bn (D ⁿ ). Therefore, so that the 0.5 + D + 0.5D ² of the impulse response remains. The discrimination point is provided with a 3-bit interfering signal.
For example, when the recording code is 010, the recording signal corresponding to the magnetization on the recording medium becomes +,
-,-Or-, +, +. In the case of +,-,-, the slicer input signal value in the last bit is assumed to be free of noise, and the impulse response of the first bit is +0.5, and the value of the second bit is -1.
Since the response of 0 and the response of the third bit -0.5 are added, the target signal value becomes -1.0. This value is identified by the slicer and used as the identification result for the second bit at the center.
In the same way, if +++ is +2, +++ is +1,-++
+ At +1,--at -2,-,-, + at -1, +-
It can be seen from −1 that −1 is the target signal value. +-+,
− + − Is prohibited by the (1,7) code rule. Therefore, the target signal value is four values of +2, +1, -1, and -2, and the read signal can be identified by distinguishing + and-with the slicer. In the case that the time when the magnetization is reversed on the recording medium is included, the discrimination of ± 1 is made, and the recording medium is easily affected by noise. That is, if the superimposed noise n at this time is n> 1, an identification error occurs.

On the other hand, if two slicers are prepared and the slicer level is set to be offset to + α and −α, if the noise is up to n = 1 + α, one of the slicers performs correct identification. . If the correct discrimination result can be selected by any method, it is possible to cope with noise up to 1 + α. One of the solutions is M2DFE. The configuration is shown in FIG. Reference numeral 7 denotes a mechanical system of a magnetic disk including a magnetic head and a recording medium. The read signal obtained from the read head 7 is amplified by the reproduction amplifier circuit 8 to a predetermined magnitude. Pre-equalization filter (Fo
(ward equalizer) M-1 performs an equalization process on the head read signal so that the impulse response of the recording signal is given in the above-described format. The output signal of the pre-equalization filter is input to adders M-2-1 and M-2-2. Each corresponding slicer M-3-1, M-
3-2 (hereinafter simply referred to as slicer 1 and slicer 2) is a feedback filter (FBF) M-4-
1. A feedback signal is generated by M-4-2. The slicer is offset by + α, and the slicer 2 is offset by −α. α is usually set to 0.3 to 0.35. The identification result of each slicer is stored in a buffer (Buffe).
r) A predetermined bit is delayed by M-5-1 and M-5-2, and one of the identification results is selected by the selector M-8. The criterion for selection is the result of squaring the difference between the target signal value in the case where there is no noise estimated from the identification result and the input signal of the slicer, and adding the square value during a predetermined bit period (referred to as CSE value). Are compared in two series, and the smaller one is selected. The calculation of the CSE value is performed by the CSE circuits M-6-1 and M-6-2, and the comparison is performed by the comparator (C
omp. ) Perform at M-7. The CSE circuit is operated by a predetermined number of bits after the absolute value of the input signal of the slicer becomes smaller than α. A period during which the CSE circuit is operating is called an erasure zone. Also, after entering the erasure zone, that is, in the erasure zone 2
After the bit, α = 0 is set.

The effect of the M2DFE will be described with reference to the signal waveform diagram of FIG. C is an example of a (1, 7) encoded digital signal sequence. 0 is always 1 between 1 and 1
There are more than R is a corresponding recording signal. S is an input signal to the slicers 1 and 2 when there is no superimposed noise and there is no error in the feedback signal. Actually, the noise N is superimposed.
The slicer input values taking noise N into consideration are SL1 and S, respectively.
L2, and the identification results are RE1 and RE2. It is assumed that there is no error in either slicer until the first noise N = -1.0 in the figure is superimposed. Although a large noise is superimposed as N = −1.0, both slicers are correctly identified because the original signal value is S = + 2. Further, the slicer input value is SL1 = SL2 = 1.0, which is larger than the offset value α, and therefore does not enter the erasure zone. At the next noise N = -1.1, the slice input value is SL1 = SL2 = -0.1. If the offset value α is set to α = 0.3, since the absolute value of the signal is equal to or smaller than α, it is determined that a suspicious signal has arrived and the erasure zone is set. Slicer 1 is α = 0.3
, And is identified as-. Also, since slicer 2 is offset at α = −0.3,
Identify as +. Since different identification results are given, either one is the correct identification. Since the identification result is reflected in the feedback signal two bits later, the two slicer input values are still the same at the next time. After that, the influence of the erroneous identification feedback signal appears. The respective target signal values SS1, SS2 expected from the respective slicer identification results are calculated. From the difference between the input signal value of the slicer and the target signal value, C
Calculate the SE value. The operation for 5 bits is as follows. In the identification result of the slicer 1, (−1 − (− 0.1)) ² + (− 2 − (− 1.2)) ² +
(−2 − (− 0.6)) ² + (− 1 − (− 0.3)) ² +
(1-1.4) ² = 4.06 On the other hand, in the slicer 2, (1-(− 0.1)) ² + (−
1-(− 1.2)) ² + (− 1 − (− 0.7)) ² + (−
1 − (− 0.6)) ² + (1−1.0) ² = 3.1. Therefore, it is assumed that the identification result of the slicer 2 having the smaller CSE value is correct. At this time, the difference between the CSE values is as small as 0.96.

It should be noted that the slicer 1 is rather smaller and the slicer 2 is larger in the CSE value of only the first bit of the erasure zone. But,
As described above, by calculating the 5-bit CSE value, a correct identification sequence can be obtained. The CSE value is usually calculated from the first bit of the erasure zone to about 8 bits or 15 bits. From the above,
If the superimposed noise at the time after the time when the erasure zone is set is relatively small, in the erroneously identified sequence, a difference appears between the target signal value and the input signal of the slicer due to an erroneous feedback signal, and the CSE value is reduced. growing. on the other hand,
Since the difference between the target signal value and the input signal of the slicer is small in a correctly identified sequence, the CSE value of the sequence is kept small. By selecting a sequence having a small CSE value, a correct sequence can be selected. As a result, M2DFE becomes MDF
Compared with E, the error rate is improved by one digit, and the signal-to-noise ratio of the read head output is improved by about 1 dB.

If the value of α is reduced, noise exceeding 1 + α is not set as an erasure zone and remains erroneously identified. On the other hand, if α is set large, the frequency of entering the erasure zone increases. Since α = 0 in the erasure zone, the operation is the same as that of the MDFE operation, the probability of erroneous identification with respect to noise increases, and the probability that two sequences do not have correct identification results increases. Therefore, there is an optimum value for α. As described above, α is usually set to 0.3 to 0.35.

However, even in M2DFE, if the superimposed noise is large and the noise is superimposed in a direction to cancel the erroneous feedback signal, the erroneously identified sequence has a smaller CSE value than the correctly identified sequence. May be smaller. As a result, an incorrect identification sequence is selected. In particular,
When the difference between the CSE values in the two series is small, erroneous selection due to the CSE value is likely to occur.

[0014]

An object of the present invention is to use a recording code of d = 1 in order to cope with a high density in a magnetic disk.
The purpose is to improve the characteristics based on DFE. Specifically, it is a countermeasure against erroneous selection due to the CSE value when the difference between the CSE values of the two streams is small. Therefore, an object of the present invention is to detect the erroneous selection using the restriction of the recording code and correct it when the difference between the CSE values of the two streams is small. This further increases the density of the magnetic disk.

[0015]

According to the semiconductor device of the present invention, in the recording coding of d = 1, the recording signals are +1 and-.
When represented by 1, as signal processing on the recording side, means for presetting the total number of +1 to an even or odd number within a predetermined block, two decision feedback equalizers on the reproduction side, Means for comparing the CSE values of the two identification result sequences in the erasure zone in the provisional identification result of the erasure zone, and, when the difference is small, determining that a different place in the two identification result sequences is 1 bit in a predetermined block. Means for detecting, means for storing the location of the one bit, and correction of the one bit by referring to whether the total number of +1 of the preset recording signal in the predetermined block is even or odd. Means. Further, the magnetic disk device of the present invention uses the above-described recording / reproducing signal processing.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to embodiments. FIG. 3 is a signal processing system diagram of a read channel semiconductor device A equipped with the signal processing of the present invention and a magnetic disk drive using the same. Reference numeral 1 denotes an interface circuit for transmitting and receiving information data between a magnetic disk drive and a computer (not shown). Reference numeral 2 denotes a check code insertion circuit that calculates a check code for error correction for information data of a predetermined length to be recorded and inserts the check code. This error correction is a high-order error correction means for dealing with a long code error such as a defect in a recording medium, and does not mainly focus on a code error due to noise. Numeral 3 is a randomizing circuit for adding data of a predetermined random sequence to the information data to randomize data to be recorded as much as possible so that a fixed signal pattern is not repeated. 4 is according to the present invention (1-7)
It is an encoding circuit. The encoding circuit performs (1-7) encoding, and when the recording code is 1, the polarity of the recording signal is inverted, and when the recording code is 0, the recording signal is held so that the polarity of the recording signal is maintained. Output. Further, the encoding is controlled so that the number of bits of the positive polarity (represented by +1) of the recording signal becomes an even number for each predetermined block. Reference numeral 5 denotes a flip-flop for determining whether the total number of +1 of the recording signal is even or odd for each predetermined block. Reference numeral 6 denotes a recording amplifier circuit for amplifying a recording signal into a signal necessary for recording on a recording medium by a magnetic head. Reference numeral 7 denotes a recording / reproducing mechanism system including a magnetic head and a recording medium. Reference numeral 8 denotes a reproducing amplifier circuit for amplifying a read signal from the magnetic head for subsequent processing. 9 is an improved M2DFE according to the present invention
Circuit. In order to obtain the final identification result, it is determined for each predetermined block whether the read signal has an even parity. A decoding circuit 10 performs (1, 7) decoding from the read signal. However, this decoding circuit removes additional data for setting even parity for each predetermined block. Reference numeral 11 denotes an inverse randomizing circuit that restores the randomization processed on the recording side. Reference numeral 12 denotes an error correction circuit that corrects the remaining code errors.

As described in the related art, in the M2DFE, when the difference between the CSE values of the two streams becomes small, erroneous selection based on the CSE value must be considered. For example, in the case of the example shown in FIG. 2, if the noise to be superimposed changes, RE1 may be selected. However, as can be seen from the figure, when an incorrect selection is made,
In many cases, the identification result differs between the two streams only in the first bit of the erasure zone. Moreover, by actually comparing the two identification results, it is possible to specify a different place. Therefore, if a 1-bit error occurs only once in a given block,
If the total number of +1 recording signals is predetermined to be an even number in a predetermined block, a one-bit error can be corrected after reading the predetermined block. The procedures (E1) to (E4) are as follows. (E
1) With respect to the erasure zone set in a predetermined block, a difference in the CSE value between two sequences is detected, and it is confirmed that the difference is found only once in the predetermined block. If it is two or more times, there is a possibility that there are two or more error bits, so the following correction operation is not performed. (E2)
In the erasure zone where the difference in CSE value is small, the identification results of the two identification systems are compared to confirm that there is only one different bit, and the location is stored. If it is 2 bits or more, the following correction operation is not performed. (E3) The total number of +1 of the identification result in the predetermined block is calculated.
(E4) If it is an even number, it is determined that there is no error in the predetermined block, and the identification result selected by the CSE value is left as it is. If it is an odd number, it is determined that there is an error and (E
The identification result of the location stored in 2) is inverted and error correction is performed.

As the predetermined block, for example, information bit 5
00 bits, that is, 750 as the number of bits of the recording signal
Even for each bit, if the error rate is about 10 −5,
It has been confirmed by simulation that the probability that the difference between the CSE values is reduced within a predetermined block is hardly twice or more, and that the above-described correction operation functions normally.

From the above, the core technology of the present invention is (1) to make the total number of +1 of the recording signal even for each predetermined block. (2) A circuit for implementing the one-bit error correction means (E1) to (E4) described above for reading. First, the (1, 7) encoding circuit 4 with an even number function of the total number of +1 in the recording signal will be described.

Table 1 shows the rules of (1, 7) encoding in the embodiment.

[0021]

[Table 1]

Note that X indicates that processing can be performed regardless of whether it is 0 or 1. Not (00) indicates a case other than 00.

As can be seen from the rule table, this (1, 7)
As the recording code, a recording code of 3 bits is given by the information 2 bits and the next information 2 bits while referring to the immediately preceding recording code. Since the recording code is in NRZI notation,
The recording code 1 reverses the polarity of the recording signal, and the recording code 0 maintains the polarity of the recording signal. For example, if the information data is 010010. . . Is obtained as follows. First, it is assumed that the bit immediately before the recording code in the initial state is set to 0. Therefore, the first two bits of information are 01, and the next two bits of information are 0.
0, the rule table No. 7, the recording code is 001. Since the next two bits of the information are 00, the next two bits are 10, and the immediately preceding recording code bit is 1, the rule table No. 10 and the recording code is 01
0. That is, the recording code is 001010. . . Becomes The corresponding recording signals are +1, +1, -1,-
1, +1, +1, or -1,-with initial polarity reversed
1, +1, +1, -1, and -1. However, the total number of +1 of the recording signals is an even number in both recording signals. In general, if the total number of information bits in a given block is even, the even parity for the total number of +1 is not related to the initial polarity of the recording signal.

FIG. 4 shows a recording encoding method in the embodiment. Since the information bit (B) is encoded by (1, 7) according to the rule table shown in Table 1, every two bits, b
1, b2 and b3, b4. Here, it is assumed that 500 bits of information bits are a predetermined block length. After the predetermined block, two bits for a parity bit for setting the total number of +1 in the recording signal to an even number are set. In the first predetermined block, they are p1 and p1, and in the second predetermined block, the information bits are b501 to b100.
Two bits p2 and p2 are prepared for 500 bits up to 0. In the recording encoding, as described above, the recording code 3 bits are determined by the immediately preceding bit of the recording code, the information 2 bits, and the next information 2 bits. c1, c2, and c3 correspond to b1 and b2. Recording signals r1, r2, and r3 are formed from the recording code (C). The following procedure is used for the last two bits of the predetermined block. The number of +1 in the recording code (R) is counted by the flip-flop (5 in FIG. 3), and it is determined whether the total number until recording and encoding the last 2 bits of information is even or odd. If it is an even number, recording coding is performed by assuming p1 bits so that the number of +1 of the recording signal for the last two-bit recording code is an even number. In the case of an odd number, p is set so that the number of +1 of the recording signal for the last two-bit recording code is an odd number.
Assuming one bit, recording encoding is performed. That is, in any case, the total number of +1 in the predetermined block of the recording signal is made even. For example, b499, b500 is 00,
When the immediately preceding recording code c747 is 0, No. The rule is 5 or 6. Further, if the total number of the last two bits of information before recording and encoding is an odd number and +1 is immediately before the recording signal, p1 = 0 is assumed. 6, the recording codes c748, c749, and c750 are 000, and the recording signals r748, r749, and r750 are +1.
+1 and +1. In the predetermined block, the total number of +1 is even-numbered. Similarly, in the second block, p
Using two bits, the total number of +1 in the recording signal is made even in the entire second block.

Next, a 1-bit correctable improved M2D
The FE will be described. FIG. 5 shows an improved M2D in the embodiment.
FIG. 3 is a detailed signal system diagram of the FE circuit 9; Those having the same functions as those in FIG. 1 of the conventional example are indicated by the same numbers. The output signal of the pre-equalization filter (Forward Equalizer) M-1 is input to adders M-2-1 and M-2-2. Each corresponding slicer M-9-1, M-9
Feedback filter (FBF) M-4-
1. A feedback signal is created by M-4-2. In addition,
Slicer M-9-1 is + α, Slicer M-9-2 is -α
Is the same as before. In the embodiment, α = 0.3. Further, in the second identification of the erasure zone, + α1 = + α / 2 and −
With an offset of α1 = −α / 2, both slicers are set to α = 0 from the identification of the third bit. Since the pre-equalization filter M-1 is a low-pass filter, the noise superimposed on the signal is also affected by this filter characteristic, and when noise large enough to enter the erasure zone is added at the beginning of the zone, it becomes second. Also, since there is a high possibility that noise of the same polarity is superimposed, the offset is also given as described above at the time of the second identification to prevent an identification error.

Further, when the absolute value of the slicer input becomes equal to or less than α, (1, 1,
7) If the discrimination result that does not satisfy the rule of the recording code is one sequence, the other sequence is satisfied, so the discrimination result of the satisfied sequence is adopted and is not set as the erasure zone. An erasure zone is a case where the identification results are different and both satisfy the (1, 7) rule. The identification result of each slicer is delayed by a predetermined bit by buffers M-5-1 and M-5-2, and one of the identification results is selected by selector M-8. The arithmetic circuits M-10-1 and M-10-2 determine two CSE values in the erasure zone, compare them by the comparator M-7, and, based on the comparison result, determine the smaller series by the selector M-8. select. The final result output circuit M-11 counts the total number of +1 in the identification result for each predetermined block because the total number of +1 in the recording signal is set to an even number for each predetermined block, and checks whether the number is even. . If it is an even number, it is determined that there is no error, and the output of the selector M-8 is set as the final output F-out. If an odd number is detected, it is determined whether the condition is correctable. If the condition is satisfied, the condition is corrected and the final result is obtained. FIG. 6 shows a detailed signal system diagram of the final result output circuit M-11 relating to this operation.

The selector output S-out is the switch circuit 1
The data is alternately input to the shift registers 11-10 and 11-11 having the number of bits equal to the number of bits of the predetermined block for each predetermined block via 1-9. The selector output S-out is input to the flip-flop 11-6. Since the reproduction bit clock (clock) is input to the clock input of the flip-flop 11-6, when the output of the flip-flop 11-6 is captured by the latch circuit 11-7 for each predetermined block, the latch circuit 1
1-7 indicates whether the total number of +1 in the selector output S-out is an even number or an odd number for each predetermined block. That is, if the number is even, the output is low, and if the number is odd, the output is high. When the output of the latch 11-7 is Low, it can be determined that there is no error in the identification signal in the block. The output of the latch 11-7 is connected to the gate circuit 11-
8 is controlled. When the output of the latch 11-7 is Low, the gate 11-8 is closed, and the switch circuit 11- is closed.
14 always outputs the output of the shift register 11-10 or 11-11 directly as the final identification result F-out via the switch circuit 11-12.

On the other hand, when the output of the latch 11-7 is High, it means that the identification signal in the block has an error. Therefore, the switch circuit 11-14 switches the signal read from the shift register at the error location. Select the inverted signal. The selection signal for this is provided from the output of the down counter 11-5 via the gate circuit 11-8.
The down counter 11-5 is an Exclus with a gate.
live OR (abbreviated as G-EX-OR) 11-1, 2
Bit counter 11-2, Philip flop 11-2
-1, 8-bit counter 11-4, gate circuit 11-3
Is controlled by an error detecting means. First, the 2-bit counter 11-2, the flip-flop 11-2-1, and the 8-bit counter 11-4 are reset every predetermined block. On the other hand, the comparator M-7 compares the CSE values, and outputs an S-com signal when the difference is equal to or less than a predetermined value. Only when this signal is output, the buffer outputs out1 and out2 of the erasure zone become E
The G-EX-OR circuit 11-1 receives the X-OR processing.
EX-OR processing is Lo when two inputs match.
When the output does not match, the output becomes High.
The number of High outputs is counted by the 2-bit counter 11-2. The 8-bit counter 11-4 has a gate circuit 1
The reproduction bit clock is counted via 1-3. 2
The inverted output of the lower bit output S0 of the bit counter 11-2 controls the gate circuit 11-3. The upper bit output S1 is input to the set terminal of the flip-flop 11-2-1. The output of the flip-flop 11-2-1 is connected to the reset terminal of the 8-bit counter 11-4. Now, when the S-com output is output and the two outputs out1 and out2 are different by one bit, when the inverted output of the lower bit output S0 of the 2-bit counter 11-2 becomes Low, the gate circuit 11-3 turns on. Since it is closed, the position of the 1-bit error remains in the 8-bit counter 11-4. However, when the two outputs out1 and out2 are different from each other by two or more bits, the upper bit S1 of the 2-bit counter 11-2 becomes High, and the flip-flop 11-2-1 is set. When the flip-flop 11-2-1 outputs High, the 8-bit counter 11-4 is reset. For each predetermined block, the contents of the 8-bit counter are the down counter 11-5.
When the value of the down counter becomes zero, the down counter 11-5 outputs a High signal. Since this output corresponds to the error position of the block, the switching circuit 11
Numeral -14 selects the inverted output 11-13 of the shift register output and corrects the error. The circuit operation of the final result output circuit M-11 that performs one-bit error correction has been described above.

In the embodiment, whether the signal processing is performed by analog processing or digital processing is not particularly described. An A / D converter for converting an analog signal into a digital signal can be provided before the pre-filter, and all processing can be performed digitally. A / D conversion can be performed at the output of the pre-filter. It is possible. The latter is more practical because it is more likely that the chip area can be reduced.

Next, another embodiment using the gist of the present invention will be briefly described. To set the total number of recording signals + 1,
As shown in FIG. 7, two interleaved sequences Pe
It is also possible to set even and odd numbers for Po and Po, respectively. At this time, if errors occur in separate streams, a 2-bit error can be corrected.

A 1-bit error correction code has been proposed. However, the redundancy is 1% to 5%, which is larger than that of the present invention. Further, the calculation for detecting the error location is complicated. This is because it must be checked for possible occurrences everywhere in a given block. On the other hand, the present invention finds an erasure zone in which an error is likely to occur, and furthermore, by comparing the two identification results of the erasure zone, it is possible to easily identify a place where there is a possibility of an error. In the above embodiment, the information block is 500 bits in the predetermined block, and two parity bits are inserted into the information block. That is, since the redundancy is as small as 0.4%, the present invention hardly sacrifices the recording format efficiency of the recording medium. At this time, a simulation confirms an improvement of 0.5 dB in terms of the signal-to-noise ratio of the head output signal.

In order to check whether the present invention is used in a digital signal recording device or a read channel LSI, the following can be easily performed.
Since the output terminal of the recording signal for recording on the recording medium is provided in the LSI, the output signal is monitored and the relation with the input information data is examined in detail. You can see if it has been adopted.

[0033]

According to the present invention, signal processing suitable for a magnetic disk drive having a high linear recording density and a high track density is provided. In addition, the circuit configuration is simpler than the maximum likelihood decoding signal processing employed in the PRML system, and a read channel LSI with good cost performance and a magnetic disk device can be provided.

[Brief description of the drawings]

FIG. 1 is a signal system diagram of a conventional M2DFE.

FIG. 2 is a typical error waveform diagram generated in an erasure zone.

FIG. 3 is a signal system diagram of the entire recording / reproducing system according to the embodiment of the present invention.

FIG. 4 is a diagram showing a relationship among information data, a recording code, and a recording signal in the embodiment.

FIG. 5 is a detailed signal system diagram of an equalization and identification circuit in the embodiment.

FIG. 6 is a signal system diagram of a circuit for performing error correction in the embodiment.

FIG. 7 is an explanatory diagram regarding setting of a recording signal in another embodiment.

[Explanation of symbols]

1 ··· Interface circuit, 2 ··· Check code insertion circuit, 3 ··· Randomization circuit, 4 ··· (1-7) coding circuit, 5 ··· Philip flop, 6 ··· Recording amplifier circuit,
7 ··· Mechanical system consisting of magnetic head and recording medium
A reproduction amplifier circuit, 9 an improved M2DFE circuit of the present invention, 10 a decoding circuit for performing (1, 7) decoding, 11
An inverse randomizing circuit for restoring the randomization processed on the recording side, and an error correction circuit for performing error correction on the remaining code errors.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tatsuharu Matsuura 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Division, Hitachi, Ltd. 5D031 DD01 EE01 FF03 5D044 BC01 CC04 FG01 GL50

Claims (6)

[Claims] 1. A semiconductor device for signal processing for recording and reproducing a digital signal, comprising: means for converting at least the digital signal into a recording code of d = 1;
When expressed by 1, -1 as signal processing on the recording side,
Means for presetting the total number of +1 to an even or odd number within a predetermined block;
Two decision feedback equalizers, means for comparing the provisional identification results of the two decision feedback equalizers, and whether or not the total number of +1 of the preset recording signal in the predetermined block is even or odd. Means for correcting the one bit by referring to the semiconductor device. 2. The comparison means for comparing CSE values of two identification result sequences in an erasure zone, and when the difference is small, a different place in the two identification result sequences is 1 bit in a predetermined block. 2. The semiconductor device according to claim 1, further comprising means for detecting the fact and means for storing the location of the one bit. 3. The semiconductor device according to claim 1, wherein the recording code of d = 1 is a (1, 7) recording code. 4. An apparatus for recording / reproducing a digital signal, wherein at least means for converting the digital signal into a recording code of d = 1, and when the recording signal is represented by +1, -1 as signal processing on the recording side. , +1 in a predetermined block, a means for presetting the total number to an even number or an odd number, a signal processing on the reproduction side, two decision feedback equalizers, and a comparison between the provisional identification results of the two decision feedback equalizers. A digital signal recording / reproducing apparatus, comprising: means for correcting the one bit by referring to whether the total number of +1 of the preset recording signal in the predetermined block is even or odd. . 5. The comparing means for signal processing on the reproducing side includes means for comparing CSE values of two identification result sequences in an erasure zone, and a difference location between two identification result sequences in a predetermined block when the difference is small. Within 1
5. The digital signal recording / reproducing apparatus according to claim 4, further comprising signal processing comprising means for detecting the bit and means for storing the location of the one bit. 6. The digital signal recording / reproducing apparatus according to claim 4, wherein the recording code of d = 1 is a (1, 7) recording code.