JP2000151570A - Ip terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the IP terminal to discard excess data or insert deficient data on the occurrence of surplus or deficiency of data resulting from an error in a clock speed. SOLUTION: Relating to a synchronizing function of a transmission clock an IP terminal functioning as a master set transmits a synchronizing timing packet at a prescribed interval, and an IP terminal functioning as a slave set decides a count of a clock counter when receiving the first synchronizing timing packet as an expected value after starting the communicating with the IP terminal 2 of the master set, discriminates a synchronization state with respect to the transmission clock used by the IP terminal 2 of the master set of the transmission clock generated by a clock generating means through the comparison result between the expected value and the count of the clock counter at the reception of the synchronizing timing packet and applies phase shift control to the clock generating means, based on the discrimination result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Protocol network (hereinafter "IP network")
That. The present invention relates to a terminal device (hereinafter, referred to as “IP terminal device”) for transmitting packetized voice data and other information in real time.

[0002]

2. Description of the Related Art At present, an operation of a real-time transmission service of voice data via an IP network, that is, an Internet telephone service has been started. Various connection forms are conceivable for the connection form of this service, such as communication between personal computers connected to an IP network and communication between telephone sets via an IP network.

However, in an IP terminal device used for such communication, an error occurs in a transmission clock speed between a transmitting side and a receiving side due to the accuracy of a crystal oscillator and other components mounted on each device. May occur.

However, in the conventional device, such an error is not taken into consideration, and when data error or lack actually occurs due to an error in clock speed, the receiving-side IP terminal device is excessively affected. The corresponding audio data is discarded or substitute data corresponding to the shortage is inserted.

[0005]

However, when such processing is executed, the identity of the contents between the original data and the discarded or inserted data (the waveform that is actually reproduced as audio) is identical. However, there is a possibility that the voice quality is degraded.

Further, if the data after such processing is demodulated by a modem, it may be demodulated into an analog waveform completely different from an original waveform, and communication via a modem cannot be realized.

[0007]

Means for Solving the Problems In order to solve such problems, the present invention comprises the following means. (A) In a first aspect, the present invention relates to a function of synchronizing a transmission clock, wherein an IP terminal functioning as a master device for another IP terminal device is provided with at least a communication period for another IP terminal device to be communicated. And a transmission unit for transmitting a synchronization timing packet for determining a synchronization state at regular intervals. (B) The second invention relates to a transmission clock synchronizing function, in which an IP terminal device that functions as a master device for all other IP terminal devices belonging to the same broadcast domain, and to all other IP terminal devices. On the other hand, a transmission means for constantly broadcasting a synchronization timing packet for determining a synchronization state at regular intervals is provided. (C) In a third aspect of the present invention, with regard to a function of synchronizing a transmission clock, an IP terminal device functioning as a slave device to the IP terminal device according to claim 1 or 2 is provided with the following means.

That is, (1) a clock generation means for generating a transmission clock, and (2) a cyclic cycle whose cyclic cycle is determined to be the same as the transmission cycle of the synchronization timing packet output from the IP terminal device on the master device side. (3) After starting communication with the IP terminal device on the master device side, the count value of the clock counter at the time of receiving the synchronization timing packet received first is determined as an expected value, and the expected value From the comparison result with the count value of the clock counter at the time of receiving the subsequently received synchronization timing packet, determine the synchronization state of the transmission clock generated by the clock generation means with respect to the transmission clock used in the IP terminal device on the master device side, Control means for controlling the phase shift of the clock generation means based on the determination result.

For example, regarding a synchronization function of a transmission clock,
When the transmission clock of the IP terminal device functioning as the slave device and the transmission clock of the IP terminal device functioning as the master device are synchronized, the count value that the cyclic clock counter takes when receiving the synchronous timing packet is always the same value. , Matches the expected value.

On the other hand, if the transmission clock of the IP terminal device functioning as the slave device is faster than the transmission clock of the IP terminal device functioning as the master device, the counter taken by the clock counter at the time of receiving the synchronization timing packet. The value shifts in a direction larger than the expected value.

When the transmission clock of the IP terminal device functioning as a slave device is slower than the transmission clock of the IP terminal device functioning as a master device,
The counter value taken by the clock counter at the time of receiving the synchronization timing packet shifts in a direction smaller than the expected value.

Using such a phenomenon, the control means performs control so that the phase of the transmission clock generated by the clock generation means is synchronized with the phase of the transmission clock of the IP terminal device functioning as the master device.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment (A-1) System Configuration FIG. 1 shows a basic configuration of a network system according to a first embodiment. FIG. 1 illustrates a system configuration in a case where a difference in transmission clock speed is adjusted between two IP terminal devices 2 and 3 connected via an IP network 1.

FIG. 1 relates to a transmission clock synchronizing function.
The figure shows a state in which a synchronous master module 4 functioning as a master is mounted on the IP terminal device 2 and a synchronous slave module 5 functioning as a slave is mounted on the IP terminal device 3. Here, the relationship between the IP terminal device operating as a master and the IP terminal device operating as a slave is fixed.

Of course, both the synchronization master module 4 and the synchronization slave module 5 can be mounted on both of the IP terminal devices 2 and 3, but the configuration shown in FIG. 1 will be described here.

When both the synchronous master module 4 and the synchronous slave module 5 are mounted on each IP terminal device, which operates as a master and which operates as a slave depends on the rules. For example, the calling side may operate as a master and the called side may operate as a slave, or the calling side may operate as a slave and the called side may operate as a master.
Other arrangements are possible. (A-2) Configuration of Each Unit Subsequently, the internal configuration of each module will be described.

FIG. 2 shows a functional block configuration of the synchronization master module 4. The synchronization master module 4 includes a clock generator 4A, an interrupt generator 4B, a controller 4C
And an IP unit 4D.

The clock generator 4A is a reference clock generating means composed of a crystal oscillator or the like. The interrupt generator 4B counts the reference clock generated by the clock generator 4A, and generates an interrupt signal once per fixed number. This interrupt signal is transmitted to the I
Regardless of the operation state of the P terminal device 3, it is always generated at regular intervals T1.

The controller 4C outputs synchronization control data each time it receives an interrupt signal. IP unit 4
D is a means for terminating the IP network, packetizes synchronization control data input at regular intervals T1, and outputs it as a synchronization timing packet. The IP unit 4D is also used for transmitting and receiving other data packets.

FIG. 3 shows a functional block configuration of the synchronous slave module 5. The synchronous slave module 5 has I
It comprises a P unit 5A, a controller 5B, a clock counter 5C, and a transmission clock generator 5D.

The IP unit 5A is a means for terminating the IP network similarly to the IP unit 4D on the master side. When the synchronization timing packet is received, the IP unit 5A outputs this to the controller 5B as synchronization control data.

The controller 5B reads the count value X1 of the clock counter 5C and compares it with the expected value X0 every time reception of the synchronization control data is confirmed, and determines the clock speed of the transmission clock generator 5D according to the comparison result. Control.

For example, when X1−X0 <0 (when the current count value X1 is smaller than the expected value X0), the controller 5B controls to increase the generated clock speed,
When X1−X0 <0 (the current count value X1 is equal to the expected value X0
(When smaller), control to reduce the generated clock speed.

However, in practice, the above-described control is performed only when the absolute value of the difference between the count value X1 and the expected value X0 exceeds a predetermined threshold value Y in consideration of the adjustable minimum width and the like. I do.

In determining the magnitude relationship between the count values,
A predetermined correction function is used, and the details of this function will be described later.

As the expected value X0, the count value X1 at the time when the synchronization timing packet is first received after connection to the IP network 1 is used. This is from the paired synchronization master module 4
Since the synchronization timing packet is transmitted at regular intervals T1, fluctuations in the IP network 1 can be ignored (a constant delay is allowed).
Synchronous master module 4 and synchronous slave module 5
If the error of the transmission clock generated within can be ignored,
This is because the count value read by the controller 5B should always be the same value as the first count value (because the clock counter 5C performs a cyclic count operation).

This value is retained while the synchronous slave module 5 is operating or connected to the IP network 1. This is because it is only necessary to ensure that the transmission clock speeds match for a series of communication operations.

The clock counter 5C is a counter that cyclically counts the reference clock generated by the transmission clock generator 5D. Here, the clock counter 5C
This is a cyclic counter in which the count value is set so as to make one cycle at the same constant interval T2 as the coincidence interval T1 at which the master outputs the interrupt signal. For this reason, the clock counter 5C is configured to repeat the operation of counting up from 0 to a certain count value so that its circulation cycle matches the fixed time T2.

The transmission clock generator 5D is a reference clock generation means composed of a crystal oscillator or the like, like the transmission clock generator 4A on the master side. The design value of the clock speed is the same as that of the transmission clock generator 4A on the master side. (A-3) Adjustment Operation Next, how the transmission clock speed is adjusted between the IP terminal devices equipped with the modules configured as described above, including the principle thereof, will be described.

First, regarding the transmission clock synchronizing function, a synchronization timing packet is always transmitted from the IP terminal device 2 on the master side at regular intervals T1 regardless of the operation state of the IP terminal device 3 on the slave side. Is done. However, if the synchronization timing packet is set to be transmitted during communication with the slave side, the purpose can be achieved.

The fixed interval T1 here is an interval determined based on the clock speed output from the clock generator 4A of the synchronization master module 4 mounted on the IP terminal device 2.

On the other hand, regarding the synchronization function of the transmission clock, the IP terminal device 3 on the slave side always monitors the arrival of the synchronization timing packet by the controller 5B of the synchronization slave module 5, and confirms the arrival of the synchronization timing packet. At this time, the count value of the clock counter 5C at that time is read and the following processing is performed.

First, when the confirmed arrival of the synchronization timing packet is the first one after the synchronization slave module 5 is activated and the IP terminal device 3 is connected to the IP network 1, the controller 5B The count value read from clock counter 5C is calculated as expected value X
An operation of holding the value as 0 until the end of the communication is performed. This value is held in a register or the like.

On the other hand, if the confirmed arrival of the synchronization timing packet is for the second or later arrival, the controller 5B checks the arrival of the synchronization timing packet (specifically, the synchronization control packet). Each time data input is confirmed), the count value X1 of the clock counter 5C at that time is read, and a comparison is made with the expected value X0 previously obtained.

Here, as described above, the count value X1 and the expected value X0 should always match if the transmission clock speed on the master side and the transmission clock speed on the slave side match.

However, as described as a problem of the prior art, since the actual circuit has a phase shift due to the accuracy error of the crystal oscillator and the like, the count value X 1
Even if the transmission fluctuation on the network 1 can be neglected, a deviation from the expected value X0 occurs in a certain direction.

For example, when the transmission clock speed on the slave side is faster than the transmission speed on the master side, the count value X1
Is shifted in a direction larger than the expected value X0, and when the transmission clock speed on the slave side is lower than the transmission speed on the master side, the count value X1 is shifted in a direction smaller than the expected value X0.

Therefore, the controller 5B on the slave side
Detects a shift direction of the count value X1 detected each time a synchronization timing packet is received or a shift direction of the count value X1 detected from the average thereof, and sets the shift amount to a predetermined threshold Y. If it exceeds, control is performed according to the deviation direction. That is, the shift direction is positive (X1> X
In the case of (0), control is performed to decrease the clock speed, and when the shift direction is negative (X1 <X0>), control is performed to increase the clock speed.

However, in order to realize the detection of the deviation direction, specifically, the controller 5B needs a correction function as described below. This is the expected value X0
Is almost at the center of the count value that can be taken by the clock counter 5C, the correction function is almost unnecessary. What is needed is that in many cases the expected value X0 is
This is a case where the count value is set near the upper limit or the lower limit of the count value that can be taken by the clock counter 5C.

The basic concept of this correction function will be described with reference to FIG. In FIG. 4, the maximum value of the count value that can be taken by the clock counter 5C is represented as 99, that is, the count value of the clock counter 5C makes one rotation in 100 count cycles. Here, FIG. 4A shows a correction process when the initial operation value exceeds the negative side, and FIG. 4B shows a correction process when the initial operation value exceeds the positive side. ing. In FIG. 4A,
FIG. 4B shows a case where the expected value X0 is set to 95 of the count value, and FIG. 4B shows a case where the expected value X0 is set to 2 of the count value.

In the case of FIG. 4A, it is assumed that the expected value X0 is simply subtracted from the current count value X1 and the deviation direction is determined from the value (that is, the determination is made without any correction). If the transmission clock speed on the slave side is high and the current count value advances by 5 clocks or more, the value of the subtraction value (= X1-X0) becomes negative.

For example, when the clock advances by 5 clocks, the clock counter 5C returns to 0, so that the current count value X
The value obtained by subtracting the expected value X0 from 1 is -95. This causes the controller 5B to erroneously determine that the transmission clock speed on the slave side is low.

Therefore, in the controller 5B of this embodiment, the range in which the subtraction value can be taken is substantially the same for each of the positive side and the negative side (+50 for the positive side and -4 for the negative side).
9) (of course, this range is merely an example, and for example, 60,
The negative side may be set to −40. If the value exceeds the range, a correction process is executed, and the deviation direction is determined based on the corrected value.

For example, as in the above-described example, when the initial operation value is -95 (that is, when the range in which the subtraction value can be taken exceeds the negative side), the controller 5B sets the state shown in FIG.
As shown in (2), a correction process of adding 100 to the initial operation value is performed, and a shift direction and a shift amount are detected for the value after the correction process. In this case, the value after the correction processing is +5, and both the shift direction and the shift amount match the original values.

On the other hand, when the initial operation value is 97 (that is, when the range over which the subtraction value can be taken exceeds the positive side), the controller 5B subtracts 100 from the initial operation value as shown in FIG. A subtraction process is performed, and the direction and the amount of the shift are detected for the value after the correction process. in this case,
The value after the correction processing is -3, which indicates that the current count value is delayed by three clocks because the transmission clock speed on the slave side is slow.

In the controller 5B, such correction processing is executed as needed. As a result, the controller 5
B can accurately control the clock speed of the transmission clock generator 5D, and can keep the transmission clock speed on the slave side during communication within a certain range with respect to the transmission clock speed on the master side. it can.

As a result, it is possible to effectively avoid discarding or inserting data. (A-4) Effects As described above, according to the first embodiment, the transmission clock generated by the synchronous slave module 5 can always be synchronized with the transmission clock generated by the synchronous master module 4. .

Thus, the IP terminal device (with a communication function) 2 using the transmission clock of the synchronization master module 4
And communication with the IP terminal device (with a call function) 3 using the transmission clock of the synchronous slave module 5, communication is performed for a long time (no time limit) without discarding data or inserting alternative data. Since the communication can be performed, modem communication becomes possible, and a call having the same quality as that of circuit switching can be made. (B) Second Embodiment (B-1) System Form FIG. 5 shows a basic form of a network system according to a second embodiment. FIG. 5 shows a system configuration in which a difference in transmission clock speed is adjusted between one IP terminal device 2 and a plurality of IP terminal devices 3 connected via an IP network 1 constituting a broadcast domain. Things. However, in FIG. 5, parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

The difference between the second embodiment and the first embodiment is that the first embodiment specifies the slave IP terminal device 3 to be the destination and transmits a synchronization timing packet. The second embodiment is different from the first embodiment in that the synchronization timing packet is broadcast as a broadcast packet to all IP terminal devices existing in the domain.

That is, in the case of this embodiment, the IP terminal device 2 equipped with the synchronization master module 4 broadcasts a synchronization timing packet to all the IP terminal devices 3 equipped with the synchronization slave module 5 at regular intervals T1. Is different.

The operation of establishing synchronization in each IP terminal device 3 equipped with the synchronous slave module 5 is the same as the operation described in the first embodiment.
Each of the P terminal devices performs an operation of synchronizing the transmission clock speed of the P terminal device with the transmission clock speed of the master device. (B-2) Effects Thus, according to the second embodiment, the following effects can be obtained. That is, all the synchronous slave modules 5 located in the same broadcast domain are
In any case, synchronization with the synchronization master module 4 located in the same broadcast domain is ensured. Therefore, the synchronization of the transmission clocks between the synchronous slave modules 5 is ensured on the premise of the synchronization with the synchronous master module 4.

Therefore, even in the communication between the IP terminal devices 3 equipped with the synchronous slave module 5, it is not necessary to discard data or insert alternative data at all, and the communication can be performed for a long time (no time limit). It becomes possible.
That is, modem communication is possible between all IP terminal devices (including not only the one equipped with the synchronous slave module 5 but also the one equipped with the synchronous master module 4) located in the same broadcast domain, and the line switching is performed. It is possible to make a call of the same quality as.

Further, the transmission clock speed between all the IP terminal devices (including not only the one equipped with the synchronous slave module 5 but also the one equipped with the synchronous master module 4) located in the same broadcast domain as described above. Therefore, simultaneous communication of a plurality of channels can be realized only by mounting one synchronization master module or synchronization slave module (that is, without mounting each module for each channel). (C) Other Embodiments In the above-described embodiment, the description has been made on the premise that audio data with high real-time properties is transmitted, but the information to be transmitted is not limited to this, and so-called videophone and The present invention can also be applied to the case of transmitting other information that requires real-time properties, such as broadcast video data.

[0054]

As described above, in the present invention, the transmission clock generated in the IP terminal functioning as the slave device is always synchronized with the transmission clock generated in the IP terminal device functioning as the master device. Therefore, communication can be performed for a long time without discarding data or inserting alternative data.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to a first embodiment.

FIG. 2 is a diagram showing a functional block configuration of a synchronization master module.

FIG. 3 is a diagram showing a functional block configuration of a synchronous slave module.

FIG. 4 is a diagram provided for conceptual explanation of a correction function mounted on a controller in a synchronous slave module.

FIG. 5 is a diagram illustrating a system configuration according to a second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... IP network, 2, 3 ... IP terminal device, 4 ... Synchronization master module, 5 ... Synchronization slave module, 4
A: Clock generator, 4B: Interrupt generator, 4C, 5
B: Controller, 4D, 5A: IP unit, 5C ...
Clock counter, 5D: Transmission clock generator.

Claims (3)

[Claims] 1. A transmission clock synchronizing function, comprising:
An IP terminal device functioning as a master device for a P terminal device, and transmitting a synchronization timing packet for determining a synchronization state at regular intervals to another IP terminal device to be communicated at least during the communication period. An IP terminal device comprising means. 2. An IP terminal device which functions as a master device for all other IP terminal devices belonging to the same broadcast domain with respect to a transmission clock synchronizing function. An IP terminal device comprising: a transmission unit that broadcasts a synchronization timing packet for determining a synchronization state at regular intervals. 3. An IP terminal device which functions as a slave device to the IP terminal device according to claim 1 or 2, wherein the clock generation means for generating a transmission clock and the cyclic period thereof are related to a transmission clock synchronization function. A cyclic clock counter defined in the same cycle as the transmission cycle of the synchronization timing packet output from the IP terminal device on the master device side, and the synchronization signal received first after communication with the IP terminal device on the master device starts. The count value of the clock counter at the time of receiving the timing packet is set as an expected value, and the clock generation means generates the count value based on a comparison result between the expected value and the count value of the clock counter at the time of receiving the subsequently received synchronous timing packet. Of the transmitted clock to the transmission clock used in the IP terminal device on the master device side An IP terminal device comprising: a control unit that determines a synchronization state of the clock generation unit based on the determination result, and controls phase shift of the clock generation unit based on the determination result.