JP2000148998A - Data processor and parallel processors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve relief efficiency when a failure occurs by providing more storage devices than the number of data of plural pieces of data and switching a data input-output line connected to the input-output terminal of a storage device that fails to the input-output terminal of another storage device when the failure takes place in one storage device. SOLUTION: This data processor 10 consists of (n+1) pieces of memories 101-1 to 101-n+1, n pieces of ALUs(arithmetic logic unit) 102-1 to 102-n, n pieces of switching signal generation circuits 103-1 to 103-n and n pieces of switching circuits 104-1 to 104-n. The data input-output terminal T1 of the memory 101-1 is also connected to the input-output terminal L of the switching circuit 104-1. The input-output terminals T3 to Tn of the memories 101-3 to 101-n are connected to the input-output terminals H of the switching circuits 104-2 to 104-n-1 on the preceding stages and also are connected to the input-output terminals L of the switching circuits 104-3 to 104-n on corresponding stages. When a failure occurs, the input-output lines of the ALUs 102-1 to 102-n are switched and connected to the input-output lines of the next stages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor and a parallel processor for inputting and outputting a plurality of data selected by a column selection line based on a column address and a row selection line based on a row address.

[0002]

2. Description of the Related Art Conventionally, in the field of signal processing for image data, the same arithmetic processing is often performed on all pixels constituting one image. In order to execute similar arithmetic processing on many data at high speed, SIMD
A (Single Instruction Multiple Data stream) type architecture has been proposed and is used not only in image signal processing but also in a wide range of fields.

[0003] The SIMD type architecture has a configuration in which a necessary number of arithmetic units are arranged, and each arithmetic unit operates according to the same instruction. Therefore, if different data is given to each arithmetic unit, an arithmetic result for each data can be obtained at once.

As an application of the SIMD type processing apparatus to image processing, for example, SVP (SERIAL VIDEO PROCESSOR / Proceed)
edings of the IEEE 1990 CUSTOM INTEGRATED CIRCUITS
The device shown in CONFERENCE / P17 3.1 to 4) is known.

[0005] This device is specifically composed of a parallel processor 1 as shown in FIG. 14 for example. The parallel processor 1 includes pixel data for one scanning line, a data input register (DIR) 2 for sequentially inputting serial data SIN, a storage device (memory), and an arithmetic unit (ALU). A plurality of processor elements (hereinafter, referred to as “processor elements”) for processing pixel data for scanning lines in parallel.
And a data output register (DOR) for sequentially outputting processed pixel data for one scanning line to a serial data output SOUT. 4.

A procedure for processing image data composed of m × n pixels of p (1, 1) to p (m, n) by the parallel processor 1 as shown in FIG. FIG.
This will be described below with reference to FIG. It should be noted that a pixel p of an arbitrary i, j (1 ≦ i ≦ m, 1 ≦ j ≦ n)
(I, j) may be represented by a plurality of bits. Since scanning of an image is usually performed in order from left to right and from top to bottom, image data is generally transmitted in a structure as shown in FIG. Here, the time for scanning one line of pixel data is called a horizontal period. The time required for scanning to return from the right end to the left end of the screen is called a blanking period. For example, a blanking period exists between the pixel data of the rightmost pixel p (i, n) on the i-th line and the pixel data of the leftmost pixel p (i + 1,1) on the next line.

In FIG. 17, a video signal in which each pixel is composed of a plurality of bits is sequentially input to an input terminal in pixel units. During the first one horizontal period, the pixel data of the first line is stored in the data input register 2 having the capacity of one line. The data of each pixel on the first line of the video signal stored in the data input register 2 is
The data is output in parallel during the subsequent blanking period and the data of one pixel per PE is the number (n) of one line.
It is supplied in parallel to the arranged PE3-1 to PE3-n.

In the next one horizontal period, each of the PEs 3-1 to 3-n
In, the arithmetic processing is performed on the supplied pixel data of the first line. In parallel with this, the pixel data of the second line is sequentially input to the data input register 2.
From each PE3-1 to 3-n within the following blanking period,
The processed pixel data of the first line is supplied to the data output register 4 in parallel. In parallel with this, pixel data of the second line is supplied from the data input register 2 to the PE group 3 in parallel. In the next one horizontal period, the pixel data of the first line stored in the data output register 4 is sequentially output to the output terminal. In parallel with this, each PE3
In the case of -1 to 3-n, the arithmetic processing of the pixel data of the second line is performed, and the pixel data of the third line is sequentially input to the data input register 2.

[0009] Thereafter, when each of the PEs 3-1 to 3-n is processing pixel data of the i-th line, the data input register 2 inputs the pixel data of the (i + 1) -th line,
The data output register 4 repeatedly outputs the pixel data of the (i-1) th line. As the data input register 2, the PEs 3-1 to 3-n, and the data output register 4 operate in synchronization as described above, a video signal that has been subjected to arithmetic processing for each horizontal period is extracted. In this way, for example, digital processing of a video signal is performed.

Next, the PE which is a main part of the parallel processor 1 will be described in detail.

FIG. 18 is a diagram showing a schematic configuration of one PE. As shown in FIG. 18, the PE is a storage device 31,
An arithmetic unit (ALU) 32 and a selection circuit 33 are provided. The storage device 31 includes memory cells (not shown) connected to the bit lines BL and the word lines WL arranged in a matrix.

The memory cell selected by the word line WL is
The one selected by the column selection line CSL is the arithmetic unit 32
Connected to Normally, the bit line BL and the word line W
Although there are a plurality of L and column selection lines CSL, they are omitted in this figure for simplicity.

The storage device 31 has a capacity enough to store data necessary for a normal image processing application. Then, the data transferred from the data input register 2 during the blanking period is stored in the storage device 31. At this time, the storage device 31 is input with the same address as the storage device of the other PEs, and stores data based on this.

The arithmetic unit 32 loads data from the storage device 31 to perform an operation, and stores the result in the storage device 31. When the arithmetic unit 32 loads data, the storage device 31 outputs data to the bit line BL from the storage device indicated by the same row address and outputs the data to the bit line BL according to the same column address. One is selected and output to the arithmetic unit 32. The arithmetic unit 3
When 2 stores data, the storage device 31 connects the bit line BL selected from the same column address to the output portion of the arithmetic device 32, and stores the data in the storage device selected by the row address.

This sequence is repeated until the operation required for image processing is completed, and the data is transferred to the data output register 4 in the next blanking period.

This storage device 31 needs, for example, about five lines to perform a filtering process that crosses scanning lines.
If it is composed of a total of 24 bits (red), G (green), and B (blue), a memory capacity of 120 bits is required. Further, if it is assumed that an intermediate operation result is to be held, the storage device 31 needs a capacity of about 256 bits. This is the number of processors x 256 in the parallel processor 1 as a whole.
If 1,000 PEs 3 are mounted, a storage device having a capacity of 256 kbits must be mounted on the parallel processor 1. Since this occupies a very large area and causes an increase in the cost of the LSI, such a storage device portion is usually designed very finely and configured to minimize the area. The storage device 31 is originally finely designed and occupies a large area in the parallel processor 1, so that the probability of occurrence of a failure increases.

For this reason, usually, a redundant storage device is prepared for a storage device, and if a portion of the storage device has a failure, the address accessed by the storage device is replaced with the address of the redundant storage device. The remedy is taken. Next, a case where a column address is generally repaired by a redundant storage device will be described.

FIG. 19 is a diagram showing an example of a configuration in a case where the storage devices 31-1 to 31-n of the respective PEs, which are the main parts of the parallel processor, have a redundant storage device RD.

Referring to FIG. 19, selection circuits 34-1 to 34-34 are provided.
-N selects the columns of the storage devices 31-1 to 31-n and the redundant storage devices RD-1 to RD-n according to the address input from the selection line CSL. If there is a defect in a normal storage device column, a defective column address is programmed in advance, and the selection line CSL is controlled so that the column address selects a redundant storage device column address. . With such a configuration, a non-defective processor can be obtained even when a normal storage device row has a defect.

[0020]

By the way, an LSI having a large number of processor elements and performing collective processing.
In this case, a large amount of data is often read from the storage device at one time, and the number of input / output (I / O) of the storage device tends to increase. The number tends to decrease. For example, if a storage device that can read 1024-bit data by one word line (row selection line) originally has a 32-bit I / O, there are 32 columns of the storage device, and if a redundant row exists, Even if one address is added, the area is increased only by 1/32.

However, if the storage device has 256-bit I / O, there are only four storage device columns. Under such conditions, if one redundant row is added for every four rows, the area increase is 1/4 = 25%, and the number of LSIs manufactured from a silicon wafer is reduced.
The probability of occurrence of a defect in the redundant storage device also increases, and as a result, the number of non-defective LSIs to be obtained is reduced as compared with the case where the redundant storage device is not mounted.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data processing apparatus and a parallel processor which can increase the rescue efficiency when a failure occurs while minimizing the area increase. To provide.

[0023]

To achieve the above object, the present invention provides a data processing apparatus for processing a plurality of data, comprising a data input / output terminal, and a plurality of data input / output terminals. Write and read one of the data, the number of storage devices larger than the number of data of the plurality of data, and if one storage device has a failure, the input / output terminal of the failed storage device And a switching circuit for switching and connecting the data input / output line connected to the storage device to the input / output terminal of another storage device.

Further, according to the present invention, there is provided an information holding means for holding information as to whether or not each storage device is faulty or defective, and the switching circuit determines that the storage device is defective according to the information of the information holding means. The data input / output line connected to the input / output terminal of the designated storage device is switched and connected to the input / output terminal of another storage device.

Further, in the present invention, the switching circuit switches the data input / output line connected to the input / output terminal of the failed storage device to the input / output terminal of the adjacent storage device and connects the data input / output line to the adjacent storage device. The data input / output lines are sequentially switched to the input / output terminals of the adjacent storage devices.

Further, according to the present invention, there is provided an information holding means for holding information as to whether or not each storage device is faulty or defective, and the switching circuit determines that the storage device is defective according to the information of the information holding means. The data input / output line connected to the specified storage device input / output terminal is switched to the input / output terminal of the adjacent storage device, and the subsequent adjacent data input / output lines are sequentially connected to the input / output terminal of the adjacent storage device. Switch and connect to the output terminal.

The present invention is also a data processing device for processing a plurality of data, which has a data input / output terminal,
Write and read one of the plurality of data through the input / output terminal, a storage device with a number greater than the number of data of the plurality of data, provided corresponding to the number of the plurality of data, An arithmetic unit that exchanges data related to arithmetic with one storage device, and, if one storage device has a failure, the data input of the arithmetic device connected to the input / output terminal of the failed storage device. A switching circuit for switching and connecting the output line to an input / output terminal of another storage device.

According to another aspect of the present invention, there is provided a data processing apparatus for processing a plurality of data in parallel, comprising a data input terminal, and writing one of the plurality of data through the input terminal. When the number of storage devices greater than the number of data of the plurality of data and one of the storage devices have a failure, the data input line connected to the input terminal of the failed storage device is replaced by another storage device. And a switching circuit for switching connection to the input terminal of

The present invention also relates to a data processing apparatus for processing a plurality of data in parallel, comprising a data output terminal, and reading out one of the plurality of data via the input terminal. When the number of storage devices greater than the number of data of the plurality of data and one of the storage devices have a failure, the data output line connected to the output terminal of the failed storage device is connected to another storage device. And a switching circuit for switching connection to the output terminal of

According to the present invention, a plurality of first data consisting of serial data is inputted to a data input register of serial input / parallel output, and a parallel output of the data input register is inputted to a plurality of processors comprising a storage device and an arithmetic device. A plurality of second data output in parallel from the processor element as a result of the first element being arithmetically processed by the processor element by supplying the first data to the processor element group including the element in parallel, A parallel processor that inputs data in parallel to a data output register of a parallel input serial output and outputs the second data as serial data from the serial output of the data output register, wherein the storage device in the processor element group includes the processor Are arranged more than the number of elements, When one storage device has a failure, the processor element group connects the data input / output line of the arithmetic device connected to the input / output terminal of the failed storage device to the input / output terminal of another storage device. And a switching circuit for switching connection.

According to the present invention, a plurality of first data consisting of serial data is inputted to a data input register of serial input parallel output, and a parallel output of the data input register is inputted to a plurality of processors comprising a storage device and an arithmetic device. A plurality of second data output in parallel from the processor element as a result of the first element being arithmetically processed by the processor element by supplying the first data to the processor element group including the element in parallel, A parallel processor that inputs data in parallel to a data output register of a parallel input serial output and outputs the second data as serial data from the serial output of the data output register, wherein the storage device in the processor element group includes the processor Are arranged more than the number of elements, In the case where one storage device of the processor element group has a failure, the data output line of the data input register connected to the input terminal of the failed storage device is switched to the input terminal of another storage device. And a switching circuit for switching.

Further, the present invention provides a plurality of processors comprising a storage device and an arithmetic device, wherein a plurality of first data consisting of serial data is inputted to a data input register of serial input parallel output, and the parallel output of the data input register is inputted. A plurality of second data output in parallel from the processor element as a result of the first element being arithmetically processed by the processor element by supplying the first data to the processor element group including the element in parallel, A parallel processor that inputs data in parallel to a data output register of a parallel input serial output and outputs the second data as serial data from the serial output of the data output register, wherein the storage device in the processor element group includes the processor Are arranged more than the number of elements, If there is a failure in one storage device of the processor element group, the data input line of the data output register connected to the output terminal of the failed storage device is switched to the output terminal of another storage device. And a switching circuit for switching.

Further, the present invention provides a plurality of processors comprising a storage device and an arithmetic device, wherein a plurality of first data consisting of serial data are inputted to a data input register of a serial input parallel output, and a parallel output of the data input register is inputted. A plurality of second data output in parallel from the processor element as a result of the first element being arithmetically processed by the processor element by supplying the first data to the processor element group including the element in parallel, A parallel processor that inputs data in parallel to a data output register of a parallel input serial output and outputs the second data as serial data from the serial output of the data output register, wherein the storage device in the processor element group includes the processor Are arranged more than the number of elements, If one storage device in the processor element group has a failure, the data input / output line of the arithmetic unit connected to the input / output terminal of the failed storage device is changed to the input / output terminal of another storage device. A first switching circuit for switching connection to a memory device, and when there is a failure in one storage device of the processor element group, the data output line of the data input register connected to the input terminal of the failed storage device, A second switching circuit for switching connection to an input terminal of another storage device; and, when one storage device of the processor element group has a failure, the data output connected to the output terminal of the failed storage device. A third switching circuit for switching and connecting the data input line of the register to the output terminal of another storage device.

According to the data processing device of the present invention, the number of storage devices is larger than the number of data of the plurality of data.
If one of these storage devices has a failure, the switching circuit changes the data input / output line connected to the input / output terminal of the failed storage device to the input / output terminal of another storage device. Switched to the output terminal and connected.
Thus, access to the failed storage device is prohibited, and data writing or reading is performed using the remaining storage devices.

In the case where an information holding means for holding information as to whether or not a failure has occurred is provided for each storage device, the switching circuit determines whether or not a failure has occurred based on the information in the information holding means. The data input / output line connected to the input / output terminal of the storage device designated to be present is switched to and connected to the input / output terminal of another storage device.

Further, according to the present invention, by the switching circuit,
The data input / output line connected to the input / output terminal of the failed storage device is switched and connected to the input / output terminal of the adjacent storage device. Then, the subsequent adjacent data input / output lines are also sequentially switched to the input / output terminals of the adjacent storage device and connected.

According to the parallel processor of the present invention,
Serial data is input to a data input register, converted into parallel data, and output to the processor element group in parallel. In the processor element group,
If the number of storage devices is greater than the number of processor elements and one of the storage devices has a failure, the arithmetic unit connected to the input / output terminal of the failed storage device Are switched to and connected to input / output terminals of another storage device.

Thus, in the processor element group, access to the failed storage device is prohibited, data is written or read using the remaining number of storage devices, and the second data is written in parallel. Output to the data output register. Then, in the data output register, the parallel data is converted into serial data and output.

When one storage device of the processor element group has a fault, for example, the data output line of the data input register connected to the input terminal of the faulty storage device by the second switching circuit becomes: The connection is switched to the input terminal of another storage device. Further, when one storage device of the processor element group has a failure, for example, the data input line of the data output register connected to the output terminal of the failed storage device by the third switching circuit is connected to another storage device. It is switched to the output terminal of the device and connected.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a data processing device according to the present invention.

The data processing device 10 includes (n + 1) storage devices (memory) 101-1 to 101-n + 1, n arithmetic units (ALU) 102-1 to 102-n, and n switching units. It is composed of signal generation circuits 103-1 to 103-n and n switching circuits 104-1 to 104-n.
Is processed in parallel. Here, n is a natural number.

Each of the storage devices 101-1 to 101-n + 1 is selected from a column selection line based on a column address and a row selection line based on a row address. According to n, data is written or read through the switching circuits 104-1 to 104-n.

Data input / output terminal T of storage device 101-1
1 is connected to the input / output terminal (L) of the switching circuit 104-1. The input / output terminal T2 of the storage device 101-2 is connected to the input / output terminal (H) of the switching circuit 104-1 and the switching circuit 1
04-2 is connected to the input / output terminal (L). Similarly, the input / output terminal T3 of the storage devices 101-3 to 101-n
To Tn are connected to the input / output terminals (H) of the switching circuits 104-2 to 104-n-1 at the preceding stage, and input / output terminals of the switching circuits 104-3 to 104-n at the corresponding stage (the same stage). It is connected to the output terminal (L). Then, the storage device 104
The -n + 1 input / output terminal Tn + 1 is connected to the input / output terminal (H) of the switching circuit 104-n.

The storage devices 101-1 to 101-n + 1 store n
In the data processing device 10 that processes the pieces of data in parallel, n pieces of data are accessed by the arithmetic devices 102-1 to 102-n. In principle, the storage device 101-
1 to 101-n are accessed by the arithmetic units 102-1 to 102-n provided correspondingly. If one of the storage devices has a failure, the n storage devices excluding the storage device are replaced with the arithmetic devices 102-1 to 102-1.
2-n.

The computing devices 102-1 to 102-n are provided corresponding to the storage devices 101-1 to 101-n, and store the data in accordance with the switching state of the switching circuits 104-1 to 104-n. The data stored in the devices 101-1 to 101-n or the storage devices 101-2 to 101-n + 1 at the next stage (adjacent) are read out, subjected to arithmetic processing, and the operation results are written back. Also, for example, the arithmetic units 102-1 to 102-1
02-n, the corresponding storage devices 101-1 to 101-
It has a register RF as information holding means for storing information as to whether or not n has a failure. Then, each of the arithmetic units 102-1 to 102-n converts the switching signal generation circuits 103-1 to 103-
n. Specifically, when information indicating that the storage device corresponding to the register FR has a failure and is defective is stored, a high-level signal is supplied to the corresponding switching signal generation circuits 103-1 to 103-n. I do.

When receiving the high-level information from the corresponding register FR, the switching signal generation circuit 103-1 generates a high-level switching signal SSW and outputs the high-level switching signal SSW.
-1 and the next-stage switching signal generation circuit 10
3-2.

Switching signal generation circuits 103-2 to 103-n-
1 indicates a case where high-level information is received from the corresponding register FR or the switching signal generation circuit 103
-1 to 103-n-2, the high-level switching signal SSW
In response to the switching signal generation circuit 103, a high-level switching signal SSW is generated and supplied to the corresponding switching circuits 104-2 to 104-n-1.
04-n.

FIG. 2 shows switching signal generation circuits 103-2 to 103-1.
03-n-1 is shown as an example. As shown in FIG. 2, the switching signal generation circuits 103-2 to 103-n-1 have a two-input OR
It is constituted by a gate GT.

The switching signal generation circuit 103-n receives the high-level information from the corresponding register FR or receives the high-level switching signal SSW from the preceding switching signal generation circuit 103-n-1. The high-level switching signal SSW is generated and supplied to the corresponding switching circuit 104-n.

The switching circuits 104-1 to 104-n are each provided with an input / output terminal (A).
02-1 to 102-n are connected to the data input / output terminals,
When the switching signal SSW is received from the corresponding switching signal generation circuits 103-1 to 103-n and the switching signal SSW is at a low level, the input / output terminal (A) and the input / output terminal (L) are connected. When the switching signal SSW is switched to the high level, the connection of the input / output terminal (A) is switched to the input / output terminal (H).

Then, as described above, the switching circuit 104
-1 to 104-n input / output terminals (L) correspond to the data input / output terminals T1 to T of the storage devices 101-1 to 101-n.
n, and the input / output terminal (H) is connected to the data input / output terminal T2 of the next (adjacent) storage device 101-2 to 101-n + 1.
To Tn + 1.

Next, the operation of the above configuration will be described with reference to FIG. Here, the i-th (1 <i <n) -th storage device 101-i is defective and the corresponding arithmetic device 102-i
An example will be described in which information of a high logic level indicating a defect is stored in the register FR of i.

At this time, since the storage device 101-i-1 at the preceding stage is not defective, information of a low logic level is stored in the register FR of the corresponding arithmetic device 102-i-1. Therefore, the switching signal generation circuit 103-i-1
, A low-level switching signal SSW is generated, and the switching circuit 104-i-1 and the next-stage switching signal generation circuit 103-
i. In the switching circuit 104-i-1 receiving the low-level switching signal SSW, the input / output terminal (A) connected to the data input / output terminal of the arithmetic unit 102-i-1 is connected to the input / output terminal of the storage device 101-i-1. It is kept connected to the input / output terminal (L) connected to the output terminal Ti-1. Therefore, the storage device 101-i-1 stores the corresponding arithmetic device 102
Accessed by −i-1.

On the other hand, the defective storage device 101-i
, The low-level switching signal SSW is supplied by the previous-stage switching signal generation circuit 103-i-1, but since the information in the register FR is high, Is generated and supplied to the switching circuit 104-i and the next-stage switching signal generation circuit 103-i + 1. In the switching circuit 104-i that has received the high-level switching signal SSW, the arithmetic unit 1
The input / output terminal (A) connected to the data input / output terminal 02-i is connected to the input / output terminal Ti + of the next storage device 101-i + 1.
The connection is switched to the input / output terminal (H) connected to 1. Therefore, the storage device 101-i is not accessed by any arithmetic device, and the storage device 101-i of the next stage is not accessed.
i + 1 is accessed by the arithmetic unit 102-i.

The switching signal generation circuit 103- corresponding to the storage device 101-i + 1 receiving the high level switching signal SSW.
At i + 1, a high-level switching signal SSW is generated,
Switching circuit 104-i + 1 and next-stage switching signal generation circuit 1
03-i + 2. High level switching signal SSW
In the switching circuit 104-i + 1 receiving the signal, the arithmetic unit 102-
Input / output terminal (A) connected to i + 1 data input / output terminal
Is switched to the connection with the input / output terminal (H) connected to the input / output terminal Ti + 2 of the storage device 101-i + 2 at the next stage.
Therefore, the next-stage storage device 101-i + 2 is accessed by the arithmetic device 102-i + 1.

Similarly, in the switching signal generation circuit 103-i + 2 corresponding to the storage device 101-i + 2 that has received the high level switching signal SSW, the high level switching signal SSW is generated and the switching circuit 104 is generated. −i + 2 and the next-stage switching signal generation circuit 103-i + 3 (not shown, there is no next-stage switching signal generation circuit in the case of the last n-th stage).
Switching circuit 104-receiving high-level switching signal SSW
At i + 2, the input / output terminal (A) connected to the data input / output terminal of the arithmetic unit 102-i + 2 is connected to the next storage unit 101-i.
Input / output terminal (H) connected to input / output terminal Ti + 3 of i + 3
Switch to connection with Therefore, the next-stage storage device 101-i + 3 is accessed by the arithmetic device 102-i + 2.

As described above, when there is a defective storage device,
The data input / output lines of the arithmetic unit provided correspondingly
Replaced by connection to the input / output terminal of the next storage device,
Thereafter, the data input / output line of the arithmetic unit is replaced with the connection to the input / output terminal of the next (adjacent) storage device, and data input / output between n storage devices and n arithmetic units is performed in parallel. Will be

As described above, according to the first embodiment, (n + 1) storage devices 101-1 to 101-n + 1 having input / output terminals T1 to Tn + 1, and storage device 10
Arithmetic unit 102 provided corresponding to 1-1 to 101n
-1 to 102-n and n storage devices 101-1 to 10-1
1-n, n registers FR for holding information on whether or not the corresponding storage device is defective;
Is provided corresponding to the storage devices 101-1 to 101-n, and when the information in the corresponding register FR indicates a failure of the storage device or when a switching signal from the preceding stage is received at a high level, the switching signal SSW of a high level is provided. Signal generation circuit 103 for outputting a signal to a next-stage circuit and a corresponding switching circuit in the same stage
-1 to 103-n and n arithmetic units 102-1 to 10-10
2-n, and when the switching signal is at a low level, the data input / output line of the arithmetic unit is connected to the corresponding input / output terminal of the storage device, and when the switching signal is switched to the high level, Since the switching circuits 104-1 to 104-n are provided for switching and connecting the data input / output lines from the input / output terminals of the corresponding storage device to the input / output terminals of the storage device at the next stage, it is possible to minimize the area increase. There is an advantage that the remedy rate when a failure occurs can be increased.

In this case, for example, when 100 arithmetic units are arranged, the area increase is only 101/100 = 1.01.

In this embodiment, the register FR holding information indicating whether or not the corresponding storage device is defective.
Has been described by way of example in the arithmetic device, but the present invention is not limited to this, and it goes without saying that various modes such as externally providing them are possible.

Second Embodiment FIG. 4 is a circuit diagram showing a data processing apparatus according to a second embodiment of the present invention.

The difference between the second embodiment and the first embodiment is that instead of connecting the input / output terminal (H) of each switching circuit to the input / output terminal of the next-stage storage device, all the switching circuits are switched. The input / output terminal (H) of the circuit is commonly connected to the input / output terminal Tn + 1 of the last storage device 101-n + 1 via the signal line GL, and if there is one defective storage device, This is because the storage device 101-n + 1 is substituted.

In the case of the second embodiment, the switching signal generation circuits 103a-1 to 103a-n output the switching signal SSW to the switching circuit 104a of the same stage as shown in FIG.
The signals are only output to -1 to 104a-n and need not be output to the next-stage switching signal generation circuit. The switching signal generation circuits 103a-1 to 103a-n according to the present embodiment, for example, can be configured by replacing with a register FR holding information indicating whether or not a corresponding storage device is defective.

Next, the operation of the above configuration will be described with reference to FIG. Here, the i-th (1 <i <n) -th storage device 101-i is defective and the corresponding arithmetic device 102-i
An example will be described in which information of a high logic level indicating a defect is stored in register FR.

At this time, since the storage device 101-i-1 at the preceding stage is not defective, information of a low logic level is stored in the register FR of the corresponding arithmetic device 102-i-1. Therefore, the switching signal generation circuit 103a-i-
1 generates a low-level switching signal SSW, which is supplied to the switching circuit 104a-i-1. In the switching circuit 104a-i-1 that has received the low-level switching signal SSW, the input / output terminal (A) connected to the data input / output terminal of the arithmetic device 102-i-1 is connected to the input / output terminal of the storage device 101-i-1. Output terminal Ti-1
Is maintained in a state of being connected to the input / output terminal (L) connected to the terminal. Therefore, the storage device 101-i-1 is accessed by the corresponding arithmetic device 102-i-1.

On the other hand, the defective storage device 101-i
Since the information in the register FR is at the high level, the switching signal generation circuit 103a-i corresponding to
Supplied to In the switching circuit 104a-i that has received the high-level switching signal SSW, the input / output terminal (A) connected to the data input / output terminal of the arithmetic device 102-i is connected to the signal line G
The connection is switched to the input / output terminal (H) connected to the input / output terminal Tn + 1 of the last storage device 101-n + 1 via L. Therefore, the storage device 101-i is not accessed by any arithmetic device, and the storage device 1 at the last stage is not accessed.
01-i + 1 is accessed by the arithmetic unit 102-i.

At this time, the storage device 101-
Since i + 1 is not defective, the corresponding arithmetic unit 102a-
The register FR of i + 1 stores information of a low logic level. Therefore, the switching signal generation circuit 10
A low-level switching signal SSW is generated from 3a-i + 1 and supplied to the switching circuit 104a-i + 1. In the switching circuit 104a-i + 1 that has received the low-level switching signal SSW, the input / output terminal (A) connected to the data input / output terminal of the arithmetic device 102-i + 1 is connected to the input / output terminal of the storage device 101-i + 1. It is kept connected to the input / output terminal (L) connected to the output terminal Ti + 1. Therefore, the storage device 101-i + 1
Are accessed by the corresponding arithmetic unit 102-i + 1.

As described above, when there is a defective storage device,
The data input / output lines of the arithmetic unit provided correspondingly
The connection to the input / output terminals of the storage device at the last stage is replaced, and the input / output of data between the n storage devices and the n arithmetic devices is performed in parallel.

According to the second embodiment, the first
The same effect as that of the embodiment can be obtained.

Third Embodiment FIG. 6 is a circuit diagram showing a third embodiment of the data processing apparatus according to the present invention.

The data processing device 20 includes (n + 1) storage devices (memory) 201-1 to 201-n + 1, a data input register (DIR) 202, and n switching signal generation circuits 203-1 to 203. -N and n switching circuits 2
04-1 to 204-n, and processes n pieces of data in parallel. Here, n is a natural number larger than 2.

Each of the storage devices 201-1 to 201-n + 1 is constituted by, for example, a DRAM or an SRAM selected by a column selection line based on a column address and a row selection line based on a row address. Remember.

Data input terminal IT of storage device 201-1
1 is connected to the output terminal (L) of the switching circuit 204-1. The input terminal IT2 of the storage device 201-2 is connected to the output terminal (H) of the switching circuit 204-1 and the switching circuit 204.
-2 output terminal (L). Similarly, the input terminals IT3 to ITn of the storage devices 201-3 to 201-n
Are connected to the output terminals (H) of the preceding-stage switching circuits 204-2 to 204-n-1 and output terminals (L) of the corresponding-stage (same-stage) switching circuits 204-3 to 204-n. )It is connected to the. Then, the storage device 204-n +
The 1 input terminal ITn + 1 is connected to the output terminal (H) of the switching circuit 204-n.

The storage devices 201-1 to 201-n + 1 store n
In the data processing device 20 that processes a plurality of pieces of data in parallel, n pieces of data are accessed by the data input register 202. When one storage device has a failure, n storage devices other than the storage device are accessed by the data input register 202.

The data input register 202 receives a plurality of (n) data SINs composed of serial data,
Switching to parallel data and switching circuits 204-1 to 204-n
Output to For example, when the input serial data is pixel data for one scanning line in image processing, the parallel data is output during a blanking period.

Further, for example, data input register 202
Indicates each of the storage devices 201-1 to 201 as data output destinations.
A register FR for storing information on whether or not there is a failure in -n
N. Then, the data input register 202
Supplies the information of the register FR to the corresponding switching signal generation circuits 203-1 to 203-n. Specifically, when information indicating that there is a failure is stored in the storage device corresponding to the register FR, a high-level signal is supplied to the corresponding switching signal generation circuits 203-1 to 203-n.

When receiving the high-level information from the corresponding register FR, the switching signal generation circuit 203-1 generates a high-level switching signal SSW, and outputs the high-level switching signal SSW.
-1 and the next-stage switching signal generation circuit 20
3-2.

Switching signal generation circuits 203-2 to 203-n-
1 is when the high-level information is received from the corresponding register FR or when the switching signal generation circuit 203 of the preceding stage is received.
-1 to 203-n-2, the high-level switching signal SSW
In response to the switching signal generation circuit 203, a high-level switching signal SSW is generated and supplied to the corresponding switching circuits 204-2 to 204-n-1.
04-n.

The switching signal generation circuits 203-2 to 203-20
3-n-1 is constituted by a 2-input OR gate GT, for example, as in FIG.

The switching signal generation circuit 203-n receives the high-level information from the corresponding register FR or receives the high-level switching signal SSW from the preceding switching signal generation circuit 203-n-1. The high-level switching signal SSW is generated and supplied to the corresponding switching circuit 204-n.

The switching circuits 204-1 to 204-n are respectively connected to the data output terminals of the data input register 202 provided with the corresponding input terminals (A), and correspond to the corresponding switching signal generation circuits 203-1 to 204-n. In response to the switching signal SSW by the signal 203-n, when the switching signal SSW is at a low level, the input terminal (A) is connected to the output terminal (L), and when the switching signal SSW is switched to a high level, the input terminal The connection of (A) is switched to the output terminal (H) side.

Then, as described above, the switching circuit 204
The data input terminals IT1 to IT of the storage devices 201-1 to 201-n correspond to the output terminals (L) of −2 to 204-n.
n, and the output terminal (H) is connected to the data input terminals IT2 to IT2 of the storage devices 201-2 to 201-n + 1 of the next stage (adjacent).
It is connected to ITn + 1.

Next, the operation of the above configuration will be described with reference to FIG. Here, the i-th (1 <i <n) -th storage device 201-i is defective and the data input register 202
An example in which the corresponding register FR stores information of a high logic level indicating a defect will be described.

At this time, since the storage device 201-i-1 at the preceding stage is not defective, the register FR corresponding to the data input register 202 stores information of a low logic level. Therefore, the switching signal generation circuit 203-
A low-level switching signal SSW is generated from i-1 and the switching circuit 204-i-1 and the next-stage switching signal generation circuit 20
3-i. In the switching circuit 204-i-1 receiving the low-level switching signal SSW, the data input register 2
The input terminal (A) connected to the (i-1) th data output terminal of the storage device 201 is the input terminal ITi- of the storage device 201-i-1.
It is kept connected to the output terminal (L) connected to 1. Therefore, the data output from the corresponding output terminal of the data input register 202 is stored in the storage device 201-i-1.

On the other hand, the defective storage device 201-i
, A low-level switching signal SSW is supplied by the preceding-stage switching signal generation circuit 203-i-1, but since the information in the register FR is at a high level, Is generated and supplied to the switching circuit 204-i and the next-stage switching signal generation circuit 203-i + 1. In the switching circuit 204-i that has received the high-level switching signal SSW, the input / output terminal (A) connected to the i-th data output terminal of the data input register 202 is connected to the input of the next-stage storage device 201-i + 1. The connection is switched to the output terminal (H) connected to the terminal ITi + 1. Therefore, the storage device 201-i is not accessed, and the data output from the i-th data output terminal is stored in the next storage device 201-i + 1.

The switching signal generation circuit 203- corresponding to the storage device 201-i + 1 receiving the high level switching signal SSW
At i + 1, a high-level switching signal SSW is generated,
Switching circuit 204-i + 1 and next-stage switching signal generation circuit 2
03-i + 2. High level switching signal SSW
In the switching circuit 204-i + 1 receiving this, the input terminal (A) connected to the (i + 1) -th data output terminal of the data input register 202 becomes the input terminal ITi + of the storage device 201-i + 2 in the next stage. The connection to the output terminal (H) connected to 2 is switched. Therefore, the data input register 202
The data output from the (i + 1) th data output terminal is stored in the next-stage storage device 201-i + 2.

Similarly, the switching signal generation circuit 203-i + 2 corresponding to the storage device 201-i + 2 that has received the high-level switching signal SSW generates the high-level switching signal SSW, and −i + 2 and the next-stage switching signal generation circuit 203-i + 3 (not shown, and in the case of the last n-th stage, there is no next-stage switching signal generation circuit).
Switching circuit 204-receiving high-level switching signal SSW
At i + 2, the input terminal (A) connected to the (i + 2) th data output terminal of the data input register 202 is the output terminal connected to the input terminal ITi + 3 of the next storage device 201-i + 3. (H). Therefore, the data output from the (i + 2) th data output terminal of the data input register 202 is stored in the next storage device 20.
It is stored in 1-i + 3.

As described above, when there is a defective storage device,
The data output line of the correspondingly provided data input register is replaced with a connection to the input terminal of the storage device of the next stage, and the data output line of the data input register thereafter becomes the input terminal of the storage device of the next stage (adjacent). And the operation of storing the parallel data in the storage device is performed.

As described above, according to the third embodiment, as in the first embodiment, it is possible to increase the rescue rate when a failure occurs while minimizing the area increase. There are advantages that can be done.

In this embodiment, the register FR holding information indicating whether or not the corresponding storage device is defective.
Has been described as an example in which is provided in the data input register.
The present invention is not limited to this, and it is needless to say that various modes such as externally provided are possible.

Fourth Embodiment FIG. 8 is a circuit diagram showing a fourth embodiment of the data processing device according to the present invention.

The difference between the fourth embodiment and the third embodiment is that instead of connecting the output terminal (H) of each switching circuit to the input terminal of the next-stage storage device, all the switching circuits are switched. The output terminal (H) is commonly connected to the input terminal ITn + 1 of the last storage device 201-n + 1 via the signal line GL, and if there is one defective storage device, all the storage devices 201
-N + 1.

In the case of the fourth embodiment, the switching signal generation circuits 203a-1 to 203a-n output the switching signal SSW to the switching circuit 204a of the same stage as shown in FIG.
The signals are only output to −1 to 204-n and need not be output to the next-stage switching signal generation circuit. The switching signal generation circuits 203a-1 to 203a-n according to the present embodiment, for example, can be configured by replacing with a register FR that holds information indicating whether a corresponding storage device is defective.

According to the fourth embodiment, the same effects as those of the third embodiment can be obtained.

Fifth Embodiment FIG. 9 is a circuit diagram showing a data processing apparatus according to a fifth embodiment of the present invention.

The data processing device 30 includes (n + 1) storage devices (memory) 301-1 to 301-n + 1, a data output register (DOR) 302, and n switching signal generation circuits 303-1 to 303. -N and n switching circuits 3
04-1 to 304-n, and processes n pieces of data in parallel. Here, n is a natural number larger than 2.

Each of the storage devices 301-1 to 301-n + 1 is selected by a column selection line based on a column address and a row selection line based on a row address, and is constituted by, for example, a DRAM or an SRAM. OT
Output from n.

The output terminal OT1 of the storage device 301-1 is
It is connected to the input terminal (L) of the switching circuit 304-1. The output terminal OT2 of the storage device 301-2 is connected to the input terminal (H) of the preceding switching circuit 304-1 and the switching circuit 30.
4-2 is connected to the input terminal (L). Similarly, the output terminals OT3 to OT of the storage devices 301-3 to 301-n
n is connected to the input terminals (H) of the switching circuits 304-2 to 304-n-1 in the preceding stage, and is connected to the input terminals (H) of the switching circuits 304-3 to 304-n in the corresponding stage (the same stage). L). Then, the storage device 304-n +
1 output terminal OTn + 1 is connected to the input terminal (H) of the switching circuit 204-n.

The output data of the storage devices 301-1 to 301-n + 1 accepted by the data output register 302 is as follows:
n. When one storage device has a failure, data of n storage devices excluding the storage device is output to the data output register 302.

The data output register 302 includes the switching circuit 3
The parallel data input through the input terminals 04-1 to 304-n are converted into serial data SOUT and output. Further, for example, the data output register 302 has n registers FR for storing information as to whether or not each of the storage devices 301-1 to 301-n that output data has a failure. Then, the data output register 302 stores the register F
Switching signal generation circuit 303 provided corresponding to R information
-1 to 303-n. Specifically, register F
If information indicating that there is a failure is stored in the storage device corresponding to R, a high-level signal is supplied to the corresponding switching signal generation circuits 303-1 to 303-n.

When receiving the high level information from the corresponding register FR, the switching signal generation circuit 303-1 generates a high level switching signal SSW, and
-1 and the switching signal generation circuit 30 of the next stage.
3-2.

Switching signal generation circuits 303-2 to 303-n-
1 is when the high-level information is received from the corresponding register FR or when the switching signal generation circuit 303
-1 to 303-n-2, the high-level switching signal SSW
When receiving the switching signal, the switching signal generating circuit 303 generates a high-level switching signal SSW and supplies it to the corresponding switching circuits 304-2 to 304-n-1.
04-n.

The switching signal generation circuits 303-2 to 303-30
3-n-1 is constituted by a 2-input OR gate GT, for example, as in FIG.

The switching signal generation circuit 303-n receives the high-level information from the corresponding register FR or receives the high-level switching signal SSW from the preceding switching signal generation circuit 303-n-1. A high-level switching signal SSW is generated and supplied to the corresponding switching circuit 304-n.

The switching circuits 304-1 to 304-n are respectively connected to the data output terminals of the data output register 302 provided with the corresponding output terminals (A), and the corresponding switching signal generation circuits 303-1 to 304-n. In response to the switching signal SSW by 303-n, when the switching signal SSW is at a low level, the output terminal (A) is connected to the input terminal (L). When the switching signal SSW is switched to a high level, the output terminal (A) is output. The connection of (A) is switched to the input terminal (H) side.

Then, as described above, the switching circuit 304
The input terminals (L) of −2 to 304-n are connected to the output terminals OT1 to OTn of the corresponding storage devices 301-1 to 301-n, and the input terminal (H) is connected to the storage device 30 of the next stage (adjacent).
1-2 to 301-n + 1 are connected to output terminals OT2 to OTn + 1.

Next, the operation of the above configuration will be described with reference to FIG. Here, the i-th (1 <i <n) -th storage device 301-i is defective and the data input register 30
An example will be described in which information corresponding to a high logic level indicating a failure is stored in the corresponding register FR of No. 2.

At this time, since the storage device 301-i-1 at the preceding stage is not defective, the register FR corresponding to the data output register 302 stores information of a low logic level. Therefore, the switching signal generation circuit 303-
i-1 generates a low-level switching signal SSW, and the switching circuit 304-i-1 and the next-stage switching signal generation circuit 303
-I. In the switching circuit 304-i-1 receiving the low-level switching signal SSW, the data output register 30
The output terminal (A) connected to the second (i-1) th data input terminal is the output terminal OTi-1 of the storage device 301-i-1.
Is maintained in a state of being connected to the input terminal (L) connected to the input terminal (L). Therefore, the data output from the storage device 301-i-1 corresponds to the data (i
+1) th input terminal.

On the other hand, the defective storage device 301-i
, The switching signal generation circuit 303-i-1 of the preceding stage supplies a low-level switching signal SSW. However, since the information in the register FR is at a high level, the switching signal generation circuit 303-i has a high level. Is generated and supplied to the switching circuit 304-i and the next-stage switching signal generation circuit 303-i + 1. In the switching circuit 304-i that has received the high-level switching signal SSW, the output terminal (A) connected to the i-th data input terminal of the data output register 302 becomes the output terminal of the storage device 301-i + 1 in the next stage. The connection is switched to the input terminal (H) connected to OTi + 1. Therefore, the storage device 301-i is not accessed, and the output terminal OT of the next storage device 301-i + 1 is not accessed.
The data output from i + 1 is
2 is input to the i-th data input terminal.

The switching signal generation circuit 303- corresponding to the storage device 301-i + 1 receiving the high level switching signal SSW
At i + 1, a high-level switching signal SSW is generated,
Switching circuit 304-i + 1 and next-stage switching signal generation circuit 3
03-i + 2. High level switching signal SSW
In the switching circuit 304-i + 1 receiving this, the output terminal (A) connected to the (i + 1) -th data input terminal of the data output register 302 becomes the output terminal OTi + of the storage device 301-i + 2 in the next stage. The connection is switched to the input terminal (H) connected to 2. Therefore, the next storage device 301-i +
The data output from the second output terminal OTi + 2 is input to the (i + 1) -th data input terminal of the data output register 302.

Similarly, in the switching signal generation circuit 303-i + 2 corresponding to the storage device 301-i + 2 that has received the high level switching signal SSW, the high level switching signal SSW is generated and the switching circuit 304 is generated. −i + 2 and the next-stage switching signal generation circuit 203-i + 3 (not shown, and in the case of the last n-th stage, there is no next-stage switching signal generation circuit).
Switching circuit 304-receiving high-level switching signal SSW
At i + 2, the output terminal (A) connected to the (i + 2) -th data input terminal of the data output register 302 is the input terminal connected to the output terminal OTi + 3 of the storage device 301-i + 3 at the next stage. (H). Therefore, the data output from the output terminal OTi + 3 of the storage device 301-i + 3 at the next stage is input to the (i + 2) th data input terminal of the data output register 302.

As described above, when there is a defective storage device,
The data input line of the corresponding data output register is replaced with a connection to the output terminal of the storage device of the next stage, and the data input line of the data output register thereafter becomes the output terminal of the storage device of the next stage (adjacent). , The input operation of the parallel data to the data output register 302 is performed.

Then, the parallel data input to the data output register 302 is converted into serial data and output.

As described above, according to the fifth embodiment, as in the third embodiment described above, it is possible to increase the rescue rate in the event of a failure while minimizing the area increase. There are advantages that can be done.

In this embodiment, the register FR holding information indicating whether or not the corresponding storage device is defective.
Has been described as an example in which is provided in the data output register.
The present invention is not limited to this, and it is needless to say that various modes such as externally provided are possible.

Sixth Embodiment FIG. 11 is a circuit diagram showing a data processing apparatus according to a sixth embodiment of the present invention.

The difference between the sixth embodiment and the fifth embodiment described above is that instead of connecting the output terminal (H) of each switching circuit to the input terminal of the next-stage storage device, all the switching circuits are switched. The output terminal (H) is commonly connected to the input terminal ITn + 1 of the last storage device 301-n + 1 via the signal line GL, and if there is one defective storage device, all the storage devices 301
-N + 1.

In the case of the sixth embodiment, the switching signal generation circuits 303a-1 to 303a-n
As shown in the figure, the switching signal SSW is supplied to the switching circuit 304 of the same stage.
a-1 to 304-n, and need not be output to the next-stage switching signal generation circuit. Note that the switching signal generation circuits 303a-1 to 303a-n according to the present embodiment, for example, can be configured by replacing with a register FR holding information indicating whether or not a corresponding storage device is defective.

According to the sixth embodiment, the same effects as those of the fifth embodiment can be obtained.

Seventh Embodiment FIG. 12 is a diagram showing a seventh embodiment of the present invention.
FIG. 2 is a circuit diagram showing a parallel processor in which the data processing device of FIG. 1 is applied as a PE group.

The parallel processor 40 includes a data input register 401, a PE (processor element) group 40,
2 and a data output register 403.

The data input register 401 receives a plurality of (n) pieces of first data SIN composed of serial data, converts the data into parallel data, and outputs the parallel data to the PE group 402.

The PE group 402 is constituted by a circuit similar to the data processing circuit shown in FIG. 1 showing the first embodiment. That is, the PE group 402 includes (n + 1) storage devices (memory) 101-1 to 101-n + 1, n arithmetic units (ALU) 102-1 to 102-n, and n switching signal generation circuits. 103-1 to 103-n and n switching circuits 104-1 to 104-n, and processes n data in parallel. The PE group 402 includes the storage devices 101-1 to 101-n of the same stage, excluding the storage device 101-n + 1, and n arithmetic units (ALUs).
102-1 to 102-n, n switching signal generation circuits 10
3-1 to 103-n and n switching circuits 104-1
PE1 to PEn are respectively constituted by the elements PE1 to PEn.

However, the storage device 1 in the PE group 402
01-1 to 101-n + 1 are data input registers 401
Instead of being directly accessed by the data output register 403, data is written or read via the arithmetic units 102-1 to 102-n and the switching circuits 104-1 to 104-n.

The data output register 403 stores the PE group 40
The plurality of (n) second data output in parallel from the two arithmetic devices 102-1 to 102-n are converted into serial data SO
Convert to UT and output.

Next, the operation of the above configuration will be described. For example, a video signal in which each pixel is composed of a plurality of bits is sequentially input to an input terminal in pixel units. In the time of the first one horizontal period, the pixel data of the first line is 1
The data is stored in the data input register 401 having the capacity of the line. The data of each pixel on the first line of the video signal stored in the data input register 401 is output in parallel during the subsequent blanking period, and one pixel of data per PE corresponds to the number of lines (n ) PE lined up
Arithmetic units 102-1 to PE-1 of PE1 to PE-n of group 402
02-n are supplied in parallel.

Then, in the next one horizontal period, each arithmetic unit 1
In 02-1 to 102-n, arithmetic processing is performed on the supplied pixel data of the first line. In parallel with this, pixel data of the second line is sequentially input to the data input register 401. During the subsequent blanking period, the processed pixel data of the first line is supplied in parallel to the data output register 403 from the arithmetic units 102-1 to 102-n. In parallel with this, the pixel data of the second line is output from the data input register 401 to the PE group 402.
Are supplied in parallel. In the next one horizontal period, the pixel data of the first line stored in the data output register 403 is sequentially output to the output terminal as serial data. In parallel with this, the arithmetic units 102-1 to 102-n have 2
The arithmetic processing of the pixel data of the line is performed, and the pixel data of the third line is sequentially input to the data output register 403.

In the above operation, the data transferred from data input register 401 is stored in arithmetic unit 102-
It is stored in n storage devices via 1-102-n.
At this time, if there is a defective storage device, the data input / output line of the processing device provided correspondingly is replaced with the connection with the input / output terminal of the storage device of the next stage, and thereafter the data input / output line of the processing device is provided. Is replaced by a connection to the input / output terminal of the next (adjacent) storage device, and data input / output between the n storage devices and the n arithmetic devices is performed in parallel. Specifically, the switching operation is performed in the same manner as the operation described in detail in the first embodiment, and a description thereof will not be repeated.

Thereafter, when the PE group 402 is processing the pixel data of the i-th line, the data input register 4
01 repeatedly inputs the pixel data of the (i + 1) th line, and the data output register 403 repeatedly outputs the pixel data of the (i-1) th line. Data input register 401, PE group 402, and data output register 40
3 operate in synchronism as described above, whereby a video signal that has been subjected to arithmetic processing for each horizontal period is extracted. In this way, for example, digital processing of a video signal is performed.

According to the seventh embodiment, when a memory defect is replaced with a redundant memory and the memory is rescued, a parallel processor which can reduce the increase in area by replacing the input / output and rescuing the memory is realized. There are advantages that can be.

In the seventh embodiment, the PE group 40
Although the case where the circuit having the configuration of FIG. 1 is applied as the example 2 has been described as an example, the circuit of FIG. 4 can also be applied, and in this case, the same effect as that described above can be obtained.

Eighth Embodiment FIG. 13 is a diagram showing an eighth embodiment of the present invention, and is a circuit diagram showing a parallel processor constituted by combining the data processing devices of FIGS. 1, 6, and 9. It is.

The parallel processor 40a includes a PE group 40
The data processing device of FIG. 1 is applied as 2a, the data processing device of FIG. 6 is applied as the data input register 401a, and the data processing device of FIG. 9 is applied as the data input register 403a. However, the (n + 1) storage devices 101-1 to 101-n + 1 in the PE group 402a
However, the parallel processor 40a is configured by sharing the storage devices 201-1 to 201-n in FIG. 6 and the storage devices 301-1 to 301-n in FIG.

The parallel processor 40a differs from the above-described seventh embodiment in that the storage devices 101-1 to 101-n + 1 of the PE group 402a are stored in the arithmetic unit 102-1.
To 102-n and the data input register 401a and the data output register 403a directly without passing through the switching circuits 104-1 to 104-n.

The operation of each unit is performed in the same manner as the operation described in detail in the first, third, and fifth embodiments. A series of operations for switching the defective memory device of the parallel processor are described above. Since the operation is performed in the same manner as that described in the seventh embodiment, the description thereof is omitted here.

According to the eighth embodiment, when a memory defect is replaced by a redundant memory and the memory is rescued, a parallel processor that can reduce the area increase by replacing the input / output and rescuing the memory is realized. There are advantages that can be.

In the eighth embodiment, the PE group 40
2a, the data processing device of FIG. 6 is applied as the data input register 401a, and the data processing device of FIG. 9 is applied as the data input register 403a. 4, FIG. 8,
The circuit in FIG. 11 can be appropriately combined and applied, and in this case, the same effect as the above-described effect can be obtained.

[0138]

As described above, according to the present invention,
There is an advantage that the remedy rate in the event of a failure can be increased while minimizing the area increase.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a data processing device according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a switching signal generation circuit according to the present invention.

FIG. 3 is a diagram for explaining the operation of the circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a second embodiment of the data processing device according to the present invention.

FIG. 5 is a diagram for explaining the operation of the circuit of FIG. 4;

FIG. 6 is a circuit diagram showing a third embodiment of the data processing device according to the present invention.

FIG. 7 is a diagram for explaining the operation of the circuit of FIG. 6;

FIG. 8 is a circuit diagram showing a fourth embodiment of the data processing device according to the present invention.

FIG. 9 is a circuit diagram showing a fifth embodiment of the data processing device according to the present invention.

FIG. 10 is a diagram for explaining the operation of the circuit of FIG. 9;

FIG. 11 is a circuit diagram showing a sixth embodiment of the data processing device according to the present invention.

FIG. 12 is a view showing a seventh embodiment of the present invention,
FIG. 2 is a circuit diagram showing a parallel processor in which the data processing device of FIG. 1 is applied as a PE group.

FIG. 13 is a view showing an eighth embodiment of the present invention,
FIG. 10 is a circuit diagram showing a parallel processor configured by combining the data processing devices of FIGS. 1, 6, and 9;

FIG. 14 is a block diagram illustrating a configuration example of a general parallel processor.

FIG. 15 is a diagram for explaining a relationship between image data and pixel data.

FIG. 16 is a diagram illustrating a transmission method of image data.

FIG. 17 is a diagram for explaining a processing procedure of image data by a parallel processor.

FIG. 18 is a diagram illustrating a configuration example of a processor element (PE).

FIG. 19 is a diagram illustrating a configuration example in a case where a memory of each PE, which is a main part of a parallel processor, includes a redundant memory RD.

[Explanation of symbols]

10, 10a, 20, 20a, 30, 30a Data processing device, 101-1 to 101-n + 1, 201-1 to 20
1-n + 1, 301-1 to 301-n + 1 ... storage device, 10
2-1 to 102-n arithmetic unit (ALU), 103-1
To 103-n, 203-1 to 203-n, 303-1 to
303-n, 103a-1 to 103a-n, 203a-
1 to 203a-n, 303a-1 to 303a-n... Switching signal generation circuits, 104-1 to 104-n, 204-1 to 204-1
204-n, 304-1 to 304-n, 104a-1
104a-n, 204a-1 to 204a-n, 304a
-1 to 304a-n: switching circuit, 40, 40a: parallel processor, 401, 401a: data input register, 4
02, 402a ... PE group, 403, 403a ... data output register, FR ... register (information holding means).

Claims (29)

[Claims] 1. A data processing device for processing a plurality of data, the data processing device having a data input / output terminal, and writing and reading one of the plurality of data via the input / output terminal. If the number of storage devices is larger than the number of data of the plurality of data and one of the storage devices has a failure, the data input / output line connected to the input / output terminal of the failed storage device is
A switching circuit for switching connection to an input / output terminal of another storage device. 2. The information processing apparatus according to claim 1, further comprising: an information storage unit configured to store information indicating whether the storage device has a failure or not. 2. The data processing device according to claim 1, wherein the data input / output line connected to the input / output terminal of the device is switched to the input / output terminal of another storage device. 3. The switching circuit switches a data input / output line connected to an input / output terminal of a failed storage device to an input / output terminal of an adjacent storage device, and switches the data input / output line of the adjacent storage device. 2. The data processing device according to claim 1, wherein the lines are also sequentially switched to input / output terminals of adjacent storage devices. 4. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, wherein the switching circuit has a memory designated as defective by the information of the information holding means. The data input / output line connected to the input / output terminal of the device is switched to the input / output terminal of the adjacent storage device, and the subsequent adjacent data input / output lines are also sequentially switched to the input / output terminal of the adjacent storage device. The data processing device according to claim 1, wherein the data processing device is connected. 5. A data processing device for processing a plurality of data, the data processing device having a data input / output terminal, and writing and reading one of the plurality of data via the input / output terminal. A storage device having a number greater than the number of data of the plurality of data; an arithmetic device provided in correspondence with the number of the plurality of data, for exchanging data related to arithmetic with one storage device; and one storage device And a switching circuit for switching the data input / output line of the arithmetic unit connected to the input / output terminal of the failed storage device to the input / output terminal of another storage device when there is a failure in the storage device. apparatus. 6. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, wherein the switching circuit has a storage designated as defective by the information of the information holding means. 6. The data processing device according to claim 5, wherein a data input / output line of the arithmetic device connected to an input / output terminal of the device is switched to an input / output terminal of another storage device. 7. The switching circuit switches a data input / output line of the arithmetic unit, which has been connected to an input / output terminal of a failed storage device, to an input / output terminal of an adjacent storage device. 6. The data processing device according to claim 5, wherein the data input / output lines of the arithmetic unit are sequentially switched to the input / output terminals of the adjacent storage device. 8. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, and the switching circuit has a memory designated as defective by the information of the information holding means. The data input / output line of the arithmetic unit connected to the input / output terminal of the device is switched to the input / output terminal of the adjacent storage device, and the data input / output line of the next adjacent arithmetic unit is sequentially connected to the storage device. 6. The data processing device according to claim 5, wherein the data processing device is switched to an input / output terminal of the device. 9. A data processing device for processing a plurality of data in parallel, the data processing device having a data input terminal, and writing one of the plurality of data through the input terminal. If there is a failure in one storage device and the number of storage devices greater than the number of data in the storage device, connect the data input line connected to the input terminal of the failed storage device to the input terminal of the other storage device. A data processing device having a switching circuit for switching connection. 10. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, wherein the switching circuit has a memory designated as defective by the information of the information holding means. 10. The data processing device according to claim 9, wherein the data input line connected to the input terminal of the device is switched and connected to the input terminal of another storage device. 11. The switching circuit switches a data input line connected to an input terminal of a failed storage device to an input terminal of an adjacent storage device, and successively connects adjacent data input lines thereafter. 10. The data processing device according to claim 9, wherein the data processing device is switched and connected to an input terminal of the storage device. 12. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, wherein the switching circuit has a memory designated as defective by the information of the information holding means. 10. A data input line connected to an input terminal of a device is switched to an input terminal of an adjacent storage device, and subsequent adjacent data input lines are sequentially switched to an input terminal of an adjacent storage device. The data processing device according to claim 1. 13. A data processing device for processing a plurality of data in parallel, comprising a data output terminal, and reading one of the plurality of data via the input terminal. If there is a failure in one of the storage devices and the number of storage devices greater than the number of data in the storage device, the data output line connected to the output terminal of the failed storage device is connected to the output terminal of the other storage device. A data processing device having a switching circuit for switching connection. 14. The information processing apparatus according to claim 1, further comprising: an information holding unit configured to hold information indicating whether or not the storage device is defective due to a failure, wherein the switching circuit stores the information designated as defective by the information of the information holding unit. 14. The data processing device according to claim 13, wherein the data output line connected to the output terminal of the device is switched to the output terminal of another storage device and connected. 15. The switching circuit switches a data output line connected to an output terminal of a failed storage device to an output terminal of an adjacent storage device, and sequentially connects adjacent data output lines thereafter. 14. The data processing device according to claim 13, wherein the data processing device is switched and connected to an output terminal of the storage device. 16. An information holding means for holding information on whether or not a failure has occurred for each of the storage devices, and the switching circuit is provided for a storage device designated as defective by the information of the information holding means. 14. The data output line connected to the output terminal is switched to an output terminal of an adjacent storage device, and subsequent adjacent data output lines are sequentially switched to an output terminal of an adjacent storage device. Data processing device. 17. A data processing apparatus comprising: a plurality of first data consisting of serial data input to a data input register of serial input / parallel output; and a plurality of processor elements comprising a storage device and an arithmetic device for parallel output of the data input register. To the processor elements in parallel,
The first data is subjected to arithmetic processing by the processor element, and a plurality of second data output in parallel from the processor element as the arithmetic result is input in parallel to a data output register of a parallel input serial output;
A parallel processor that outputs the second data as serial data from a serial output of the data output register, wherein the number of storage devices in the processor element group is greater than the number of the processor elements, and the processor element group When one storage device has a failure, the data input / output line of the arithmetic device connected to the input / output terminal of the failed storage device is
A parallel processor having a switching circuit for switching connection to an input / output terminal of another storage device. 18. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, wherein the switching circuit has a memory designated as defective by the information of the information holding means. 18. The data processing device according to claim 17, wherein a data input / output line of the arithmetic device connected to an input / output terminal of the device is switched to an input / output terminal of another storage device. 19. The switching circuit switches a data input / output line of the arithmetic unit, which has been connected to an input / output terminal of a failed storage device, to an input / output terminal of an adjacent storage device, and connects the input / output terminal of the adjacent storage device. 18. The data processing device according to claim 17, wherein the data input / output lines of the processing device are sequentially switched to input / output terminals of the adjacent storage device. 20. An information storage unit for holding information on whether or not a failure has occurred in each of the storage devices, and the switching circuit has a storage designated as defective by the information in the information storage unit. The data input / output line of the arithmetic unit connected to the input / output terminal of the device is switched to the input / output terminal of the adjacent storage device, and the data input / output line of the next adjacent arithmetic unit is sequentially connected to the storage device. 18. The data processing device according to claim 17, wherein the data processing device is switched to an input / output terminal of the device. 21. A plurality of processor elements each comprising a plurality of first data consisting of serial data, input to a data input register of serial input parallel output, and a parallel output of the data input register comprising a storage device and an arithmetic device. To the processor elements in parallel,
The first data is subjected to arithmetic processing by the processor element, and a plurality of second data output in parallel from the processor element as the arithmetic result is input in parallel to a data output register of a parallel input serial output;
A parallel processor that outputs the second data as serial data from a serial output of the data output register, wherein the number of storage devices in the processor element group is greater than the number of the processor elements, and the processor element group A switching circuit that switches the data output line of the data input register connected to the input terminal of the failed storage device to the input terminal of another storage device when one of the storage devices has a failure. Parallel processor. 22. An information storage unit for holding information on whether or not a failure has occurred for each of the storage devices, wherein the switching circuit has a storage designated as defective by the information of the information storage unit. 22. The parallel processor according to claim 21, wherein a data output line of the data input register connected to an input terminal of the device is switched to an input terminal of another storage device. 23. The switching circuit switches a data output line of the data input register, which is connected to an input terminal of a failed storage device, to an input terminal of an adjacent storage device. 22. The parallel processor according to claim 21, wherein the output lines are also sequentially switched to input terminals of adjacent storage devices. 24. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, and the switching circuit has a memory designated as defective by the information of the information holding means. The data output line of the data input register connected to the input terminal of the device is switched to the input terminal of the adjacent storage device, and the subsequent adjacent data output lines are also sequentially switched to the input terminal of the adjacent storage device. The parallel processor according to claim 21, which is connected. 25. A semiconductor device comprising: a plurality of first elements consisting of serial data input to a data input register of serial input parallel output; and a plurality of processor elements comprising a storage device and an arithmetic device for parallel output of the data input register. To the processor elements in parallel,
The first data is subjected to arithmetic processing by the processor element, and a plurality of second data output in parallel from the processor element as the arithmetic result is input in parallel to a data output register of a parallel input serial output;
A parallel processor that outputs the second data as serial data from a serial output of the data output register, wherein the number of storage devices in the processor element group is greater than the number of the processor elements, and the processor element group A switching circuit that switches the data input line of the data output register connected to the output terminal of the failed storage device to the output terminal of another storage device when one of the storage devices has a failure. Parallel processor. 26. An information storage means for holding information on whether or not a failure has occurred in each of the storage devices, and the switching circuit has a memory designated as defective by the information of the information holding means. 26. The parallel processor according to claim 25, wherein the data input line of the data output register connected to the input terminal of the device is switched to the output terminal of another storage device. 27. The switching circuit switches a data input line of the data output register, which is connected to an output terminal of a failed storage device, to an output terminal of an adjacent storage device. 26. The parallel processor according to claim 25, wherein the input line is also sequentially switched to the output terminal of the adjacent storage device. 28. An information holding means for holding information on whether or not a failure has occurred in each of the storage devices, and the switching circuit has a memory designated as defective by the information of the information holding means. The data input line of the data output register connected to the output terminal of the device is switched to the output terminal of the adjacent storage device, and the subsequent adjacent data input line is also sequentially switched to the output terminal of the adjacent storage device. 26. The parallel processor of claim 25, wherein the parallel processor is connected. 29. A semiconductor device comprising: a plurality of first elements consisting of serial data, input to a data input register of serial input / parallel output; and a plurality of processor elements comprising a storage device and an arithmetic device for outputting a parallel output of the data input register. To the processor elements in parallel,
The first data is subjected to arithmetic processing by the processor element, and a plurality of second data output in parallel from the processor element as the arithmetic result is input in parallel to a data output register of a parallel input serial output;
A parallel processor that outputs the second data as serial data from a serial output of the data output register, wherein the number of storage devices in the processor element group is greater than the number of the processor elements, and the processor element group If one of the storage devices has a failure, the data input / output line of the arithmetic unit connected to the input / output terminal of the failed storage device is
A first switching circuit for switching connection to an input / output terminal of another storage device; and, when one storage device of the processor element group has a failure, the data connected to the input terminal of the failed storage device. A second switching circuit for switching and connecting a data output line of the input register to an input terminal of another storage device; and an output terminal of the failed storage device when one storage device of the processor element group has a failure. And a third switching circuit for switching and connecting the data input line of the data output register connected to the above to the output terminal of another storage device.