JP2000148527A - Processing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing controller capable of easily executing maintenance even in a fault environment where a controlling CPU or the like in an extended board system can not properly control a program. SOLUTION: An extended board 200 is provided with a CPU 201 and an address decoding circuit 202 which are of the same sorts as a CPU 101 and an address decoding circuit 102 mounted on a control board 100 and a signal line 101a or the like capable of selecting which is used of two CPUs or the like at the time of maintenance or fault diagnosis. The maintenance extended board 200 and the control board 100 respectively include mechanisms for individually selecting and setting up a device to be used for maintenance or fault diagnosis by use of a display signal for monitoring a mutual connection state and a signal from the mechanism for selecting the device to be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing control device in which devices constituting a microcomputer are mounted on a control board, the control board is incorporated in the device, and information processing and devices are controlled by the microcomputer. In particular, the present invention relates to a board configuration having a maintenance function and a failure diagnosis function.

[0002]

2. Description of the Related Art At present, microcomputers are usually incorporated in control devices used in various fields. The microcomputer for controlling the operation is incorporated in a product in the form of a control board, and its use is very widely used from ordinary households to various industries. As described above, control boards equipped with microcomputers used for various products are not only required to realize functions and performances but are also required to reduce the price of the products as much as possible.

On the other hand, from the standpoint of producing these products, the control board equipped with this microcomputer is:
It is essential to improve the maintainability as much as possible.
It is required to be able to execute diagnostics and to be able to download and rewrite an execution program.

[0004] These two requirements impose mutually contradictory conditions on the form of the product. For example, in order to reduce the price of a product according to the former requirement, it is necessary to reduce the number of components mounted on the control board itself as much as possible.
OM, work RAM) and a control target, and a minimum hardware configuration as shown in FIG. 3 is adopted.

FIG. 1 shows a case of a control device configuration, in which a control target 106 is controlled by a control board 100 on which a microcomputer is mounted. Control board 1
Of 00, 101 is a control CPU, 102 is an address decode circuit for generating a selection signal for each device, 103 is an execution program ROM, 104 is a work RAM, and 105 is a control circuit.

Further, 100a is an address bus output from the CPU 101, 100b is a CPU 101,
This is a data bus through which peripheral circuits 03 to 105 exchange data. Reference numerals 102a to 102c denote device select signals for the respective circuits. The signal lines of the buses 100a, 100b and 102a to 102c and the devices 101 to 105 are integrated into a control board.

[0007] Next, when the latter requirement, that is, the maintenance of the control board itself is emphasized, a redundant maintenance realizing function is mounted as far as the price permits. For example, a ROM or a program containing a diagnostics program for maintenance
It is common to add a download RAM to the board or to mount a serial port for maintenance. This is shown in FIG.

In FIG. 1, of the control board 100,
101 is a control CPU; 102 is an address decode circuit for generating a selection signal for each device;
3A is an execution program ROM, and 103B is an R containing a diagnostics program for maintenance.
OM, 104A is a work RAM, 104B is a RAM for downloading a program, 107 is a serial port for maintenance, and 105 is a control circuit.

Further, 100a is an address bus, 100a
b is a data bus, and 102a to 102f are device select signals for the respective circuits. The buses 100a and 100b, the signal lines of 102a to 102f, and the devices 101 to 106 are integrated on the control board.

[0010]

As described above, for a control board incorporating a microcomputer, two conflicting demands are given, namely, a reduction in cost and an emphasis on maintainability. The actual situation is that a circuit configuration in which devices are appropriately selected accordingly is adopted.

In other words, when the price reduction is strongly required, the circuit configuration becomes close to that of FIG. 3, and the price is kept low, but the maintainability is sacrificed accordingly. On the other hand, when the maintenance property is emphasized, the circuit is close to that shown in FIG. 4 and the maintenance property is improved, but the product price is inevitably high.

At present, even in a product having a circuit with an emphasis on maintainability as shown in FIG. 4, if a failure occurs in a CPU or a peripheral circuit on a control board, diagnosis or maintenance is required. Execution (self-running) becomes impossible, and the redundant circuit mounted is wasted at the expense of price.

On the other hand, the present application describes several techniques for simultaneously satisfying the two propositions of lowering the price of a product and improving the maintainability of a product, and greatly improving the environment for product development and maintenance. People have already proposed.

FIG. 5 shows this configuration. In the figure, 1
00 is the entire control board, 101 is the control CPU, 102
Is an address decode circuit for generating a selection signal for each device, 103 is an execution program ROM,
104 is a work RAM, 105 is a control circuit, and 106 is a control target.

100a is an address bus, 100a
b is a data bus, and 102a to 102f are device select signals for the respective circuits.

These buses 100a, 100b, 102a
The signal lines 102 to 102f and the devices 101 to 105 are integrated on the control board.

In FIG. 1, reference numeral 200 denotes a maintenance expansion board added only at the time of maintenance. 203 is a ROM in which a diagnostic program for maintenance is written, and 205 is a serial port for maintenance. The select signal of 102 d is applied to the ROM 203, and the select signal of 102 f is applied to the serial port 205.

Reference numeral 200a denotes an address bus extension having the same meaning as 100a, and 200b denotes a data bus extension having the same meaning as 100b. Also, 200c
Is a display signal for notifying the control board of 100 that the 200 expansion boards have been connected, and in this example, the same potential as GND is given.

In FIG. 1, reference numeral 110 denotes a control board 100
And a connector for connection with the external maintenance expansion board 200. Reference numeral 111 denotes a pull-up resistor provided to reliably input the “H” level when the board 200 is not connected in order to recognize the display signal of 200 c.

In this configuration, the only part applied to the product and shipped is the part indicated by 100,
The part is an extension part connected only at the time of manufacturing test or maintenance. Since only 100 basic parts are incorporated into a normal product, only a connector 110 and a display signal input pull-up resistor 111 are added to the minimum configuration circuit of FIG.

In this configuration, during normal use (when the device is installed), the CPU 101 executes the contents (execution) of the ROM 103 mapped from address 0 in accordance with the address map shown in FIG. Program) to perform control operations as a product. At this time, the display signal 102x is at the “H” level without being asserted,
The output 102a of the decoding circuit 102 is asserted by a space access from address 0.

At the time of maintenance, 200 expansion boards are connected with 100 control boards removed from the equipment. At this time, the display signal level "L" of 200c is transmitted to the 102x input and supplied to the decoding circuit 102. The decoding circuit of 102
When the CPU 101 accesses from address 0, the control is switched so that the signal 102d is asserted instead of asserting 102a. Then, in this state, the address map of the CPU 101 is as shown in FIG.
(B), the execution is started from the address 0, and the ROM 203 is replaced by the ROM 203 instead of the program ROM 103.
Will be accessed.

In the program ROM 203, 2
Diagnostics program using serial port 05 (connecting terminals and development tools, etc.) is written. This control board can perform inspection and test of peripheral circuits including control circuit. become able to.

Thus, 100 control boards and 200
The state of the combination of the maintenance expansion board
This is equivalent to the circuit configuration shown in FIG.

As a result, in the product, the price is reduced by only 100 control boards, and the maintenance is improved by combining with the maintenance extension board of 200, but the price of the product is successfully reduced, and the maintenance of the product is improved. Can be satisfied at the same time.

However, in the case of the system using the expansion board, the device is used both when the device is operated as a product and when the processing operation is performed at the time of maintenance.
Since the control CPU of 101 mounted on the control board is used, if this CPU or a peripheral circuit for operating the CPU fails, the entire device does not function, and the failure in this mode is prevented. However, as before, there still remains a weak point that the cause must be clarified by observing each control signal on the board using an external measuring device and confirming the operation.

Further, in this method, other control parts,
In particular, even when the address decoding circuit 102 is out of order, there is a weak point that it is impossible to execute a test using the maintenance expansion board.

It is an object of the present invention to provide a processing control apparatus which can easily perform maintenance even in a failure environment where a control CPU or the like in an expansion board system cannot perform program control well.

[0029]

SUMMARY OF THE INVENTION According to the present invention, a maintenance expansion board is provided with a test CPU and an address decoding circuit, etc., so that the maintenance expansion board can be used even if the CPU or the address decoding circuit on the control board fails. The system can be maintained and diagnosed using the CPU and address decode circuit of the board, and the device on the control board or the expansion board can be selected and set. The configuration is characterized.

[0030] In a processing control apparatus in which a device for minimizing the microcomputer is mounted on a control board, and a maintenance expansion board that can be connected to the control board with a maintenance board and a device for diagnosing a failure of the control board are mounted. The maintenance expansion board is characterized in that the same CPU as the CPU on the control board is mounted, and a mechanism capable of selecting which of the two CPUs to use at the time of maintenance or failure diagnosis is provided.

The maintenance expansion board includes devices having the same functions as the devices mounted on the control board. For maintenance and failure diagnosis, each functional device is provided on the control board or on the maintenance board. A mechanism is provided for selecting which of the expansion boards to use.

Further, the maintenance expansion board and the control board individually identify devices to be used for maintenance and failure diagnosis according to a display signal for monitoring a mutual connection state and a signal of a mechanism for selecting a device to be used. , And a mechanism for setting the value is provided.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present embodiment, in order to satisfy both requirements of reducing the product price and improving the maintainability of the product, the hardware of the control board itself is reduced to improve the maintainability. A mechanism that can connect a maintenance expansion board is realized with only minimum additional elements. Also, the same CPU and functional devices as those on the control board are mounted on the maintenance expansion board, and faults on the control board can be isolated in various modes.

(First Embodiment) FIG. 1 is a block diagram showing a board according to an embodiment of the present invention. In FIG.
Is an entire control board; 101 is a control CPU; 102 is an address decode circuit for generating a selection signal for each device; 103 is an execution program ROM;
4 is a work RAM, 105 is a control circuit, and 106 is a control target.

100a is an address bus, 100a
b is a data bus, 102a to 102c are device select signals for each functional circuit on the control board,
102d to 102f are device select signals for each functional circuit on the maintenance expansion board.

Buses 100a, 100b, 102a-10
The 2f signal line and the devices 101 to 105 are integrated on the control board.

Reference numeral 200 denotes a maintenance expansion board which is connected to the control board only at the time of maintenance. Reference numeral 201 denotes a maintenance CPU added to the conventional expansion board, and reference numeral 202 denotes an added maintenance address decode circuit. 203 is a maintenance program ROM in which a diagnostic program is written, 204 is a maintenance work RAM, and 205 is a maintenance serial port.

Reference numeral 200a denotes an extension of an address bus having the same meaning as 100a, and 200b denotes an extension of a data bus having the same meaning as 100b. Also, 102x is a display signal for notifying the control board of 100 that 200 expansion boards have been connected.
The same potential as that of GND is given at the portion 00c. Also, 1
01x is a bus release request signal to the control CPU (true at "L" level), and 101a is a bus release notification signal (true at "L" level) for the bus release request.
It is. When the 101x signal is asserted, the control CPU stops using the bus, puts each bus into a floating (high impedance) state, and then asserts a 101a signal indicating that the bus has been released.

Reference numeral 210 denotes a NOT circuit,
A signal 201x is generated by inverting the level of the signal a.
The 201x signal is a bus release request signal of the 201 maintenance CPU.

Reference numeral 220 denotes a bus release request setting switch of the control CPU provided on the 200 board. By operating this switch, it is possible to select whether or not to connect the 101x signal to the GND level of 200c. Thus, when the switch is ON, the 101x signal can be set to “L” level, and when the switch is OFF, the signal can be set to “H” level.

Reference numeral 110 denotes a connector for connecting the control board body to an external maintenance expansion board.
Reference numerals 11 and 112 are pull-up resistors provided so as to reliably input the "H" level when the 200 expansion board is not connected in order to recognize the 101a and 102x signals.

In the configuration of FIG. 1, 102a to 102f
Are output from both the address decode circuit 102 and the maintenance address decode circuit 202, and are connected to each other. At any one time, only one of the decoding circuits is driven. The signal that determines which decoding circuit is valid is the bus release notification signal 101a. When this signal is in a state where the bus is not released (“H” level), the 102 circuit outputs a select signal. When the signal is in a state where the bus is released (“L” level), the 202 signal is used as the select signal. Is output.

The circuit operation of the present embodiment having the above configuration will be described in detail below.

In FIG. 1, 100 control boards and 20
When the maintenance extension board of 0 is disconnected, the operation of the control board of 100 is based on the 102x signal and the 1
Since the 01x signal is fixed at the “H” level by the pull-up resistors 111 and 112, respectively, FIG.
The operation is exactly the same as that of the device for this product. That is,
The control CPU 101 operates, the decode circuit 102 generates a device select signal, and the execution program stored in 103 is executed.

Next, when the control board of 100 and the maintenance expansion board of 200 are connected by the connection connector of 110, the GND level of 200c fixes the 102x signal to the "L" level.
It is displayed to the decoding circuit that 200 expansion boards are connected.

Next, when the control CPU bus release request signal setting switch 220 is in the OFF state, 101x
The control CPU bus release request signal remains at "H" level, and the control CPU 101 executes the bus control and does not release it, so the bus release notification signal of 101a is negated ("H" level). Will remain. In this case, the maintenance CPU bus release request signal of 201a inverted by the NOT circuit of 210 becomes the "L" level and becomes asserted, so that the maintenance CPU of 201 releases the bus. Also, the maintenance address decode circuit 202 to which the same signal is supplied is not driven by setting its select signal output to a high impedance state.

In this state, the address decode circuit 102 asserts the select signals on the maintenance expansion boards 102d to 102f instead of the select signals on the control boards 102a to 102c, thereby obtaining the "control CPU 101". Using the device on the maintenance expansion board, the maintenance process can be performed. This is equivalent to the conventional case of FIG.

Next, when the control board 100 and the maintenance expansion board 200 are connected by the connection connector 110 and the control CPU bus release request signal setting switch 220 is turned ON, the control CP 101x
When the U bus release request signal is at the "L" level, the control CPU 101 releases the bus control and releases it.
The bus release notification signal of 101a is asserted ("L" level).

In this case, the maintenance CPU bus release request signal 201a inverted by the NOT circuit 210 becomes "H" level and becomes negated, so that the maintenance CPU 201 has the right to use the bus. To win. The maintenance address decode circuit 202 to which the same signal is applied also drives the select signal output.

In this state, the CPU executing the maintenance processing is the maintenance CPU 201, and
The address decode circuit 202 is 102a to 102f
It is possible to assert all select signals.
Therefore, it is possible to execute the maintenance “the maintenance CPU 201 uses all the devices in the system”.

This makes it possible to test any device on the control board 100 depending on the program in the maintenance program ROM 203. Further, in this embodiment, even in a failure mode in which the control CPU itself becomes immobile, a peripheral function test of the board can be performed by combining with a maintenance expansion board that is confirmed to perform normal operation.

Therefore, even in a control board in which the control CPU has an improper failure and does not operate, it is possible to easily perform a failure analysis, thereby reducing a huge amount of troubleshooting time generated in such a case. As a result, the conventional problem which still remains can be solved.

(Second Embodiment) FIG. 2 shows a further development of the embodiment shown in FIG. 1, in which consideration has been added for easily realizing a more complicated maintenance mode.

In FIG. 2, a device 206 provided on the maintenance expansion board 200 is a setting element such as a switch group which can be operated by an operator from the outside, and is a setting circuit for setting a maintenance mode to be implemented. Reference numeral 206a denotes a maintenance mode code display signal group for encoding the set maintenance mode and displaying it on the address decode circuits 102 and 202 and the maintenance program ROM circuit 203.

In other respects, except that the bus release request signal setting switch 220 of the control CPU provided in FIG. 1 is omitted and the 101x signal is generated by the 206 circuit instead, the components of FIG. Is exactly the same as

In this embodiment, the CPU circuit, the address
Devices desired to be used for the test, such as a decode circuit, a program ROM circuit, and a work RAM circuit, can be individually selected and set by the setting circuit 206, thereby enabling precise maintenance and failure diagnosis.

In the setting circuit 206, the operator sets a switch to use the function mounted on the control board side or the maintenance board side, and the setting state is encoded by the 206 circuit. , 101x signal and a maintenance mode code of 206a.

The CPU for executing the test is selected according to the level of the bus release request signal of the 101x signal and the level of the bus release notification signal of the 101a. Also, 102 and 20
The code indicating the set maintenance mode is input to each address decode circuit of No. 2 and the maintenance program ROM of 203, and for each mode, for each device, the control board side and the maintenance board side Which of the decoder circuits is selected, which decoder circuit outputs the select signal, and what kind of program to run can be designated.

By adding such a maintenance mode setting circuit 206, the CP
In addition to selecting U, it becomes possible to externally select and set, for each functional device, whether to use the control board side or the maintenance board side for each device. This makes it possible to more smoothly perform a functional test of the control board to be tested and trouble shooting (isolation of a defective portion).

[0060]

As described above, according to the present invention, the maintenance expansion board is provided with the test CPU and the address decode circuit, etc., so that the maintenance of the CPU and the address decode circuit on the control board can be maintained. The maintenance and fault diagnosis of the device can be performed using the CPU and address decode circuit of the expansion board for use, and the device on which of the control board and the expansion board is used can be selected and set. effective.

(1) The same CPU as the control board is mounted on the maintenance expansion board, and the CPU on the maintenance expansion board can be used in addition to the control CPU during the test. Even in the case of a trouble that the CPU on the target control board fails and does not operate, the failed CPU can be separated and the other parts of the test can be tested with the CPU on the maintenance expansion board. This makes it possible to quickly analyze a failure or trouble of the CPU itself, which has been very difficult in the past.

(2) By providing a mechanism for selecting, for each device, whether to use a device on a target control board or a device on a maintenance expansion board at the time of testing, a simple operation is provided. In this way, it is possible to narrow down the defective portion to a specific device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a board showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a board showing another embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional control board emphasizing price.

FIG. 4 is a configuration diagram of a conventional control board emphasizing maintainability.

FIG. 5 is a configuration diagram of a conventional control board and an expansion board.

FIG. 6 is an example of an address map of the CPU 101 in FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 control board 200 maintenance extension board 101, 201 CPU 102, 202 address decoding circuit 103, 203 program ROM 104, 204 work RAM 105 control circuit 205 serial port 220 bus release request signal Setting switch 206: Maintenance mode setting circuit

Claims (3)

[Claims] 1. A processing control device comprising a control board mounted with a device for minimizing a microcomputer, and a device for maintenance and failure diagnosis of the control board mounted on a maintenance expansion board connectable to the control board. In the above, the maintenance expansion board is equipped with the same CPU as the CPU on the control board, and is provided with a mechanism capable of selecting which of the two CPUs to use at the time of maintenance or failure diagnosis. Processing control device. 2. The maintenance expansion board includes devices having the same functions as the devices mounted on the control board. For maintenance and failure diagnosis, each maintenance device is provided on the control board or on the maintenance board. 2. The processing control device according to claim 1, further comprising a mechanism for selecting which one of the extension boards is to be used. 3. The maintenance expansion board and the control board individually identify devices to be used for maintenance and failure diagnosis according to a display signal for monitoring a mutual connection state and a signal of a mechanism for selecting a device to be used. The processing control device according to claim 1, further comprising a mechanism for setting the processing control.