JP2000148110A - 複合画面ｐｃベ―スシステム - Google Patents

複合画面ｐｃベ―スシステム

Info

Publication number
JP2000148110A
JP2000148110A JP11233307A JP23330799A JP2000148110A JP 2000148110 A JP2000148110 A JP 2000148110A JP 11233307 A JP11233307 A JP 11233307A JP 23330799 A JP23330799 A JP 23330799A JP 2000148110 A JP2000148110 A JP 2000148110A
Authority
JP
Japan
Prior art keywords
bus
screen
computer
general
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11233307A
Other languages
English (en)
Japanese (ja)
Inventor
Rahemutoura Karimu
ラヘムトゥラ カリム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Checkout Holdings Ltd
Original Assignee
Checkout Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Checkout Holdings Ltd filed Critical Checkout Holdings Ltd
Publication of JP2000148110A publication Critical patent/JP2000148110A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1438—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using more than one graphics controller

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Digital Computer Display Output (AREA)
JP11233307A 1998-11-16 1999-08-19 複合画面ｐｃベ―スシステム Pending JP2000148110A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9825107.7A GB9825107D0 (en) 1998-11-16 1998-11-16 Multiple screen pc based systems
GB9825107.7 1998-11-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2000302934A Division JP2001166760A (ja) 1998-11-16 2000-10-02 複合画面ｐｃベースシステム

Publications (1)

Publication Number Publication Date
JP2000148110A true JP2000148110A (ja) 2000-05-26

Family

ID=10842539

Family Applications (2)

Application Number Title Priority Date Filing Date
JP11233307A Pending JP2000148110A (ja) 1998-11-16 1999-08-19 複合画面ｐｃベ―スシステム
JP2000302934A Withdrawn JP2001166760A (ja) 1998-11-16 2000-10-02 複合画面ｐｃベースシステム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2000302934A Withdrawn JP2001166760A (ja) 1998-11-16 2000-10-02 複合画面ｐｃベースシステム

Country Status (7)

Country Link
EP (1) EP1131696A1 (https=)
JP (2) JP2000148110A (https=)
KR (1) KR20010093077A (https=)
AU (1) AU5526999A (https=)
GB (2) GB9825107D0 (https=)
HK (1) HK1041060A1 (https=)
WO (1) WO2000029934A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734862B1 (en) * 2000-06-14 2004-05-11 Intel Corporation Memory controller hub
US7116331B1 (en) 2000-08-23 2006-10-03 Intel Corporation Memory controller hub interface
US6859208B1 (en) 2000-09-29 2005-02-22 Intel Corporation Shared translation address caching
GB0107458D0 (en) * 2001-03-24 2001-05-16 Patterson Simon D Method and apparatus
KR100494169B1 (ko) * 2002-11-07 2005-06-08 엘지전자 주식회사 듀얼 모니터의 영상신호 처리장치 및 방법
TWM240594U (en) * 2002-12-06 2004-08-11 Shuttle Inc Improved arrangement of integrated motherboard slot
WO2004064034A1 (en) * 2003-01-09 2004-07-29 Jones Mccue Multi Display Systems Pty Limited Display system
CN100336045C (zh) * 2004-11-19 2007-09-05 威盛电子股份有限公司 多功能芯片组及相关方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5488385A (en) * 1994-03-03 1996-01-30 Trident Microsystems, Inc. Multiple concurrent display system
US5841994A (en) * 1996-06-14 1998-11-24 Texas Instruments Incorporated Portable computer with multiple zoom port interface

Also Published As

Publication number Publication date
JP2001166760A (ja) 2001-06-22
GB2348307A (https=) 2000-09-27
EP1131696A1 (en) 2001-09-12
WO2000029934A1 (en) 2000-05-25
GB2348307B (en) 2003-06-25
KR20010093077A (ko) 2001-10-27
HK1041060A1 (zh) 2002-06-28
GB9825107D0 (en) 1999-01-13
AU5526999A (en) 2000-06-05
GB0010818D0 (en) 2000-06-28

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Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20010731