JP2000138374A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, in which an impurity injection process where SD(source/drain) layers and an LDD(lightly-doped drain) layer formed can be simplified, when impurities are activated through laser annealing after impurities are injected, and a gate electrode can be prevented from being eliminated by irradiation with a laser beam. SOLUTION: A semiconductor device is equipped with a substrate 1, a thin- film semiconductor layer, a gate SiO2 film 5, a gate electrode 7, an SiO2 sidewall 8 formed on the sidewall of the gate electrode 7, and a cap SiO2 film 6 formed covering them, wherein the optical thickness of the cap SiO2 film 6 formed on the gate electrode 7 is set so as to make the cap SiO2 film 6 high in reflectivity to a laser beam used for activation of impurities, the total sum of the optical thicknesses of the gate SiO2 film 5 and the cap SiO2 film 6 located on a source 3 and a drain 4 is set so as to make the films 5 and 6 low in reflectivity of the laser, and the optical thickness of the cap SiO2 film 6 is set to make the film 6 higher in reflectivity of the laser on the SiO2 sidewall 8 than that on the source 3 and the drain 4 and is set to be the required thickness for the formation of LDD layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device formed by an impurity activation method using a laser suitable for a planar p-Si TFT and a method of manufacturing the same.

[0002]

2. Description of the Related Art Manufacturing of a conventional planar p-Si TFT
The method will be described with reference to FIGS.
Conventionally, an LDD (low concentration drain) region of a TFT and an SDD
To form the (source / drain) region,
Film semiconductor layer 10 and gate SiO _TwoThe film 5 and the gate electrode 7
After the formation, as shown in FIG.
LDD layer formation by ion implantation or ion doping equipment
Impurity is implanted, and then as shown in FIG.
Then, two times of ion implantation for forming an SD layer are performed.
Impurity is implanted by ion implantation.
As shown, furnace annealing (FIG. 12 (a))
Activation of impurities by laser annealing (FIG. 12 (b))
The method of doing is used.

[0003]

However, the above-described conventional impurity implantation and activation methods have the following problems.

The first problem is that, at the time of impurity implantation,
Since the concentration of impurities to be implanted is different between the SD layer and the LDD layer, at least two times of impurity implantation is required to form the SD layer and the LDD layer, which takes a long time in the impurity implantation process. is there.

A second problem is that when furnace annealing is used for activating the impurity-implanted region, it is necessary to anneal at a high temperature of 550 ° C. or higher for activating the impurities, particularly for activating the phosphorus-doped layer. In addition, since the temperature rise time and the temperature fall time are long, the glass used as the substrate is distorted or the throughput is lowered.

A third problem is that when laser annealing is used to activate the impurity-implanted region, the SD
A certain irradiation energy is required to activate the layer, but since the gate electrode is also directly irradiated with laser light,
That is, the gate electrode is damaged and disappears.

The present invention has been made in view of the above problems, and a main object of the present invention is to perform impurity implantation for forming an SD layer and an LDD layer when activating an impurity by laser annealing after the impurity implantation. An object of the present invention is to provide a semiconductor device capable of simplifying a process and preventing a gate electrode from being lost due to laser irradiation, and a method for manufacturing the same.

[0008]

According to a first aspect of the present invention, there is provided an active region formed by irradiating an impurity-implanted region with a laser through an insulating film to activate an impurity. In the semiconductor device having a region, the insulating film is set to have an optical thickness such that the reflectance of the laser is reduced in the activation region, and a predetermined portion of the activation region other than the activation region that is damaged by laser absorption. In the region, the optical thickness is set so as to increase the reflectance of the laser.

According to a second aspect of the present invention, there is provided a source / drain region and an LDD (low-concentration drain) region formed by irradiating a laser to an impurity implantation region via an insulating film to activate the impurity. In the semiconductor device having: the insulating film is set to have an optical thickness such that the laser reflectance is reduced in the source / drain region, and the laser reflectance is reduced in the source / drain region in the LDD region. The optical thickness is set to be larger than the optical thickness required to transmit the laser by an amount necessary for forming the LDD layer, and in a predetermined region other than the source / drain and the LDD region, which is damaged by laser absorption, The optical thickness is set so that the reflectivity of the laser increases.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to a third aspect of the present invention, wherein a laser is irradiated through an insulating film to activate an impurity-implanted region to form an active region. The insulating film is formed in a plurality of times so that the reflectivity of the laser is small in the activated region, and the reflectivity of the laser is increased in the region other than the activated region and damaged by laser absorption. The optical thickness of the film is changed according to the region.

In the present invention, the optical thickness of the insulating film on the activation region is d, the optical thickness of the insulating film on a predetermined region other than the activation region is D, Assuming that the wavelength of the laser is λ, at least the relationship of 4d ≒ (2m + 1) λ [m is an integer] is satisfied on the activation region, and 2D ≒ on a predetermined region other than the activation region.
It is preferable that d and D are set so as to satisfy the relationship of mλ.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the semiconductor device according to the present invention, a thin film semiconductor layer, a gate SiO ₂ film (1 in FIG. 1) and a gate electrode (1 in FIG. 1) are formed on a substrate (1 in FIG. 1). 1) and SiO formed on the side wall of the gate electrode
_{It has two} sidewalls (8 in FIG. 1) and a cap SiO ₂ film (6 in FIG. 1) formed so as to cover them, and the optical thickness of the cap SiO ₂ film on the gate electrode depends on the activation of impurities. The source (3 in FIG. 1) / drain (FIG. 1)
Of the 4), the total optical thickness of the gate SiO ₂ film and the cap SiO ₂ film is set so that the laser reflectance decreases, the cap on the SiO ₂ sidewalls SiO ₂
The optical thickness of the film is set to a thickness necessary for forming the LDD layer, with a larger laser reflectance than on the source / drain.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] A planar p-Si TFT according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view for explaining the structure of a planar p-SiTFT according to the first embodiment. FIGS. 2 and 3 are views for schematically explaining a manufacturing process of the planar p-SiTFT. FIG. FIG.
FIG. 5 is a diagram showing the reflectance of the laser on the gate electrode and the SD layer with respect to the thickness of SiO _2. FIGS. 5 to 7 show cap SiO ₂ when the gate SiO ₂ film is set to a predetermined thickness. FIG. 4 is a diagram showing a critical intensity of disappearance of a gate electrode of a laser beam and a critical intensity of activation of an SD layer with respect to a film thickness. 8 and 9 are diagrams showing the critical intensity of the gate electrode disappearance and the SD layer activation critical intensity of the laser light with respect to the thickness of the gate SiO ₂ film when the cap SiO ₂ film is set to a predetermined thickness. is there.

First, the planar type p-SiT of this embodiment
The method of manufacturing the FT will be described with reference to FIGS. 2 and 3. In the TFT of the present embodiment, after forming a p-Si layer serving as an active layer on the substrate 1, a gate SiO ₂ film 5 is formed on the substrate 1.
It is deposited to a thickness of 8 nm to form an island. Thereafter, a gate electrode 7 made of WSi is formed on the gate SiO ₂ film 5, and a source 3 and a drain 4 are formed by performing ion implantation for forming an SD layer by ion implantation / ion doping (FIG. 2A). reference).

Next, after forming SiO ₂ sidewalls 8 on the side walls of the gate electrode 7 (see FIG. 2B), FIG.
As shown in (a), the cap SiO ₂ film 6 is formed with a thickness of, for example, 400 nm. Then, as shown in FIG. 3B, an excimer laser is irradiated from above the cap SiO ₂ film 6 to activate the implanted impurities.

At the time of activating the impurities, in this embodiment, as shown in FIG. 1, the film thickness of SiO ₂ is y just above the gate electrode 7, and Si is just above the source 3 and the drain 4.
The film thickness of O ₂ is x + y as is apparent from the figure. When a TFT having such a structure is irradiated with an excimer laser, the reflectance in each region is determined by the thickness of the SiO ₂ layer, the optical characteristics of the layer immediately below, the laser wavelength, and the like. Therefore, by designing a TFT having a structure in which the SiO ₂ film thicknesses x and y have a predetermined film thickness, the effective incident intensity of the laser is reduced at the gate electrode 7 portion and the effective incident intensity at the source 3 / drain 4 portion. It becomes possible to raise it.

Further, the right under SiO ₂ sidewalls 8, by an optical film thickness of the SiO ₂ sidewalls 8 as viewed from the normal direction of the substrate 1 to a predetermined value, it is possible to lower the laser incident intensity Therefore, the activation rate is low, that is, the resistance can be made high, and a region corresponding to a generally used LDD structure can be formed. Usually, in order to form an LDD structure, two impurity implantation processes of a high concentration and a low concentration are required. However, in the structure of this embodiment, only one implantation under a high concentration condition is performed and SiO _{2 is} implanted. By changing the reflectivity of the laser caused by the film thickness, a structure corresponding to the LDD structure can be formed.

The effect of this embodiment will be specifically described. In the case where activation is performed by directly irradiating a XeCl laser (wavelength: 308 nm) without forming the cap SiO ₂ film 6, SD
Activation of the layer requires an irradiation intensity of 175 mJ / cm ² or more. On the other hand, the gate electrode 7 made of WSi is 140 m
It has been found that it disappears at an irradiation intensity of J / cm ² or more.

Here, as shown in FIG.
When the O ₂ film 6 is formed to have a thickness of, for example, 400 nm (that is, y = 400 nm), the reflectance of the laser immediately above the gate electrode 7 is 51.4% as shown by a dashed line in FIG.
On the other hand, immediately above the SD layer, the total SiO 2
The thickness of the _two films is 458 nm (that is, x + y = 458n).
m), and its reflectivity is also 30.2% from FIG.

The activation laser intensity of the above-mentioned SD layer 175
mJ / cm ^2, considering the reflectivity for the SD layer activation, 175 ÷ (1-0.302) = 250mJ / cm 2
Is required, and at this time, the effective intensity applied to the gate electrode is 250 × (1−0.514) = 122 mJ.
/ cm ² , which is lower than the disappearance irradiation intensity of the gate electrode 7 made of WSi of 140 mJ / cm ² . Therefore, the SD layer can be activated without damaging the gate electrode 7. The critical laser intensity at which the gate electrode 7 disappears is 140 ° (1−0.514) = 2
Since it is 88 mJ / cm ² , it is possible to secure a margin of the laser irradiation intensity.

Thus, the SD layer can be activated by laser annealing while protecting the gate electrode 7 from damage due to laser irradiation. Further, with such a configuration, the gate electrode 7 is protected, so that the margin of the laser intensity can be increased.

Next, the gate SiO ₂ film 5 and the cap S
A method for determining the thickness of the iO ₂ film 6 will be described with reference to FIGS. 5 to 7 show that the thickness of the gate SiO ₂ film 5 is 30 nm and 50 n, respectively.
FIGS. 8 and 9 illustrate the case where the thickness of the cap SiO ₂ film 6 is fixed to 400 nm and 110 nm, respectively.

The waveforms shown by solid lines in FIGS. 5 to 7 show the critical strength required for activating the SD layer when the thickness of the cap SiO ₂ film 6 is changed, and are shown by broken lines. The waveform shows the critical intensity at which WSi (gate electrode 7) disappears. The shaded areas in FIGS. 5 to 7 indicate the broken-line W
This is a region in which the activation of the SD layer can be performed while preventing the loss of WSi, in an intensity region equal to or lower than the critical intensity of the disappearance of Si and equal to or higher than the critical intensity of the activation of the SD layer indicated by the solid line.

Similarly, the waveform shown by the solid line in FIGS. 8 and 9 shows the SD when the thickness of the gate SiO ₂ film 5 is changed.
The critical strength required for the layer to be activated is shown, and the dashed waveform indicates the critical strength at which WSi disappears.
The shaded region is less than WSi vanishing critical strength and S
This is a region in which the intensity of the D layer activation critical intensity or higher can activate the SD layer while preventing the loss of WSi in the same manner.

As shown in FIGS. 5 to 9, the thicknesses of the gate SiO ₂ film 5 and the cap SiO ₂ film 6 are changed within a range satisfying both the gate electrode disappearance critical strength and the SD layer activation critical strength. Is possible. As a result, the design range of the planar p-Si TFT shown in FIG. 1 can be given a degree of freedom.

Embodiment 2 Next, a planar p-Si TFT according to a second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a diagram illustrating the reflectance of the laser immediately above the SD layer and the gate electrode of the planar p-Si TFT according to the present embodiment.

In this embodiment, unlike the first embodiment, when the wavelength of the laser is changed, that is, when KrF
This is a case where a laser (λ = 248 nm) is used. In FIG. 10, the curve shown by the solid line indicates the reflectivity immediately above the SD layer, and the broken line indicates the reflectivity immediately above the gate electrode 7. When the thicknesses of the gate SiO ₂ film 5 and the cap SiO ₂ film 6 are x = 50 nm and y = 400 nm,
The reflectance of the laser immediately above the gate electrode 7 is 48.9.
%, And the reflectivity of the laser immediately above the SD layer is 40.9%.

Therefore, similarly to the first embodiment, the laser reflectance can be reduced on the gate electrode 7 and increased on the SD layer, and the efficiency of the SD layer can be efficiently reduced while preventing the disappearance of the gate electrode. Impurities can be activated.

In the present invention, an excimer laser and a KrF laser have been described as examples of laser types.
The present invention is not limited to the above, and a combination such that the reflectance of the laser is large on the gate electrode and the reflectance is small on the SD layer in relation to the thickness of the gate oxide film and the cap oxide film. Should be fine.

[0031]

As described above, according to the present invention,
It is possible to efficiently activate the impurities implanted into the source / drain regions without damaging the gate electrode, and to improve a process margin for laser activation.

The effect of the present invention is that in the present invention, when annealing with a laser, by setting the thicknesses of the gate oxide film and the cap oxide film to predetermined values, the reflectivity of the laser on the gate electrode is increased and the source / drain Above, the reflectance of the laser can be reduced, and therefore, even if the laser having the intensity required for activating the impurity in the SD layer is irradiated, the gate electrode can be prevented from disappearing. Further, since the gate electrode is protected, the margin of the critical laser intensity at which the gate electrode disappears can be increased.

Further, according to the present invention, since a low dose process for forming an LDD can be omitted, there is an effect that the process can be saved.

The reason is that the laser irradiation intensity is lower immediately below the sidewalls, so that the impurity activation rate is lower than in the SD region, and a high resistance region is formed. Therefore, the conventional LDD structure requires two impurity implantation steps, but in the present invention, the same performance can be obtained only by one impurity implantation step.

[Brief description of the drawings]

FIG. 1 is a planer type p-type according to a first embodiment of the present invention.
It is sectional drawing which shows the structure of SiTFT.

FIG. 2 is a planer type p-SiTF according to a first embodiment.
FIG. 5 is a process cross-sectional view illustrating a method of manufacturing T.

FIG. 3 is a planer p-SiTF according to a first embodiment.
FIG. 5 is a process cross-sectional view illustrating a method of manufacturing T.

FIG. 4 is a planer type p-SiTF according to a first embodiment.
FIG. 4 is a diagram showing the reflectance of a laser just above the SD layer and the gate electrode of T.

FIG. 5 is a planer p-SiTF according to a first embodiment.
FIG. 4 is a diagram showing a relationship between a critical intensity of disappearance of WSi and a critical intensity of activation of an SD layer with respect to a film thickness of a cap SiO ₂ of T, in which a gate oxide film thickness is 30 nm.

FIG. 6 is a planer type p-SiTF according to a first embodiment.
FIG. 4 is a diagram showing the relationship between the critical strength of disappearance of WSi and the critical strength of activation of the SD layer with respect to the film thickness of the cap SiO ₂ of T, and explains the case where the gate oxide film thickness is 50 nm.

FIG. 7 is a planer p-SiTF according to a first embodiment.
FIG. 4 is a diagram showing a relationship between a critical intensity of disappearance of WSi and a critical intensity of activation of an SD layer with respect to a film thickness of a cap SiO ₂ of T, and explains a case where a gate oxide film thickness is 70 nm.

FIG. 8 is a planer p-SiTF according to a first embodiment.
FIG. 9 is a diagram showing the relationship between the critical strength of disappearance of WSi and the critical strength of activation of the SD layer with respect to the thickness of the gate SiO ₂ of T,
The case where the thickness of the cap SiO ₂ is 400 nm will be described.

FIG. 9 is a planer p-SiTF according to a first embodiment.
FIG. 9 is a diagram showing the relationship between the critical strength of disappearance of WSi and the critical strength of activation of the SD layer with respect to the thickness of the gate SiO ₂ of T,
The case where the thickness of the cap SiO ₂ is set to 110 nm will be described.

FIG. 10 is a planer p-SiT according to a second embodiment.
It is a figure which shows the reflectance of the laser just above the SD layer of FT, and just above the gate.

FIG. 11 is a process sectional view illustrating a method for manufacturing a conventional planar p-Si TFT.

FIG. 12 is a process sectional view illustrating a method for manufacturing a conventional planar p-Si TFT.

[Explanation of symbols]

1 substrate 2 lower active region 3 source 4 drain 5 a gate SiO ₂ film 6 cap SiO ₂ film 7 gate electrode 8 SiO ₂ sidewalls 10 annealing furnace 11 wafers

Claims (12)

[Claims] 1. A semiconductor device having an active region formed by irradiating a laser to an impurity-implanted region through an insulating film and activating the impurity, wherein the insulating film is formed of a laser in the activated region. The reflectance is set to an optical thickness to be reduced, other than the activation area, in a predetermined area damaged by laser absorption, the optical thickness is set to an increased laser reflectance. A semiconductor device characterized by the above-mentioned. 2. A semiconductor device having a source / drain region and an LDD (low-concentration drain) region formed by irradiating a laser to an impurity implantation region via an insulating film and activating the impurity, wherein the insulating film is In the source / drain regions,
The laser thickness is set to an optical thickness that reduces the reflectance of the laser. In the LDD region, the reflectance of the laser is higher than that of the source / drain regions, and the laser transmits the laser by an amount necessary for forming the LDD layer. A thickness other than the source / drain and the LDD region,
A semiconductor device, wherein a predetermined region damaged by laser absorption is set to have an optical thickness at which the laser reflectance increases. 3. The optical thickness of the insulating film on the activated region is d, the optical thickness of the insulating film on a predetermined region other than the activated region is D, and the wavelength of the laser is Where λ is at least 4d を (2m + 1) λ (m is an integer) on the activation region, and 2D ≒ mλ on a predetermined region other than the activation region. The semiconductor device according to claim 1, wherein d and D are set. 4. A method of manufacturing a semiconductor device in which an active region is formed by irradiating a laser through an insulating film to activate an impurity-implanted region, wherein the active region has a low laser reflectance. In an area other than the activation area, which is damaged by laser absorption, the insulating film is formed in a plurality of times so that the reflectance of the laser is increased, and the optical thickness of the insulating film is set in the area. A method for manufacturing a semiconductor device, wherein the method is changed in accordance with the method. 5. An optical thickness of the insulating film on the activation region is d, an optical thickness of the insulating film on a predetermined region other than the activation region is D, and a wavelength of the laser is Where λ is at least 4d を (2m + 1) λ (m is an integer) on the activation region, and 2D ≒ mλ on a predetermined region other than the activation region. 5. The method according to claim 4, wherein d and D are set. 6. A thin film semiconductor except a portion immediately below the gate electrode, wherein a thin film semiconductor layer, a gate insulating film, and a gate electrode are formed on a substrate, and a laser is irradiated through a cap insulating film formed so as to cover these layers. Planar type TFT in which a source / drain is formed by activating a predetermined region of a layer
In the above, the optical thickness of the cap insulating film on the gate electrode is set so as to increase the reflectance of the laser, and the gate insulating film on a predetermined region of the thin film semiconductor layer serving as a source / drain A total optical thickness of a film and the cap insulating film is set so that the reflectance of the laser is reduced.
T. 7. A laser beam is radiated through a cap insulating film formed on a substrate, comprising a thin film semiconductor layer, a gate insulating film, a gate electrode, and a side wall formed on a side wall of the gate electrode. In a planar type TFT in which a source / drain is formed by activating a predetermined region of the thin film semiconductor layer except immediately below the gate electrode, the optical thickness of the cap insulating film on the gate electrode is The total optical thickness of the gate insulating film and the cap insulating film on a predetermined region of the thin film semiconductor layer serving as a source / drain is set so as to increase the reflectance of the laser. And the optical thickness of the cap insulating film on the side wall is larger than that on the source / drain when viewed from the normal direction of the substrate. Planar type TFT reflectance is large, LDD is set to (lightly doped drain) layer is formed, it is characterized. 8. The planar type TFT according to claim 7, wherein said source / drain layers and said LDD layers have substantially the same impurity concentration. 9. When the optical thickness of the gate insulating film is d ₁ , the optical thickness of the cap insulating film is d ₂ , and the wavelength of the laser beam is λ, at least 2d on the gate electrode. ₂ {mλ (m is an integer), and 4 (d ₁ + d ₂ )} (2
9. The planar TFT according to claim 6, wherein d ₁ and d ₂ are set so as to satisfy a relationship of (m + 1) λ. 10. The planarizer according to claim 6, wherein the gate insulating film, the cap insulating layer, and the side wall portion are made of SiO ₂ , and the gate electrode includes at least a WSi layer. Type TFT. 11. A step of forming a thin film semiconductor layer, a gate insulating film and a gate electrode on a substrate, and a step of forming a source / drain by injecting impurities into the thin film semiconductor layer. (C) forming a side wall portion made of an insulating member on the side wall of the gate electrode; and (d) forming a cap insulating film on the entire substrate so as to cover the thin film semiconductor layer, the gate insulating film, and the gate electrode. And (e) irradiating a laser from above the substrate via the cap insulating film to activate the impurities, wherein the optical thickness of the gate insulating film is d ₁ , When the optical thickness of the cap insulating film is d ₂ and the wavelength of the laser is λ, at least on the gate electrode, a relationship of 2d ₂ ≒ mλ (m is an integer) is satisfied, and on the source / drain region Then _{(D 1 + d 2) ≒} (2
m + ₁₎ d 1 and d ₂ so as to satisfy the relation of λ is set, the production method of the planar type TFT, characterized in that. 12. The method of claim 11, wherein the gate insulating film, the cap insulating layer, and the side wall are made of SiO ₂ , and the gate electrode includes at least a WSi layer.