JP2000134989A - Motor controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motor controller which is completely free of adjustment and besides is inexpensive, by essentially solving the conventional theme related to the gain adjustment of a current error amplifier. SOLUTION: This motor controller is equipped with a line current detection means, a line current command generation means, a current control means 14, a group of main circuit power elements. Then, the current control means 14 is composed of a comparison means which compares the magnitudes of each line current measurement result and each current command, a timing generation means 34, and a logical circuit which outputs a signal to turn on or turn off a main circuit switching power element in the direction of reducing the difference between each line current measurement result and each line current command, based on the timing signal and the output from the comparison circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control device used in the industrial field and the information equipment field.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a conventional motor control device. In general, a servomotor used in the industrial field and the like is controlled by a control device having such a configuration. However, a motor in the information device field is also controlled by a similar control device.

Hereinafter, the conventional motor control device shown in FIG. 10 will be described. 1 is a three-phase electric motor.

[0006] Reference numeral 6 denotes a line current detecting means, which is a three-phase motor 1.
, And the remaining one line current is obtained by taking the sum of the two detected line currents and inverting the sign. The first line current measurement result iFU and the second line current measurement result iF
V, and output as the third line current measurement result iFW. The line current detecting means 6 detects three line currents of the three-phase motor 1 and generates the first line current measurement result iFU, the second line current measurement result iFV, and the third line current measurement result iFW. May be output.

Reference numeral 12 denotes a line current command generating means, which sets a fundamental frequency f and an effective current value ip of a three-phase AC current waveform supplied to the three-phase motor 1, and generates a line current command based on these information. The means 12 outputs a first line current command iTU, a second line current command iTV, and a third line current command iTW for commanding each line current to flow into each phase drive winding of the electric motor 1.

Reference numeral 13 denotes a current control means, which is a first line current command iTU, a second line current command iTV, a third line current command iTW, and a line current detection means 6 which are outputs of the line current command generation means 12. The first line current measurement result iFU which is the output of
Second line current measurement result iFV, third line current measurement result i
FW, the first line current command iTU, the first line current measurement result iFU, the second line current command iTV, the second line current measurement result iFV, and the third line current command iTW
And the third line current measurement results iFW are generated as much as possible, and the switching command signals PU, PV, PW are generated.

Reference numeral 4 denotes a main circuit power element group, which is a switching command signal PU, P which is an output of the current control means 13.
The power of the main circuit DC power supply 3 is supplied to the three-phase motor 1 based on V and PW.

In the conventional motor control device having such a configuration, switching is performed by the current control means 13 so that a line current according to the line current command signal output from the line current command generation means 12 flows through the three-phase motor 1. A command signal is generated to supply the power of the main circuit DC power supply 3 to the three-phase motor 1. As a result, torque is generated in the three-phase motor 1 and the three-phase motor 1
Can be controlled.

The conventional motor control device controls the line current flowing through the three-phase motor 1 according to the line current command by the above operation.

Here, the above-described current control means 13
As shown in FIG. 1, the first, second, and third line current commands iT
Subtraction means for subtracting U, iTV, iTW and first, second, and third line current measurement results iFU, iFV, iFW, and outputting first, second, and third line current deviations iEU, iEV, iEW. 41, 42, and 43 and the first, second, and third line current deviations iEU, iEV, and iEW are input and the voltage command signal V
First, second, and third current error amplifiers 44, 45, and 46 for outputting U, VV, and VW, a triangular wave generating means 50 for outputting a triangular wave signal SC that is a PWM carrier signal, and voltage command signals VU and VV. , VW to the non-inverting input terminal and the triangular wave signal SC to the inverting input terminal, compare the voltage command signals VU, VV, VW with the triangular wave signal SC, and compare the result with the switching command signals PU, PV, The first, second, and third comparators 47, 48, and 49 output as PW.

The current control means 13 constructed as described above
Amplifies each current deviation, which is the difference between each line current command and each line current measurement result, by a current error amplifier, and compares the resulting voltage command with a PWM carrier signal to convert the switching command signals PU, PV, and PW. Operate to output.

Here, in the current control means 13, as the current error amplifiers 44, 45 and 46, as shown in the figure, a PI type (proportional / integral type) amplifier having a gain characteristic obtained by (Equation 1) is used. Generally, it is done.

G = Kp (1 + 1 / TiS) (Equation 1)

In a control system including such a PI type error amplifier, the control response can be enhanced as the gain of the error amplifier is increased, and the steady-state error can be reduced to almost zero by providing an integral term. it can.

FIG. 12 shows the internal operation waveforms of the current control device 13 and how the line current flowing through the three-phase motor 1 is controlled.

[0016]

However, in the conventional motor control device described above, the phase delay due to the electric time constant of the three-phase motor, the phase delay of the current error amplifier, the operation delay of the power element, and the three-phase PWM signal Since there is a dead time delay or the like at the time of occurrence of the oscillation, if the gain of the current error amplifier is too large, an oscillation phenomenon occurs.
Therefore, the gain of the current error amplifier is generally set to a value as large as possible within a range not oscillating. In designing, the characteristics of the three-phase motor, the line current detection means, the current control means, and the main circuit power element group are used. It is determined by considering the loop transfer function of the current control loop. That is, it is necessary to suppress the gain so that the oscillation phenomenon does not occur even in the worst case in consideration of the manufacturing variation of these characteristics and the temperature characteristics.

For the above-described reasons, in the conventional motor control device, there is a limit in increasing the current gain, so that the response to the current command cannot be improved, and the motor control device is outside the current control system. There is a problem that the responsiveness of the speed control system and the position control system cannot be enhanced.

In the industrial field, it is desired to increase the productivity by shortening the tact time of machines such as machine tools and robots, but this involves positioning servo motors mounted on these machines. It is necessary to increase responsiveness.

In the field of information equipment, a copy machine, a printer, a hard disk, a DVD, a CD-
It is desired to increase the speed of accessing information in a ROM or the like. However, it is necessary to improve the control response of a motor mounted on an information device.

However, as described above, in the conventional motor control device, it is difficult to increase the responsiveness of the entire control system because the gain of the current error amplifier cannot be sufficiently increased, and these problems cannot be solved.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a motor control device having extremely excellent response to a command.

[0022]

In order to solve the above-mentioned problems, a first electric motor control device according to the present invention measures a line current flowing from each line to a three-phase electric motor directly or indirectly. A line current detection unit that outputs one line current measurement result, a second line current measurement result, and a third line current measurement result; and a first line command that instructs a line current to flow into the three-phase motor from each of the lines. A line current command generating unit that outputs a line current command, a second line current command, and a third line current command,
Compare the magnitude relationship between the first line current command and the first line current measurement result, the first line current comparison result when the first line current measurement result is greater than the first line current command When the first line current measurement result is smaller than the first line current command, the first comparison means to reduce the first line current comparison result, and the second line current command Compare the magnitude relationship with the second line current measurement result, if the second line current measurement result is larger than the second line current command, the second line current comparison result is large, the second line A second comparing means for reducing the second line current comparison result when the current measurement result is smaller than the second line current command; and the third line current command and the third line current measurement result If the third line current measurement result is larger than the third line current command, the third line current comparison A third comparison means for reducing the third line current comparison result when the third line current measurement result is smaller than the third line current command; a main circuit DC power supply; A first main circuit switching power element connected to a positive terminal of the circuit DC power supply and supplying a first line current to the three-phase motor; and a second main circuit switching power element connected to the plus terminal of the main circuit DC power supply and connected to the three-phase motor. A second main circuit switching power element that supplies a line current of, a third main circuit switching power element that is connected to a positive terminal of the main circuit DC power supply and supplies a third line current to the three-phase motor, A fourth main circuit switching power element connected to a negative terminal of the main circuit DC power supply and supplying a first line current to the three-phase motor; and a three-phase motor connected to a negative terminal of the main circuit DC power supply. second A fifth main circuit switching power element that supplies a line current, a sixth main circuit switching power element that is connected to a minus terminal of the main circuit DC power supply, and supplies a third line current to the three-phase motor; A main circuit power element group constituted by a reflux diode connected in parallel to each main circuit switching power element and having a three-phase bridge configuration, the first line current comparison result, the second line current comparison result, and a third A logic circuit that receives a line current comparison result and generates a switching command signal for the first, second, third, fourth, fifth, and sixth main circuit switching power elements, and a periodic state update timing. The logic circuit further includes a timing generation unit for giving the first line current comparison result small, the second line current comparison result large, and the third line current comparison result at the update timing. In a large case, the second, third, and fourth main circuit switching power elements are commanded to be in an off state, and the first, fifth, and sixth main circuit switching power elements are commanded to be in an on state, and If the second line current comparison result becomes smaller before the third line current comparison result becomes smaller, the second line current comparison result from that time until the third line current comparison result becomes smaller The fifth main circuit switching power element is instructed to be in an off state, the second main circuit switching power element is instructed to be in an on state, and the third line current comparison result is reduced from the point at which it becomes small until the next update timing. Command the first, second, and third main circuit switching power elements to an off state, and command the fourth, fifth, and sixth main circuit switching power elements to an on state,
If the third line current comparison result becomes smaller before the second line current comparison result becomes smaller, the sixth line from that time to the second line current comparison result becomes smaller. Command the off state to the main circuit switching power element of the second circuit, and instruct the on state to the third main circuit switching power element. The first, second, and third main circuit switching power elements are commanded to be in an off state, the fourth, fifth, and sixth main circuit switching power elements are configured to be commanded to be in an on state, and the update timing When the first line current comparison result is large, the second line current comparison result is small, and the third line current comparison result is large, the first, third, and fifth main circuit switching power elements are turned off. Command the status, and switch the second, fourth, and sixth main circuits. If the third line current comparison result becomes smaller before the first line current comparison result becomes smaller, the first line current comparison result is obtained from that point in time. Until the value becomes small, the sixth main circuit switching power element is instructed to be in the off state, the third main circuit switching power element is instructed to be in the on state, and the first line current comparison result is small. From the time to the next update timing, the first, second, and third main circuit switching power elements are commanded to be in the off state, and the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state. And also
If the first line current comparison result becomes smaller before the third line current comparison result becomes smaller, the fourth line current from that point in time until the third line current comparison result becomes smaller is obtained. Command the off-state to the main circuit switching power element of the first, and instruct the on-state to the first main circuit switching power element, from the time when the third line current comparison result becomes small until the next update timing. The first, second, and third main circuit switching power elements are commanded to be in an off state, the fourth, fifth, and sixth main circuit switching power elements are configured to be commanded to be in an on state, and the update timing When the first line current comparison result is large, the second line current comparison result is large, and the third line current comparison result is small, the first, second, and sixth main circuit switching power elements are turned off. Command the status, and switch the third, fourth, and fifth main circuits. If the first line current comparison result becomes smaller before the second line current comparison result becomes smaller, the second line current comparison result is obtained from that point. Until is reduced, the fourth main circuit switching power element commanded off state, the first main circuit switching power element commanded on state, the second line current comparison result was small From the time to the next update timing, the first, second, and third main circuit switching power elements are commanded to be in the off state, and the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state. And also
If the second line current comparison result becomes smaller before the first line current comparison result becomes smaller, the fifth line from that time to the first line current comparison result becomes smaller. Command the off-state to the main circuit switching power element of the second circuit, and instruct the on-state to the second main circuit switching power element. The first, second, and third main circuit switching power elements are commanded to be in an off state, the fourth, fifth, and sixth main circuit switching power elements are configured to be commanded to be in an on state, and the update timing When the first line current comparison result is large, the second line current comparison result is small, and the third line current comparison result is small, the first, fifth, and sixth main circuit switching power elements are turned off. Command the status, and switch the second, third, and fourth main circuit switches. If the second line current comparison result becomes large before the third line current comparison result becomes large, the third line current comparison result is obtained from that point. Until the value becomes large, the second main circuit switching power element is instructed to be in an off state, the fifth main circuit switching power element is instructed to be in an on state, and the third line current comparison result is large. From the time to the next update timing, the first, second, and third main circuit switching power elements are commanded to be in the off state, and the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state. And also
If the third line current comparison result becomes large before the second line current comparison result becomes large, the third line current comparison result from that time to the second line current comparison result becomes large, Command the off-state to the main circuit switching power element of the second circuit, and instruct the on-state to the sixth main circuit switching power element, and perform the first time from when the second line current comparison result becomes large until the next update timing. The first, second, and third main circuit switching power elements are commanded to be in an off state, the fourth, fifth, and sixth main circuit switching power elements are configured to be commanded to be in an on state, and the update timing When the first line current comparison result is small, the second line current comparison result is large, and the third line current comparison result is small, the second, fourth, and sixth main circuit switching power elements are turned off. Command the status, and switch the first, third, and fifth main circuits. If the third line current comparison result becomes large before the first line current comparison result becomes large, the first line current comparison result is obtained from that point in time. Until the value becomes large, the third main circuit switching power element is instructed to be in the off state, the sixth main circuit switching power element is instructed to be in the on state, and the first line current comparison result is large. From the time to the next update timing, the first, second, and third main circuit switching power elements are commanded to be in the off state, and the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state. And also
If the first line current comparison result becomes large before the third line current comparison result becomes large, the first line current comparison result from that time to the third line current comparison result becomes large, Command the off-state to the main circuit switching power element and command the on-state to the fourth main circuit switching power element, and wait for the next update timing from the time when the third line current comparison result becomes large. The first, second, and third main circuit switching power elements are commanded to be in an off state, the fourth, fifth, and sixth main circuit switching power elements are configured to be commanded to be in an on state, and the update timing When the first line current comparison result is small, the second line current comparison result is small and the third line current comparison result is large, the third, fourth, and fifth main circuit switching power elements are turned off. Command the status, and switch the first, second and sixth main circuits. If the second line current comparison result becomes large before the first line current comparison result becomes large, the first line current comparison result is obtained from that point in time. Until the value becomes large, the second main circuit switching power element is instructed to be in the on state, the fifth main circuit switching power element is instructed to be in the on state, and the first line current comparison result is large. From the time to the next update timing, the first, second, and third main circuit switching power elements are commanded to be in the off state, and the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state. And also
If the first line current comparison result is large before the second line current comparison result is large, the first line current comparison result from that time to the second line current comparison result becomes large, Command the off-state to the main circuit switching power element and command the on-state to the fourth main circuit switching power element from the time when the second line current comparison result becomes large until the next update timing. The first, second, and third main circuit switching power elements are commanded to turn off, and the fourth, fifth, and sixth main circuit switching power elements are commanded to turn on.

With this configuration, the electric motor control device of the present invention can control the line current command and the line current respectively at the state update timing and at the timing when the first, second, and third line current comparison results change. Simple to determine whether the first, second, third, fourth, fifth, and sixth main circuit switching power elements are to be turned on or off, respectively, in a direction in which the difference between the measurement results decreases. By repeating such operations, it is understood that each line current of the three-phase motor approaches each line current command signal, and each line current error can be reduced. Since the motor control device of the present invention has no current error amplifier, it can essentially solve the problem relating to the gain adjustment of the current error amplifier, and does not need any gain adjustment. Furthermore, even if the characteristics and specifications of the three-phase motor, the line current detecting means, the current control means, and the main circuit power element group change, the operation always minimizes each line current error, and the manufacturing variation of the characteristics, temperature characteristics, etc. Even if there is an error, each line current error is always operated to be minimized, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs. In addition, the current control means in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second, and third comparison means, and the part constituted by the digital circuit is not subject to offset or drift. Not
It is also cheap. The six main circuit switching power elements are NPN transistors (or N-channel MOS).
-FET or N-channel IGBT) and has a bootstrap type base drive means. As a result, the loss of the entire motor control device can be reduced,
It is possible to achieve an IC and a reduction in size. The second motor control device according to the present invention directly or indirectly measures the line current flowing from each line into the three-phase motor, and measures the first line current measurement result, the second line current measurement result, and the third line current measurement result. A line current detection unit that outputs a line current measurement result, and a first line current command, a second line current command, and a third line current command that command a line current to flow into the three-phase motor from each line. The line current command generating means to be output and the magnitude relation between the first line current command and the first line current measurement result are compared, and the first line current measurement result is larger than the first line current command. In the case, the first line current comparison result is large, and the first line current measurement result is smaller than the first line current command. , The magnitude relationship between the second line current command and the second line current measurement result Compare, when the second line current measurement result is larger than the second line current command, the second line current comparison result is made larger, and the second line current measurement result is smaller than the second line current command. In the case, the second comparing means for reducing the second line current comparison result, and comparing the magnitude relationship between the third line current command and the third line current measurement result, the third line current When the third line current measurement result is larger than the command, the third line current comparison result is made larger, and when the third line current measurement result is smaller than the third line current command, the third line current is made larger. Third comparison means for reducing the comparison result, a main circuit DC power supply, and a first main circuit switching power supply connected to a positive terminal of the main circuit DC power supply and supplying a first line current to the three-phase motor. Element and
A second main circuit switching power element connected to a positive terminal of the main circuit DC power supply and supplying a second line current to the three-phase motor; and a three-phase motor connected to a positive terminal of the main circuit DC power supply. A third main circuit switching power element that supplies a third line current, and a fourth main circuit switching power element that is connected to a minus terminal of the main circuit DC power supply and supplies a first line current to the three-phase motor. When,
A fifth main circuit switching power element that is connected to the minus terminal of the main circuit DC power supply and supplies a second line current to the three-phase motor, and that the three-phase motor is connected to the minus terminal of the main circuit DC power supply. A sixth main circuit switching power element that supplies a third line current, a main circuit power element group configured with a reflux diode connected in parallel to each of the main circuit switching power elements and having a three-phase bridge configuration, The first line current comparison result, the second line current comparison result, and the third line current comparison result are input, and the first, second,
A logic circuit for generating a switching command signal for the third, fourth, fifth, and sixth main circuit switching power elements, and timing generation means for providing a periodic state update timing to the logic circuit, wherein the logic circuit If the first line current comparison result is small and the second line current comparison result is large and the third line current comparison result is large at the update timing, the second,
The third and fourth main circuit switching power elements are commanded to be in an off state, the first, fifth, and sixth main circuit switching power elements are to be commanded to be in an on state. If the second line current comparison result becomes small before the voltage becomes small, the fifth main circuit switching power element is turned off from that point until the third line current comparison result becomes small. Command the state and command the ON state to the second main circuit switching power element, the fourth, fifth, from the time when the third line current comparison result becomes small until the next update timing
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the second line current comparison result becomes small. When the third line current comparison result becomes small, the off state is instructed to the sixth main circuit switching power element from that time until the second line current comparison result becomes small. Command the ON state to the third main circuit switching power element, the fourth, fifth, sixth main circuit switching power between the time when the second line current comparison result becomes small and the next update timing Element to command the off state, the first, second, and third main circuit switching power element to be configured to command the on state, and the update timing, the first line current comparison result is large and the second Line current comparison result is small and the third line current If the comparison result is large, the first,
The third and fifth main circuit switching power elements are commanded to be in an off state, the second, fourth, and sixth main circuit switching power elements are commanded to be in an on state. If the third line current comparison result becomes smaller before the first line current comparison result becomes smaller, the sixth main circuit switching power element is turned off from that time until the first line current comparison result becomes smaller. Command the state and command the ON state to the third main circuit switching power element, from the time when the third line current comparison result becomes small to the next update timing, the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the third line current comparison result becomes small. When the first line current comparison result is small, the fourth main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes small. Command the ON state to the first main circuit switching power element, the fourth, fifth, sixth main circuit switching power from the time when the third line current comparison result becomes small to the next update timing Element to command the off state, the first, second, and third main circuit switching power element to be configured to command the on state, and the update timing, the first line current comparison result is large and the second Line current comparison results are large and the third line current If the comparison result is small, the first,
The second and sixth main circuit switching power elements are commanded to be in an off state, the third, fourth, and fifth main circuit switching power elements are commanded to be in an on state. If the first line current comparison result becomes smaller before the value becomes smaller, the fourth main circuit switching power element is turned off from that time until the second line current comparison result becomes smaller. Command the state and command the ON state to the first main circuit switching power element, the fourth, fifth, from the time when the second line current comparison result becomes small until the next update timing
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the first line current comparison result becomes small. If the second line current comparison result is small, the fifth main circuit switching power element is commanded to be in the off state from that time until the first line current comparison result becomes small. Command the ON state to the second main circuit switching power element, the fourth, fifth, sixth main circuit switching power between the time when the first line current comparison result becomes small and the next update timing Element to command the off state, the first, second, and third main circuit switching power element to be configured to command the on state, and the update timing, the first line current comparison result is large and the second Line current comparison result is small and the third line current If the comparison result is small, the first,
The fifth and sixth main circuit switching power elements are commanded to be in an off state, the second, third, and fourth main circuit switching power elements are to be commanded to be in an on state. If the second line current comparison result becomes large before becoming large, the second main circuit switching power element is turned off from that time until the third line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, the period from the time when the second line current comparison result becomes large to the next update timing is the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the second line current comparison result becomes large. When the third line current comparison result becomes large, the third main circuit switching power element is commanded to be in an off state from that time until the second line current comparison result becomes large. Command the ON state to the sixth main circuit switching power element, the fourth, fifth, sixth main circuit switching power from the time when the second line current comparison result becomes large to the next update timing The off-state command is issued to the element, the first, second, and third main circuit switching power devices are configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison results are large and the third line current If the comparison result is small, the second,
The fourth and sixth main circuit switching power elements are commanded to be in an off state, the first, third, and fifth main circuit switching power elements are commanded to be in an on state, and then the first line current comparison result is obtained. If the third line current comparison result becomes large before it becomes large, the third main circuit switching power element is turned off from that time until the first line current comparison result becomes large. Command the state and command the ON state to the sixth main circuit switching power element, from the time when the first line current comparison result becomes large to the next update timing, the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the third line current comparison result becomes large. When the first line current comparison result becomes large, the first main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes large. Command the ON state to the fourth main circuit switching power element, and execute the fourth, fifth, and sixth main circuit switching power between the time when the third line current comparison result becomes large and the next update timing. The off-state command is issued to the element, the first, second, and third main circuit switching power devices are configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison result is small and the third line current If the comparison result is large, the third,
The fourth and fifth main circuit switching power elements are commanded to be in an off state, the first, second, and sixth main circuit switching power elements are commanded to be in an on state. If the second line current comparison result becomes large before becoming large, the second main circuit switching power element is turned off from that time until the first line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, the fourth line, the fifth, from the time when the first line current comparison result becomes large to the next update timing
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the second line current comparison result becomes large. When the first line current comparison result becomes large, the off state is instructed to the first main circuit switching power element from that time until the second line current comparison result becomes large. Command the ON state to the fourth main circuit switching power element, the fourth, fifth, sixth main circuit switching power between the time when the second line current comparison result becomes large and the next update timing It is configured to instruct the element to be in the off state and to instruct the first, second, and third main circuit switching power elements to be in the on state.

With such a configuration, the motor control device of the present invention can control the line current command and the line current at the time of the state update timing and at the timing when the first, second, and third line current comparison results change. Simple to determine whether the first, second, third, fourth, fifth, and sixth main circuit switching power elements are to be turned on or off, respectively, in a direction in which the difference between the measurement results decreases. By repeating such operations, it is understood that each line current of the three-phase motor approaches each line current command signal, and each line current error can be reduced. Since the motor control device of the present invention has no current error amplifier, it can essentially solve the problem relating to the gain adjustment of the current error amplifier, and does not need any gain adjustment. Furthermore, even if the characteristics and specifications of the three-phase motor, the line current detecting means, the current control means, and the main circuit power element group change, the operation always minimizes each line current error, and the manufacturing variation of the characteristics, temperature characteristics, etc. Even if there is an error, each line current error is always operated to be minimized, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs. In addition, the current control means in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second, and third comparison means, and the part constituted by the digital circuit is not subject to offset or drift. Not
It is also cheap. The six main circuit switching power elements are PNP transistors (or P-channel MOS).
-FET or P-channel IGBT) and having a bootstrap-type base drive means. As a result, the loss of the entire motor control device can be reduced,
It is possible to achieve an IC and a reduction in size.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a motor control device according to the present invention will be described below with reference to the drawings.

(Embodiment 1) This embodiment is a motor control device in which the configuration shown in FIG. 6 is applied to the main circuit power element group 4 and the current control means 14 in the conventional motor control device.

Hereinafter, the configuration of the present embodiment will be described in detail with reference to FIGS. 1, 2 and 6. FIG.

In the following description, the main circuit power element group 4 and the current control means 14 will be mainly described, and the other parts which have already been described in the prior art will be denoted by the same reference numerals and description thereof will be omitted. I do.

The main circuit power element group 4 is connected to a positive terminal of the main circuit DC power supply 3 and supplies a first line current IU to the three-phase motor 1 as shown in FIG. Q1, a second main circuit switching power element Q2 connected to the plus terminal of the main circuit DC power supply 3 and supplying the second line current IV to the three-phase motor 1, and connected to a plus terminal of the main circuit DC power supply 3. A third main circuit switching power element Q3 that supplies a third line current IW to the three-phase motor 1 and a first line current IU that is connected to the minus terminal of the main circuit DC power supply 3 and supplies the three-phase motor 1 Fourth main circuit switching power element Q4 and main circuit DC power supply 3
The fifth main circuit switching power element Q connected to the negative terminal of the
5, a sixth main circuit switching power element Q6 connected to the negative terminal of the main circuit DC power supply 3 and supplying the third line current IW to the three-phase motor 1, and connected in parallel to each main circuit switching power element. A three-phase bridge 35 composed of a freewheeling diode, a logic inversion means 37 and a base drive means 36, and a first main circuit according to the switching command signal PU by the action of the logic inversion means 37 and the base drive means 36. One of the switching power element Q1 and the fourth main circuit switching power element Q4 is turned on, and one of the second main circuit switching power element Q2 and the fifth main circuit switching power element Q5 is turned on according to the switching command signal PV. The third main circuit switching power element according to the switching command signal PW. Q3 and is obtained either the sixth main circuit switching power element Q6 configured so as to ON.

Here, the switching command signal PU is H
Level, the first main circuit switching power element Q
1 is turned on, and when the switching command signal PU becomes L level, the fourth main circuit switching power element Q4
Is turned on, and when the switching command signal PV becomes H level, the second main circuit switching power element Q2 is turned on. When the switching command signal PV becomes L level, the fifth main circuit switching power element Q5 is turned on. Also, a description will be given of a configuration in which the third main circuit switching power element Q3 is turned on when the switching command signal PW goes high, and the sixth main circuit switching power element Q6 is turned on when the switching command signal PW goes low.

The current control means 14, as shown in FIG.
Comparison means 30, 3 for comparing the line current command signals iTU, iTV, iTW with the line current measurement results iFU, iFV, iFW.
1, 32, a logic circuit 33 for outputting switching command signals PU, PV, PW based on these outputs, and a timing generating means 34 for generating a timing signal for controlling the operation timing of the logic circuit 33. I have.

Here, the first, second and third comparing means 3
0, 31, and 32 respectively have inverting input terminals iTU, iT
V, iTW are input, and the first, second, and third line current measurement results iFU, iFV, iF
W is input. Then, the first, second, and third line current comparison results HU, HV, and HW are output from each comparing unit.

For the sake of convenience in the following description, the HU, H
V and HW are H level when the line current measurement result is larger than the line current command value, and are L level when the line current measurement result is smaller than the line current command value. Shall be.

The logic circuit 33 receives the first, second, and third line current comparison results HU, HV, and HW, receives the update timing signal CLK10 from the timing generator 34, and switches the main circuit. Second switching command signals PU, PV, PW for commanding ON and OFF of power elements Q1, Q2, Q3, Q4, Q5, Q6
Is output.

First, the logic circuit 33 changes the state at the rising edge of the update timing signal CLK10 based on the signal levels of the first, second and third line current comparison results HU, HV and HW. , The switching command signals PU, PV, and PW are output. Then, based on the change in the signal levels of the first, second, and third line current comparison results HU, HV, and HW, the switching command signals PU, PV, and PW are output.
It is configured to change the PW.

Here, the truth table of the logic circuit 33 is shown in (Table 1), and its operation will be described.

[0037]

[Table 1]

Hereinafter, how to read Table 1 will be described. In (Table 1), state No. (A00, AX1,
AX2, A00, AY1, AY2, B00, BX1, etc.)
Indicates the input / output state of the logic circuit 33, the symbol ↑ of the update timing signal indicates the timing of the rising edge of the update timing signal CLK10, and the symbol ◆ indicates a stable state of H level or L level.

The symbol * in the line current comparison result is DO
N'T CARE, that is, indicates that the operation is not related to the H level or the L level.

In other cases, H indicates H level and L indicates L level. The reset signal RESET is an input signal for initializing the logic circuit 33. When the logic signal is normally at L level and H level, the logic circuit 33 is immediately initialized.

Next, the operation of the logic circuit 33 will be described with reference to (Table 1). First, the update timing signal CLK1
When 0 rises (a rising edge is input), the first, second, and third line current comparison results HU, H at that time
V, HW, the state No. A00, B0
0, C00, D00, E00, F00, G00, H00
To eight states. (Focusing on the first digit of the state number, branching to eight from A to H. For convenience of explanation, the three-digit alphanumeric symbols of the state number are the first, second, and third digits from the left.
It is called the digit. )

Here, first, state No. A00, B0
A case will be described in which the state changes to any one of 0, C00, D00, E00, and F00.

In the case of transition to these states, the first, second, and third line current comparison results HU, HV, H of the rising edge timing of the update timing signal CLK10.
Focusing on two signals of the same signal level out of W,
The subsequent operation differs depending on which of the two signals changes first. (Focusing on the second digit of the state No., branching to X and Y)

For example, the state No. In the case of A00, if the second line current comparison result HV changes first, the state No. AX
1 if the third line current comparison result HW changes first. Transition to AY1.

Thereafter, among the first, second, and third line current comparison results HU, HV, and HW of the rising edge timing of the update timing signal CLK10, the signal has first changed among two signals of the same signal level. When the other signal other than the signal changes, the state No. And the third digit is the same as the first and second digits.

For example, state No. From the state of AX1,
State No. AX2, state No. If the state is AY1, the state No. Transition to AY2.

Thereafter, the state is held until the timing of the next rising edge of the update timing signal CLK10.

Finally, at the timing of the rising edge of the update timing signal CLK10, the state No. Explaining the case of transition to G00 or H00, in these cases, this state is maintained until the next rising edge of the update timing signal CLK10 is input, and accordingly, the switching command signals PU, PV, PW output their levels. Keep doing.

The above is the description of the reading of (Table 1). Hereinafter, the operation of the logic circuit 33 will be described based on the truth table of (Table 1).

First, the operation at the timing of the rising edge of the update timing signal CLK10 will be described.

The logic circuit 33 includes an update timing signal CL
At the timing of the rising edge of K10, the signal levels of the first, second, and third line current comparison results HU, HV, and HW are read, and the first, second, and third line current measurement results iFU, iFV at that time are read. , IFW, respectively, the first, second,
The outputs PU, P of the logic circuit 33 are moved in a direction approaching the third line current command iTU, iTV, iTW, that is, in such a manner that iFU, iFV, iFW change in accordance with the line current command.
V and PW signal levels are determined. This results in
The signal levels of PU, PV, and PW are inverted levels of HU, HV, and HW, respectively. For example, if the HU is at the H level, the PU is determined to be at the L level, and if the HU is at the L level, the PU is determined to be at the H level. The same applies to PV and PW.

Next, the operation of the logic circuit 33 from the timing of the rising edge of the update timing signal CLK10 to the timing of the next rising edge of the update timing signal CLK10 will be described.

The operation during this period is performed according to the update timing signal CL.
H at the timing of the rising edge of K10
It is determined by the levels of three signals U, HV and HW.

Here, focusing on the three signal levels of HU, HV, and HW, the operation when one of the three signal levels is different, that is, (HU, HV, HW) = ( L, H, H) or = (H, L, H) or = (H, H, L) or = (H, L, L) or = (L, H, L) or = (L, L, H ) And when all three signal levels are the same level,
That is, (HU, HV, HW) = (H, H, H) or = (L, L, L) will be described separately below.

First, at the timing of the rising edge of the update timing signal CLK10, HU, HV, H
The operation when the level of one of the three signal levels W is different will be described.

It is self-evident that the line current of the three-phase motor 1 is a value obtained by inverting the polarity of the sum of the values of the two line currents of the three line currents to the remaining one value. Therefore, the logic circuit 33 according to the embodiment of the present invention focuses on two signals having the same level among the three signals HU, HV, and HW at the timing of the rising edge of the update timing signal CLK10. The levels of the switching command signals PU, PV, and PW are determined so as to control ON and OFF of the main circuit switching power element that supplies the line current related to the switching circuit.

That is, first, ON / OFF of a main circuit switching power element for supplying a line current related to a signal whose level is inverted first of two signals having the same level.
, The level of the corresponding switching command signal is inverted so as to switch to OFF if ON, and ON if OFF. Subsequently, when the level of the remaining one of the two signals having the same level is inverted, the three main circuit switching power elements connected to the positive side of the main circuit DC power supply are turned off, In addition, a corresponding switching command signal is output so as to turn on three main circuit switching power elements connected to the negative side of the main circuit DC power supply.

At this time, three signals of the switching command signals PU, PV, and PW, which are the outputs of the logic circuit 33, have the same level (PU, PV, PW) = (L, L, L), and the next update timing The PU, PV, and PW maintain their levels until the timing of the rising edge of the signal CLK10. Then, the same operation is repeated after the timing of the next rising edge of the update timing signal CLK10.

Next, at the timing of the rising edge of the update timing signal CLK10, HU, HV, H
The operation in the case where the levels of all three signals W are the same will be described.

If the three signals HU, HV, and HW are all at the same level, the timing until the next rising edge of the update timing signal CLK10 is reached.
The signal level (PU, PV, PW) = (L, L, L) determined at the timing of the rising edge of the update timing signal CLK10 is maintained.

The above is the description of the current control means 14. Hereinafter, the configuration of the logic circuit 10 of the current control unit 6 of the motor control device according to the first embodiment of the present invention will be described in more detail.

The internal configuration of the logic circuit 10 will be described below with reference to FIG. In FIG. 3, first, the operation of the components will be described.

First, 60, 61, 62, 63, 64, 6
5 is the first, second, third, fourth, fifth, sixth EX-NO
The operation of the R circuit is to output an L level when the levels of the signals input to the two input terminals are different, and to output an H level when the levels of the signals input to the two input terminals are the same.

Next, reference numerals 66, 67, and 68 denote first, second, and third reset priority RS flip-flops each having an input terminal R.
Is high and the input terminal S is low, the output terminal Q changes to low, and the input terminal R is low.
And when the input terminal S is at the H level, the output terminal Q is changed to the H level. When the input terminal R is at the H level and the input terminal S is at the H level, the reset is preferentially reset, and the output terminal is reset. Q changes to L level.

Next, 69, 70, 71, 72, 73, 7
Reference numeral 4 denotes first, second, third, fourth, fifth, and sixth D latches, which latch the level of the input terminal D at the timing of the rising edge of the signal input to the input terminal CK and change the level thereof. Output to the output terminal Q. However, the input terminal PR is a terminal for inputting a preset signal. When an H level is input, the input terminal PR is preset with the highest priority.
The level is output.

Next, reference numeral 76 denotes a first NOR circuit, which operates to output an H level when the levels of the signals input to the three input terminals are all L levels, and to output an L level otherwise. Output.

Next, reference numeral 77 denotes a first OR circuit, which operates to output an L level when the levels of the signals input to the two input terminals are all L levels, and to output an H level otherwise. Output. 22 is a data decoding means,
It has input terminals A, B, and C and an output terminal Y, and its truth table is shown in (Table 2).

In the truth table (Table 3), AND, O
It can be easily realized by R and an inverting gate.

[0069]

[Table 2]

Numeral 34 is a timing signal distribution means, which is a system clock CLK1 and a state update timing signal CLK.
10, the state update timing delay signal CLK11
Is output.

Here, CLK1, CLK10 and CL
The relationship of K11 will be described with reference to FIG.
It is assumed that the cycle of the state update timing signal CLK10 is sufficiently larger than the cycle of the system clock CLK1, and that the update timing signal CLK10 changes in synchronization with the falling edge of the system clock CLK1. Next, the state update timing delay signal CLK11
Is a signal obtained by delaying the state update timing signal CLK10 by about half of the time between the rising edge and the falling edge of the system clock CLK1.

The operation of the components has been described above. The operation of the logic circuit 10 will be described below following the flow of signals.

Here, the first, second and third EX-NO
The outputs of the R circuits 60, 61, and 62 are output to the output signals Y1U, Y1
1V, Y1W, and outputs of the first, second, and third RS flip-flops 66, 67, and 68 to output signals Y2U, Y
2V, Y2W, 4th, 5th, 6th EX-NOR
The outputs of the circuits 63, 64 and 65 are output to output signals Y3U and Y3.
V, Y3W. First, the first, second and third line current comparison results HU, HV and HW are respectively the first and second line current comparison results.
The signals are input to the D input terminals of the second and third D latches 69, 70, and 71, respectively, and the first, second, and third EX-N
The signals are input to the input terminals of the OR circuits 60, 61, and 62.

Here, the state update timing signal CLK1
0 changes from the L level to the H level, that is, the state immediately after the rising edge is input, that is, FIG.
Will be described. First, the input levels of the D input terminals of the first, second, and third D latches 69, 70, and 71 are latched and held, and output to the output terminal Q, respectively. This state of the first, second, and third D latches 69, 70, 71 does not change until the next rising edge of the state update timing signal CLK10 is input. Next, the first, second, and third D latches 69,
The signals output from the output terminals Q of 70 and 71 are input to the data decoding means 22, and the output terminal Y is set to H level or L level according to the truth table shown in Table 3. Hereinafter, a signal output from the output terminal Y is referred to as a mode signal Y.
Let's call it M.

Here, the first, second and third EX-NORs
The mode signal YM is input to the other input terminals of the circuits 60, 61, and 62, and the first, second, and third EX-
The NOR circuits 60, 61 and 62 output output signals Y1U, Y1V and Y1W according to the mode signal YM.

Next, the state update timing delay signal CLK
11 changes from the L level to the H level, that is, a rising edge is input. The state immediately after this, that is, TIME2 in FIG. 4 will be described. First, the first, second, and third RS flip-flops 66, 6
The state update timing delay signal CLK11 is input to each of the input terminals S, 7 and 68, and is set when the signal is at the H level. However, as mentioned above, the first,
Since the second and third RS flip-flops 66, 67 and 68 are reset priority RS flip-flops, when the input terminal R is at the H level, the reset is prioritized. Therefore, among the first, second, and third RS flip-flops 66, 67, and 68, only the one whose input terminal R is at the L level has the state update timing delay signal CLK11 at the H level.
The result is set at the level.

The output signals Y2U, Y2V, Y of these first, second, and third RS flip-flops 66, 67, 68
2W is input to the input terminals of the fourth, fifth, and sixth EX-NOR circuits 63, 64, and 65, respectively, and is input to the first NOR circuit 76.

The output signal of the first NOR circuit 76 is connected to the first OR circuit 77 together with the mode signal YM, and the first OR circuit 77 is connected to the first NOR circuit 76.
Is high when the output signal or the mode signal YM is at the H level.
Output level. The fourth, fifth and sixth EX-NO
The output signals of the first OR circuit 77 are input to the other input terminals of the R circuits 63, 64, 65, and the fourth, fifth, and sixth EX-NOR circuits 63, 64, 65 According to the output signal of one OR circuit 77, output signals Y3U, Y3U
Output 3V, Y3W.

Next, the state immediately after the system clock CLK1 changes from the L level to the H level, that is, a rising edge is input, that is, TIME3 in FIG. 4 will be described. First, when the rising edge of the system clock CLK1 is input to the input terminal CK of the fourth, fifth, and sixth D latches 72, 73, 74, the fourth, fifth, and sixth D latches 72, 73, 74
Inputs and latches output signals Y3U, Y3V, Y3W from an input terminal D, and outputs fourth, fifth, and sixth D latches 72,
The output terminals Q of 73 and 74 are connected to the latched input terminal D.
And the output signals are held until the next rising edge of the state update timing signal CLK10. The signals output from the fourth, fifth, and sixth D latches 72, 73, and 74 become switching command signals PU, PV, and PW.

Here, the switching command signals PU, P
V, PW are the fourth, fifth, and sixth D latches 72, 73,
Since it is updated at the timing when the rising edge of the system clock CLK1 is input to the input terminal CK of 74, it does not change at TIME1 or TIME2.

The above is the state update timing signal CLK1
0 changes from L level to H level (TIME
From 1), the state update timing delay signal CLK11 becomes L
The operation at the time when the level changes from the level to the H level (TIME2) and the time when the system clock CLK1 subsequently changes from the L level to the H level (TIME3) will be described.

These are the state update timing signals CLK
10 is an operation when a rising edge is input (a rising edge is input). A00, B0
0, C00, D00, E00, F00, G00, H00
It is an explanation of the operation of transitioning to the eight states. Next, the subsequent operation, that is, the next state update timing signal CL
The operation until the rising edge of K10 is input will be described.

Here, first, state N in (Table 1)
o. A00, B00, C00, D00, E00, F00
, Ie, two signals of the same signal level among the first, second, and third line current comparison results HU, HV, and HW of the rising edge timing of the state update timing signal CLK10. A case will be described.

Here, the state of A00 in (Table 1) will be described as an example. State No. In the state of A00,
Line current comparison result HU is L level, HV is H level, HW
Is H level, mode signal YM is L level, output signal Y1
U is at H level, Y1V is at L level, Y1W is at L level,
The first RS flip-flop 26 is in a reset state, the second RS flip-flop 27 is in a set state, and the third RS flip-flop 27 is in a set state.
The flip-flop 28 is in a set state. The output signal Y3U is at L level, Y3V is at H level, and Y3W is at H level.
Level.

Here, first, the second line current comparison result HV
Changes from the H level to the L level, that is, the state No. in (Table 1). A00 to state No.
Consider the operation that transitions to AX1. When the second line current comparison result HV changes from H level to L level,
The level of the output signal Y1V switches from the L level to the H level, whereby the second RS flip-flop 27
Is reset, the output signal Y3V is switched from L level to H level.

Therefore, PU, PV, and PW become (PU, PV, PW) = (H, H, L) at the timing of the next rising edge of the system clock CLK1. The next-stage main circuit power element group 4 operates according to the switching command signals PU, PV, and PW.

Next, after that, the third line current comparison result HW
Changes from the H level to the L level, that is, the state No. in (Table 1). AX1 to state No.
Consider the operation that transitions to AX2.

When the third line current comparison result HW changes from H level to L level, the level of output signal Y1W becomes L
From the level to the H level, which resets the third RS flip-flop 28.
Output signal Y2W is switched from H level to L level. At this point, the first, second, and third RS flip-flops 66, 67, and 68 are all in the reset state, and (Y2U, Y2V, Y2W) = (L, L, L), and the first OR circuit 77 Switches from the L level to the H level. Also, output signals Y3U, Y3V, Y3W of the fourth, fifth, and sixth EX-NOR circuits 63, 64, 65 are provided.
(Y3U, Y3V, Y3W) = (L, L, L).

Therefore, PU, PV, and PW become (PU, PV, PW) = (L, L, L) at the timing of the next rising edge of the system clock CLK1. The next-stage main circuit power element group 4 operates according to the switching command signals PU, PV, and PW.

This state, that is, (PU, PV, PW) = (L, L, L) is the system clock CLK1 after the timing of the next rising edge of the state update timing signal CLK10.
Is maintained until the timing of the rising edge of. Up to now, the state No. is set at the timing of the rising edge of the state update timing signal CLK10. A00, B00, C
00, D00, E00, or F00, that is, the same among the first, second, and third line current comparison results HU, HV, and HW of the rising edge timing of the state update timing signal CLK10. The operation in the case where there are two signals of the signal level will be described. G00 or H00, that is, the first of the rising edge timings of the state update timing signal CLK10,
The case where the second and third line current comparison results HU, HV, HW are all at the same signal level will be described.

Here, the state No. shown in Table 1 is used. The state of G00 will be described as an example. State No. In the state of G00, the line current comparison result HU is at H level, HV is at H level, HW is at H level, the mode signal YM is at H level, and Y is at Y level.
1U is at the H level, Y1V is at the H level, Y1W is at the H level, and the first, second, and third RS flip-flops 66, 6
7 and 68 are all in the reset state, and the output of the first OR circuit 77 is at the H level.

As a result, Y3U is at L level and Y3V is at L level.
Level, Y3W, is the L level and therefore PU, P
V and PW are at the timing of the next rising edge of the system clock CLK1, PU is at L level, PV is at L level, and PW is at L level. According to the PU, PV and PW, the main circuit power element group 4 in the next stage Works.

This state, that is, (PU, PV, PW) = (L, L, L) is the system clock CLK1 after the timing of the next rising edge of the state update timing signal CLK10.
Is maintained until the timing of the rising edge of. The above is the state No. in (Table 1). A00 to state No.
AX1 and state No. The transition to AX2,
At the timing of the rising edge of the state update timing signal CLK10, the state No. This is the description of the operation when the state transitions to G00. However, since other state transitions in (Table 1) can be considered in the same manner as described above, the description is omitted.

The above is the description of the logic circuit 1 in the current control means 6 of the motor control device according to the first embodiment of the present invention.
0 is a specific operation description. Next, referring to FIG.
The manner in which the line current is controlled by the current control means 14 in the above-described embodiment will be described.

In FIG. 5, (a) shows first, second, and third line current commands iTU, iTV, iTW and first, second, and third line current measurement results iFU, iFV, iFW. FIG. 7B is a diagram showing the operation of the logic circuit 33 in which the dotted line portion of FIG. 7A is enlarged, and FIG.
The first, second, third, fourth, fifth, sixth main circuit switching power elements Q1, Q2, Q3, based on the output levels of the switching command signals PU, PV, PW which are the outputs of
It is a figure which shows ON and OFF operation | movement of Q4, Q5, and Q6.

First, at time t = t1, that is,
The operation at the timing of the rising edge of the update timing signal CLK10 will be described.

ITU, iTV, iTW and iF of the timing of the rising edge of update timing signal CLK10
At time t = t1 where the magnitude relationship between U, iFV, and iFW is iTU> iFU iTV <iFV iTW <iFW, the first, second, and third line current comparison results HU, HV, HW are (HU, HV) , HW) = (L, H, H).

This state corresponds to state No. in the truth table of (Table 1). The switching command signals PU, PV, PW corresponding to A00 and output from the logic circuit 33 are (PU, PV, PW) = (H, L, L) and transmitted to the main circuit power element group 4.

Then, the main circuit switching power element Q
1, Q2, Q3, Q4, Q5, and Q6 are ON and OF, respectively.
F, OFF, OFF, ON, ON, and each line current measurement result iFU, iFV, iFW approaches each line current command iTU, iTV, iTW according to the electrical time constant of the three-phase motor 1.

The above is the description of the current control operation by the current control means 14 at the timing of the rising edge of the update timing signal CLK10 at time t = t1.

Next, iTV> iFV, and (HU, HV, HW) = (L, H, H) to (HU, H
(V, HW) = (*, L, H) The operation at the timing (time t = t11) will be described. (Since the level of the HU is ignored, HU = * means DON'T CARE for the sake of explanation.
Hereinafter, '*' means DON'T CARE. )

The logic circuit 10 receives the first, second, and third line current comparison results HU, HV, and HW, and outputs the switching command signals PU, PV, and PW as (PU, PV, PW) = ( H, L, L) to (PU, P
V, PW) = (H, H, L), and the main circuit switching power element Q2 is
Switch N and Q5 to OFF. (Transition to state No. AX1)

The above is the description of the operation at time t = t11. Next, iTW> iFW, and (HU, HV, HW) = (*, L, H) to (HU, H
(V, HW) = (*, H, H) The operation at the timing (time t = t12) will be described.

The logic circuit 33 receives the first, second, and third line current comparison results HU, HV, and HW, and outputs switching command signals PU, PV, and PW as follows: (PU, PV, PW) = ( H, H, L) to (PU, P
V, PW) = (L, L, L), and the main circuit switching power elements Q1, Q
2. Switch Q3 off and Q4, Q5, Q6 on. (Transition to state No. AX2)

The operation at time t = t12 has been described. Then, the state of (PU, PV, PW) = (L, L, L) is maintained until the next rising edge timing of the update timing signal CLK10.

Further, the next update timing signal CLK
By performing the same operation after the timing of the rising edge of No. 10, the respective line currents of the three-phase motor 1 become first, second, and
Control is performed in accordance with the third line current commands iTU, iTV, and iTW.

The above is a description of how the current is controlled by the current control means 14 in the present embodiment.

As described above, since the motor control device of the present embodiment does not have a current error amplifier, the problem relating to the gain adjustment of the current error amplifier can be essentially solved. Absent.

Furthermore, even if the characteristics and specifications of the three-phase motor 1, the line current detection means 6, the current control means 14, and the main circuit power element group 4 change, the operation is always performed to minimize the line current error. Even if there are manufacturing variations, temperature characteristics, etc., the line current error is always minimized, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs.

The current control means 6 in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second, and third comparison means. There is no worry about drifting and it is inexpensive. Therefore, the present invention does not require the gain adjustment work and offset adjustment work of the current error amplifier,
An inexpensive motor control device with excellent current control responsiveness can be supplied.

Further, the state No. , The state of the switching command signals PU, PV, and PW at all times is (L, L, L), so that the states of the switching command signals PU, PV, and PW are all (L, L, L), and finally the power elements Q4, Q4 provided on the minus side of the main circuit DC power supply.
5 and 6 are turned on, the main circuit switching power element can be driven by the bootstrap type base drive means 36 as shown in FIG.

The bootstrap type base drive means 36 is generally well known. The main circuit switching power element is constituted by an NPN transistor (or an N-channel MOS-FET or an N-channel IGBT), and the main circuit DC power is supplied. When the main circuit switching power element Q4, Q5, or Q6 on the minus side of the power supply is in the ON state, energy for driving the main circuit switching power element Q1, Q2, or Q3 on the plus side of the main circuit DC power supply is supplied. Power element Q stored in capacitor C
1, or Q2 or Q3.

This method is characterized by low loss and easy circuit integration. Therefore, by outputting the switching command signal to the logic circuit 33 based on (Table 1), the main circuit power element group 4 having the above-described bootstrap type base drive means 36 can be applied, and the motor control can be performed. Low loss of the whole device, I
C and miniaturization can be realized.

In FIG. 2, the base drive means 36 is shown as a bootstrap type, but it goes without saying that the embodiment of the present invention can be applied to a method using an insulating transformer.

It is generally known that the current control means 14 uses a hysteresis comparator as another configuration as shown in FIG.

However, when current control is performed by the current control means 15 using the hysteresis comparator,
Since the line current command signal and the line current measurement result are simply compared to form the second switching command signals PU, PV, PW, the second switching command signals PU, PV, PW are set to H
There is no regularity in the timing of the level or L level.

Using such irregular signals as switching command signals PU, PV, PW, main circuit power element group 4
Is controlled, the switching frequency of each main circuit switching power element Q1 to Q6 is not determined, and the operation becomes unstable. That is, if the noise of the motor becomes large or the switching frequency becomes too high, the switching loss of the main circuit switching power elements Q1 to Q6 increases, and in some cases, there is a possibility of causing breakdown. is there.

When the current control is performed by the current control means 14 having the configuration shown in FIG. 1 as in the present embodiment, the switching timing of the main circuit switching power element is updated as is clear from the above description. Can be controlled by the timing, (the switching of the main circuit switching power element, during the update timing,
The update timing and the change timing of each line current comparison result can be set to two times. 3.) The switching frequency of the main circuit switching power elements Q1 to Q6 can be stabilized.

Therefore, the switching operation of the main circuit switching power element is stabilized, the generation of noise of the motor is suppressed, the switching loss of the main circuit switching power elements Q1 to Q6 does not increase, and there is no fear of destruction. The problem as in the case of the configuration using the hysteresis comparator shown in FIG. 22 is eliminated.

(Embodiment 2) In the present embodiment, the internal configuration of the logic circuit 33 provided in the current control means 14 in the motor control device of the first embodiment is shown in FIG.
As shown in FIG. 5, the configuration is different from that of the first embodiment.

Since the other configuration except for the internal configuration of the logic circuit 35 is exactly the same as that of the first embodiment, the description of the other parts already described in the first embodiment is omitted. In particular, the configuration and operation of the logic circuit 35 will be described.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. First, before explaining the logic circuit 35, a truth table of the logic circuit 35 is shown in (Table 3).

[0123]

[Table 3]

The way of reading (Table 3) is exactly the same as the truth table (Table 1) of the logic circuit 33 of the first embodiment.
Explanation of how to read is omitted.

Logic circuit 35 based on the truth table of (Table 3)
In the operation, the same operation as the logic circuit 33 of the first embodiment will not be described.

The logic circuit 35 sets the first and second timings at the rising edge timing of the state update timing signal CLK10.
The second and third line current comparison results HU, HV, HW are read, and PU, PV, P are determined based on these HU, HV, HW.
Determining the signal level of W is exactly the same as the operation of the logic circuit 33 of the first embodiment.

Next, the next state update timing signal CL
Regarding the operation of the logic circuit 35 up to the timing of the rising edge of K10, similarly to the description of the operation of the logic circuit 33 of the first embodiment, the operation when one of the three signal levels is different, that is, (HU , HV, HW) = (L, H, H) or = (H, L, H) or = (H, H, L) or = (H, L, L) or = (L, H, L) or = (L, L, H) and the case where all three signal levels are the same level,
That is, (HU, HV, HW) = (H, H, H) or = (L, L, L) will be described separately below.

First, the state update timing signal CLK10
HU, H at the timing of the rising edge of
The operation when the level of one of the three signal levels V and HW is different will be described.

First, the state update timing signal CLK10
HU, H at the timing of the rising edge of
Regarding the operation in the case where one of the three signal levels of V and HW is different, the main circuit that supplies a line current related to the signal whose level is inverted first among two signals having the same level ON of switching power element,
Inverting the level of the corresponding switching command signal so that OFF is switched to ON if OFF and ON if OFF is exactly the same as the operation of the logic circuit 33 of the first embodiment. Subsequently, when the level of the remaining one of the two signals having the same level is inverted, the three main circuit switching power elements connected to the minus side of the main circuit DC power supply are turned off. 3 connected to the positive side of the main circuit DC power supply
A corresponding switching command signal is output so as to turn on the two main circuit switching power elements.

At this time, the three signals of the switching command signals PU, PV, and PW output from the logic circuit 35 have the same level (PU, PV, PW) = (H, H, H), and the next update timing The PU, PV, and PW maintain their levels until the timing of the rising edge of the signal CLK10. Then, the same operation is repeated after the timing of the next rising edge of the update timing signal CLK10.

Next, at the timing of the rising edge of the update timing signal CLK10, HU, HV, H
The operation in the case where the levels of all three signals W are the same will be described.

If the levels of the three signals HU, HV and HW are all the same, until the timing of the next rising edge of the update timing signal CLK10,
The signal level (PU, PV, PW) = (H, H, H) determined at the timing of the rising edge of the update timing signal CLK10 is maintained.

The above is the description of the configuration of the current control means 14 of the motor control device according to the second embodiment of the present invention. The following describes the current control of the motor control device according to the second embodiment of the present invention. The configuration of the logic circuit 35 of the means 14 will be described in more detail.

The internal configuration of the logic circuit 35 will be described below with reference to FIG. 8, with respect to differences from the first embodiment.

Referring to FIG. 8, first, the operation of newly provided components in the logic circuit 33 of the first embodiment will be described.

A second OR circuit 79 outputs an L level to an output terminal when the L level is input to all of the two input terminals of the second OR circuit 79. If at least one of the input terminals is at the H level, the H level is output to the output terminal.

Reference numeral 80 denotes a first AND circuit, which is a first AND circuit.
When the H level is input to all of the two input terminals of the circuit 80, the H level is output to the output terminal. If at least one of the input terminals has the L level, the L level is output to the output terminal.

With the above components, the output signals Y of the first, second, and third RS flip-flops 66, 67, 68
2U, Y2V, and Y2W are input to three input terminals of the second OR circuit 79, respectively. This second OR circuit 79
And the mode signal YM are connected to the input terminals of the first AND circuit 80, respectively. That is, when the mode signal YM is at the H level and at least one of Y2U, Y2V, and Y3V is at the H level, the first AND circuit 80 outputs the H level.

This is the first, regardless of the mode signal YM.
When the second and third RS flip-flops 66, 67 and 68 are all reset, the output of the first AND circuit 80 goes to L level, and the fourth, fifth and sixth EX-NOs
Output signals Y3U, Y3V, Y of R circuits 63, 64, 65
This means that 3W and PU, PV, and PW also become H level.

The operation of the logic circuit 35 configured as described above will be described below. From FIG. 4, from the levels of PU, PV, and PW determined at the timing of the rising edge of the state update timing signal CLK10 to the rising edge of the state update timing signal CLK10, among the three signals PU, PV, and PW, First one
Y2U, Y2
Since at least one of the signal levels V and Y2W is at the H level, the output of the first AND circuit 80 is at the same level as the mode signal YM.
The fourth, fifth, and sixth EX-NOR circuits 6 are used until the flip-flops 66, 67, and 68 are all reset.
The levels of the input terminals 3, 64 and 65 are not inverted.

Therefore, A00, B0 in Table 2
0, C00, D00, E00, F00, that is, the state update timing signal CLK1
When there are two signals of the same signal level among the first, second, and third line current comparison results HU, HV, and HW of the rising edge timing of 0, the rising edge of the state update timing signal CLK10 From the PU, PV, and PW levels determined at the timing, PU, P
The operation is exactly the same as that of the first embodiment up to the transition of the operation in which any one of the three signals V and PW is inverted first.

Subsequently, when the remaining one of the HU, HV, and HW signals is inverted, the first, second, and third R signals are inverted.
The S flip-flops 66, 67, 68 are all reset, and the fourth, fifth, and sixth EX-NOR circuits 63, 64,
The level of the input terminal 65 is inverted, and the state N of (Table 2) is changed.
o. As shown in AX2, AY2, BX2, BY2, etc.,
State No. of (Table 1) Is switched to the inverted level. As in the first embodiment, the switched level is maintained until the timing of the rising edge of the system clock CLK1 after the timing of the next rising edge of the status update timing signal CLK10.

Next, in the case of transition to one of G00 and H00 in (Table 2), that is, the first, second and third line current comparison results HU and HU of the rising edge timing of the state update timing signal CLK10. A case where HV and HW are all at the same level will be described.

As shown in FIG. 4, state update timing signal CLK1
At the rising timing of 0, the first, second, and third RS flip-flops 66, 67, and 68 are all reset, and the output of the second OR circuit 79 becomes L level.
Further, the output of the first AND circuit 80 is also at L level, and the outputs Y3U, Y3V, Y3W of the fourth, fifth, and sixth EX-NOR circuits 63, 64, 65 and the switching command signals PU, PV, PW are at H level. Therefore, in the operation in this case, as shown in the truth table of (Table 3), a signal level completely different from that of the first embodiment is output.

The above is the description of the logic circuit 3 in the current control means 14 of the motor control device according to the second embodiment of the present invention.
5 is a specific operation description. In the present embodiment, the state update timing signal CLK10 is compared with the first embodiment (Table 1) and the second embodiment (Table 3).
HU, H at the timing of the rising edge of
Only when the level of one of the three signals V and HW is different, the signal levels of PU, PV, and PW having the same level as the final transition result of the operation are equal to each other in the second embodiment. The only difference is that the levels of the PU, PV, and PW of the first embodiment are inverted.
When the levels of PU, PV, and PW are the same, the line voltage of each phase of the three-phase motor 1 becomes 0,
Regardless of whether PU, PV, or PW is H, H, H or L, L, L, the next state update timing signal CLK1
Until the timing of the rising edge of 0, there is no change in the line voltage of each phase. Therefore, the second embodiment can control the line current of the three-phase motor 1 completely equivalent to the first embodiment. it can.

As described above, the second embodiment of the present invention does not have a current error amplifier as in the first embodiment, so that the problem relating to the gain adjustment of the current error amplifier is essential. And no gain adjustment is required.

Further, even if the characteristics and specifications of the three-phase motor 1, the line current detecting means 6, the current control means 14, and the main circuit power element group 4 change, the operation is always performed to minimize the line current error. Even if there are manufacturing variations, temperature characteristics, etc., the line current error is always minimized, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs.

The current control means 6 in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second and third comparison means. There is no worry about drifting and it is inexpensive.

Therefore, according to the present invention, there is no need to perform a gain adjustment operation and an offset adjustment operation of the current error amplifier, and it is possible to supply an inexpensive motor control device having excellent current control responsiveness.

In the second embodiment of the present invention, the state N
o. Switching command signals PU, P at the third digit of
(H, H, H) when the state of V and PW is all
, The switching command signal P
In all cases where the states of U, PV and PW are (H,
H, H), and finally, the power elements Q1, Q2, and Q3 provided on the plus side of the main circuit DC power supply are operated so as to be turned on, so that the bootstrap type base as shown in FIG. The power element can be driven by the drive means 38.

The bootstrap type base drive means 38 is different from the first embodiment in that the main circuit switching power element is a PNP transistor (or a P-channel M
OS-FET or P-channel IGBT)
To drive the main circuit switching power element Q4, Q5, or Q6 on the minus side of the main circuit DC power supply when the main circuit switching power element Q1, Q2, or Q3 on the plus side of the main circuit DC power supply is on. Is stored in a capacitor C to drive a main circuit switching power element Q4, Q5, or Q6.

This method is characterized by low loss and easy circuit integration. Therefore, by outputting the switching command signal to the logic circuit 35 based on (Table 3), the main circuit power element group 4 having the above-described bootstrap type base drive means 38 can be applied, and the motor control can be performed. Low loss of the whole device, I
C and miniaturization can be realized.

[0153]

In the first motor control device according to the present invention, the current control means includes a comparing means for comparing the line current command signal with the measured result of the line current, and outputs a switching command signal based on these outputs. And a timing generation means for generating a timing signal for controlling the operation timing of the logic circuit. In other words, since the configuration does not include the current error amplifier, the problem of gain adjustment of the current error amplifier is essential. And no need for gain adjustment.

Furthermore, even if the characteristics and specifications of the electric motor, the line current detecting means, the current control means, and the main circuit power element group change, the operation is always performed to minimize the line current error. Even if there is an error, the line operation is always performed to minimize the line current error, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs.

The current control means in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second and third comparison means. No worries and it is cheap.

Therefore, according to the present invention, it is not necessary to perform a gain adjustment operation and an offset adjustment operation of the current error amplifier, and it is possible to provide an inexpensive motor control device having excellent current control responsiveness.

Also, the power elements provided on the minus side of the main circuit DC power supply are finally turned on.
By configuring the logic circuit so as to output a switching command signal, the six main circuit switching power elements can be NPN transistors (or N-channel MOS-FEs).
(T or N-channel IGBT, etc.) and having a bootstrap-type base drive means. As a result, it is possible to reduce the loss, make the IC, and reduce the size of the entire motor control device. Become.

In the second motor control device according to the present invention, the current control means includes a comparison means for comparing the line current command signal with the line current measurement result, and a logic for outputting a switching command signal based on these outputs. It has a circuit and a timing generating means for generating a timing signal for controlling the operation timing of the logic circuit, and has no current error amplifier. Can be solved and no gain adjustment is required.

Further, even if the characteristics and specifications of the electric motor, the line current detecting means, the current control means, and the main circuit power element group change, the operation is always performed to minimize the line current error. Even if there is an error, the line operation is always performed to minimize the line current error, so that the current control response is excellent, and there is no fear that an oscillation phenomenon occurs.

The current control means in the motor control device of the present invention can be constituted by a simple digital circuit except for the first, second and third comparison means. No worries and it is cheap.

Therefore, according to the present invention, a gain control operation and an offset adjustment operation of the current error amplifier are not required, and a motor control device which is excellent in current control response and inexpensive can be supplied.

Further, by configuring a logic circuit so as to output a switching command signal so that all the power elements provided on the plus side of the main circuit DC power supply are finally turned on, six main circuits are formed. The switching power element is a PNP transistor (or P-channel MOS-FET)
Or a P-channel IGBT or the like and having a bootstrap type base drive means. As a result, it is possible to reduce the loss, make the IC, and reduce the size of the entire motor control device. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a current control unit according to a first embodiment of the present invention in FIG. 7;

FIG. 2 is a configuration diagram of a main circuit power element group according to the first embodiment of the present invention in FIG. 7;

FIG. 3 is a configuration diagram of a logic circuit according to the first embodiment of FIG. 1;

FIG. 4 is a timing chart of timing signal distribution means of the logic circuit of FIG. 1;

FIG. 5 is an explanatory diagram of the operation of FIGS. 6 and 1;

FIG. 6 is a system configuration diagram of a motor control device of the present invention.

FIG. 7 is a diagram showing current control means using a hysteresis comparator.

FIG. 8 is a configuration diagram of a logic circuit according to a second embodiment of the present invention.

FIG. 9 is a configuration diagram of a main circuit power element group according to a second embodiment of the present invention.

FIG. 10 is a system configuration diagram of a conventional general motor control unit.

11 is a configuration diagram of the current control means of FIG.

FIG. 12 is a configuration diagram of the current error amplifier of FIG. 11;

FIG. 13 is an operation explanatory diagram of FIGS. 10 and 11;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 three-phase motor 3 main circuit DC power supply 4 main circuit power element group 6 line current detection means 12 current command generation means 13, 14, 15 current control means 30 first comparison means 31 second comparison means 32 third comparison Means 33, 35 Logic circuit 34 Timing generation means 36 Base drive means 37 Logical inversion means 38 Base drive means 41, 42, 43 Subtraction means 44 First current error amplifier 45 Second current error amplifier 46 Third current error amplifier 47 first comparator 48 second comparator 49 third comparator 50 triangular wave generating means 60 first EX-NOR circuit 61 second EX-NOR circuit 62 third EX-NOR circuit 63 fourth EX-NOR circuit 64 Fifth EX-NOR circuit 65 Sixth EX-NOR circuit 66 First RS flip-flop 67 Second R Flip-flop 68 Third RS flip-flop 69 First D-latch 70 Second D-latch 71 Third D-latch 72 Fourth D-latch 73 Fifth D-latch 74 Sixth D-latch 75 Data decoding means 76 First NOR circuit 77 First OR circuit 78 Timing signal distribution means 79 Second OR circuit 80 First AND circuit Q1 First main circuit switching power element Q2 Second main circuit switching power element Q3 Third Main circuit switching power element Q4 Fourth main circuit switching power element Q5 Fifth main circuit switching power element Q6 Sixth main circuit switching power element

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor ▲ Taka ▼ Kazuyuki Tadashi 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5H007 BB06 CA02 CB02 CB05 CC13 DA05 DB02 DC02 5H576 AA18 BB03 BB10 CC01 DD02 EE15 GG04 HA02 HA03 HA04 HB02 JJ02 JJ09 JJ19 LL22

Claims (2)

[Claims] 1. A line current flowing from each line to a three-phase motor is directly or indirectly measured, and a first line current measurement result, a second line current measurement result, and a third line current measurement result are output. Line current detection means, and line current command generation means for outputting a first line current command, a second line current command, and a third line current command for commanding a line current to flow into the three-phase motor from each line. And, comparing the magnitude relationship between the first line current command and the first line current measurement result, the first line current when the first line current measurement result is greater than the first line current command The first comparison means to make the comparison result large, and to make the first line current comparison result small when the first line current measurement result is smaller than the first line current command, and the second line current And comparing the magnitude relationship between the command and the second line current measurement result. If the second line current measurement result is larger than the second line current comparison result is large, and if the second line current measurement result is smaller than the second line current command, the second line current comparison result The second comparing means for reducing the result, the magnitude relation between the third line current command and the third line current measurement result is compared, and the third line current measurement is more than the third line current command. When the result is large, the third line current comparison result is set to be large, and when the third line current measurement result is smaller than the third line current command, the third line current comparison result is set to be small. Comparing means, a main circuit DC power supply, a first main circuit switching power element connected to a positive terminal of the main circuit DC power supply and supplying a first line current to the three-phase motor, A second main circuit connected to a positive terminal and supplying a second line current to the three-phase motor; A switching power element, a third main circuit switching power element connected to a positive terminal of the main circuit DC power supply and supplying a third line current to the three-phase motor, and a third terminal connected to a minus terminal of the main circuit DC power supply; A fourth main circuit switching power element for supplying a first line current to the three-phase motor, and a fifth main circuit connected to a minus terminal of the main circuit DC power supply for supplying a second line current to the three-phase motor. A circuit switching power element, a sixth main circuit switching power element connected to the minus terminal of the main circuit DC power supply, and supplying a third line current to the three-phase motor, and in parallel with each of the main circuit switching power elements. A main circuit power element group composed of connected reflux diodes and having a three-phase bridge configuration, and the first line current comparison result, the second line current comparison result, and the third A logic circuit that receives a line current comparison result and generates a switching command signal for the first, second, third, fourth, fifth, and sixth main circuit switching power elements, and a periodic state update timing. The logic circuit includes a timing generation unit that provides a first line current comparison result is small, a second line current comparison result is large, and a third line current comparison result is large at an update timing. Command the second, third, and fourth main circuit switching power elements to be in the off state, and instruct the first, fifth, and sixth main circuit switching power elements to be in the on state, and then perform the third If the second line current comparison result becomes smaller before the line current comparison result becomes smaller, the fifth main current from that time until the third line current comparison result becomes smaller is obtained. Command the off state to the circuit switching power element Command the ON state to the circuit switching power element, and turn off the first, second, and third main circuit switching power elements from the time when the third line current comparison result becomes small to the next update timing. And command the ON state to the fourth, fifth, and sixth main circuit switching power elements, and determine that the third line current comparison result is small before the second line current comparison result is small. When the second line current comparison result becomes smaller from that point in time, the sixth main circuit switching power element is commanded to be in the off state, and the third main circuit switching power element is in the on state. Command from the time when the second line current comparison result becomes small to the next update timing, command the off state to the third main circuit switching power element, the fourth, Fifth and sixth main circuit switching power elements When the first line current comparison result is large and the second line current comparison result is small and the third line current comparison result is large at the update timing, one,
The third and fifth main circuit switching power elements are commanded to be in an off state, the second, fourth, and sixth main circuit switching power elements are commanded to be in an on state. If the third line current comparison result becomes smaller before the first line current comparison result becomes smaller, the sixth main circuit switching power element is turned off from that time until the first line current comparison result becomes smaller. Command the state and command the ON state to the third main circuit switching power element, the first, the second, from the time when the first line current comparison result is small until the next update timing
Before the third main circuit switching power element is commanded to be in the off state, the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state, and before the third line current comparison result becomes small. When the first line current comparison result is small, the fourth main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes small. Command the ON state to the first main circuit switching power element, the first, second, third main circuit switching power between the time when the third line current comparison result becomes small and the next update timing The off-state command is issued to the element, the fourth, fifth, and sixth main circuit switching power elements are configured to command the on-state, and the first line current comparison result is large and second at the update timing. Line current comparison results are large and the third line current If the comparison result is small, the first,
The second and sixth main circuit switching power elements are commanded to be in an off state, the third, fourth, and fifth main circuit switching power elements are commanded to be in an on state. If the first line current comparison result becomes smaller before the value becomes smaller, the fourth main circuit switching power element is turned off from that time until the second line current comparison result becomes smaller. Command the state and command the ON state to the first main circuit switching power element, the first, second, from the time when the second line current comparison result becomes small until the next update timing
Command the off state to the third main circuit switching power element, and command the on state to the fourth, fifth, and sixth main circuit switching power elements, and before the first line current comparison result becomes small. If the second line current comparison result is small, the fifth main circuit switching power element is commanded to be in the off state from that time until the first line current comparison result becomes small. Command the ON state to the second main circuit switching power element, the first, second, third main circuit switching power between the time when the first line current comparison result becomes small and the next update timing The off-state command is issued to the element, the fourth, fifth, and sixth main circuit switching power elements are configured to command the on-state, and the first line current comparison result is large and second at the update timing. Line current comparison result is small and the third line current If the comparison result is small, the first,
The fifth and sixth main circuit switching power elements are commanded to be in an off state, the second, third, and fourth main circuit switching power elements are to be commanded to be in an on state. If the second line current comparison result becomes large before becoming large, the second main circuit switching power element is turned off from that time until the third line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, the first, second, from the time when the third line current comparison result becomes large to the next update timing
The third main circuit switching power element is commanded to be in the off state, the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state, and before the second line current comparison result becomes large. When the third line current comparison result becomes large, the third main circuit switching power element is commanded to be in an off state from that time until the second line current comparison result becomes large. Command the ON state to the sixth main circuit switching power element, the first, second, third main circuit switching power between the time when the second line current comparison result becomes large and the next update timing The off-state command to the element, the fourth, fifth, and sixth main circuit switching power element is configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison results are large and the third line current If the comparison result is small, the second,
The fourth and sixth main circuit switching power elements are commanded to be in an off state, the first, third, and fifth main circuit switching power elements are commanded to be in an on state, and then the first line current comparison result is obtained. If the third line current comparison result becomes large before it becomes large, the third main circuit switching power element is turned off from that time until the first line current comparison result becomes large. Command the state and command the ON state to the sixth main circuit switching power element, from the time when the first line current comparison result becomes large to the next update timing, the first, second,
The third main circuit switching power element is commanded to be in the off state, the fourth, fifth, and sixth main circuit switching power elements are commanded to be in the on state, and before the third line current comparison result becomes large. When the first line current comparison result becomes large, the first main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes large. The fourth main circuit switching power element is commanded to be in an ON state, and the first, second, and third main circuit switching powers are supplied between the time when the third line current comparison result becomes large and the next update timing. The off-state command to the element, the fourth, fifth, and sixth main circuit switching power element is configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison result is small and the third line current If the comparison result is large, the third,
The fourth and fifth main circuit switching power elements are commanded to be in the off state, the first, second, and sixth main circuit switching power elements are to be commanded to be in the on state, and then the first line current comparison result is obtained. If the second line current comparison result becomes large before the first line current comparison result becomes large, the second main circuit switching power element is turned on from that time until the first line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, from the time when the first line current comparison result becomes large to the next update timing, the first, second,
Command the off state to the third main circuit switching power element, and command the on state to the fourth, fifth, and sixth main circuit switching power elements, and before the second line current comparison result becomes large. When the first line current comparison result becomes large, the first main circuit switching power element is commanded to be in an off state from that time until the second line current comparison result becomes large. Command the ON state to the fourth main circuit switching power element, the first, second, third main circuit switching power between the time when the second line current comparison result becomes large and the next update timing A motor control device configured to instruct an element to be in an off state and to instruct a fourth, fifth, and sixth main circuit switching power elements to be in an on state. 2. A line current flowing from each line to a three-phase motor is measured directly or indirectly to output a first line current measurement result, a second line current measurement result, and a third line current measurement result. Line current detection means, and line current command generation means for outputting a first line current command, a second line current command, and a third line current command for commanding a line current to flow into the three-phase motor from each line. And, comparing the magnitude relationship between the first line current command and the first line current measurement result, the first line current when the first line current measurement result is greater than the first line current command The first comparison means to make the comparison result large, and to make the first line current comparison result small when the first line current measurement result is smaller than the first line current command, and the second line current And comparing the magnitude relationship between the command and the second line current measurement result. If the second line current measurement result is larger than the second line current comparison result is large, and if the second line current measurement result is smaller than the second line current command, the second line current comparison result The second comparing means for reducing the result, the magnitude relation between the third line current command and the third line current measurement result is compared, and the third line current measurement is more than the third line current command. When the result is large, the third line current comparison result is set to be large, and when the third line current measurement result is smaller than the third line current command, the third line current comparison result is set to be small. Comparing means, a main circuit DC power supply, a first main circuit switching power element connected to a positive terminal of the main circuit DC power supply and supplying a first line current to the three-phase motor, A second main circuit connected to a positive terminal and supplying a second line current to the three-phase motor; A switching power element, a third main circuit switching power element connected to a positive terminal of the main circuit DC power supply and supplying a third line current to the three-phase motor, and a third terminal connected to a minus terminal of the main circuit DC power supply; A fourth main circuit switching power element for supplying a first line current to the three-phase motor, and a fifth main circuit connected to a minus terminal of the main circuit DC power supply for supplying a second line current to the three-phase motor. A circuit switching power element, a sixth main circuit switching power element connected to the minus terminal of the main circuit DC power supply, and supplying a third line current to the three-phase motor, and in parallel with each of the main circuit switching power elements. A main circuit power element group composed of connected reflux diodes and having a three-phase bridge configuration, and the first line current comparison result, the second line current comparison result, and the third A logic circuit that receives a line current comparison result and generates a switching command signal for the first, second, third, fourth, fifth, and sixth main circuit switching power elements, and a periodic state update timing. The logic circuit includes a timing generation unit that provides a first line current comparison result is small, a second line current comparison result is large, and a third line current comparison result is large at an update timing. Command the second, third, and fourth main circuit switching power elements to be in the off state, and instruct the first, fifth, and sixth main circuit switching power elements to be in the on state, and then perform the third If the second line current comparison result becomes smaller before the line current comparison result becomes smaller, the fifth main current from that time until the third line current comparison result becomes smaller is obtained. Command the off state to the circuit switching power element Command the ON state to the circuit switching power element, and turn off the fourth, fifth, and sixth main circuit switching power elements from the time when the third line current comparison result becomes small to the next update timing. And instructs the first, second, and third main circuit switching power elements to be in the ON state, and the third line current comparison result is small before the second line current comparison result is small. When the second line current comparison result becomes smaller from that point in time, the sixth main circuit switching power element is commanded to be in the off state, and the third main circuit switching power element is in the on state. Command the off state to the fourth, fifth, sixth main circuit switching power element from the time when the second line current comparison result becomes small to the next update timing, the first, Second and third main circuit switching power elements When the first line current comparison result is large and the second line current comparison result is small and the third line current comparison result is large at the update timing, one,
The third and fifth main circuit switching power elements are commanded to be in an off state, the second, fourth, and sixth main circuit switching power elements are commanded to be in an on state. If the third line current comparison result becomes smaller before the first line current comparison result becomes smaller, the sixth main circuit switching power element is turned off from that time until the first line current comparison result becomes smaller. Command the state and command the ON state to the third main circuit switching power element, from the time when the third line current comparison result becomes small to the next update timing, the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the third line current comparison result becomes small. When the first line current comparison result is small, the fourth main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes small. Command the ON state to the first main circuit switching power element, the fourth, fifth, sixth main circuit switching power from the time when the third line current comparison result becomes small to the next update timing Element to command the off state, the first, second, and third main circuit switching power element to be configured to command the on state, and the update timing, the first line current comparison result is large and the second Line current comparison results are large and the third line current If the comparison result is small, the first,
The second and sixth main circuit switching power elements are commanded to be in an off state, the third, fourth, and fifth main circuit switching power elements are commanded to be in an on state. If the first line current comparison result becomes smaller before the value becomes smaller, the fourth main circuit switching power element is turned off from that time until the second line current comparison result becomes smaller. Command the state and command the ON state to the first main circuit switching power element, the fourth, fifth, from the time when the second line current comparison result becomes small until the next update timing
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the first line current comparison result becomes small. If the second line current comparison result is small, the fifth main circuit switching power element is commanded to be in the off state from that time until the first line current comparison result becomes small. Command the ON state to the second main circuit switching power element, the fourth, fifth, sixth main circuit switching power between the time when the first line current comparison result becomes small and the next update timing Element to command the off state, the first, second, and third main circuit switching power element to be configured to command the on state, and the update timing, the first line current comparison result is large and the second Line current comparison result is small and the third line current If the comparison result is small, the first,
The fifth and sixth main circuit switching power elements are commanded to be in an off state, the second, third, and fourth main circuit switching power elements are to be commanded to be in an on state. If the second line current comparison result becomes large before becoming large, the second main circuit switching power element is turned off from that time until the third line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, the period from the time when the second line current comparison result becomes large to the next update timing is the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the second line current comparison result becomes large. When the third line current comparison result becomes large, the third main circuit switching power element is commanded to be in an off state from that time until the second line current comparison result becomes large. Command the ON state to the sixth main circuit switching power element, the fourth, fifth, sixth main circuit switching power from the time when the second line current comparison result becomes large to the next update timing The off-state command is issued to the element, the first, second, and third main circuit switching power devices are configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison results are large and the third line current If the comparison result is small, the second,
The fourth and sixth main circuit switching power elements are commanded to be in an off state, the first, third, and fifth main circuit switching power elements are commanded to be in an on state, and then the first line current comparison result is obtained. If the third line current comparison result becomes large before it becomes large, the third main circuit switching power element is turned off from that time until the first line current comparison result becomes large. Command the state and command the ON state to the sixth main circuit switching power element, from the time when the first line current comparison result becomes large to the next update timing, the fourth, fifth,
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the third line current comparison result becomes large. When the first line current comparison result becomes large, the first main circuit switching power element is commanded to be in an off state from that time until the third line current comparison result becomes large. Command the ON state to the fourth main circuit switching power element, and execute the fourth, fifth, and sixth main circuit switching power between the time when the third line current comparison result becomes large and the next update timing. The off-state command is issued to the element, the first, second, and third main circuit switching power devices are configured to instruct the on-state, and the first line current comparison result is small and second at the update timing. Line current comparison result is small and the third line current If the comparison result is large, the third,
The fourth and fifth main circuit switching power elements are commanded to be in an off state, the first, second, and sixth main circuit switching power elements are commanded to be in an on state. If the second line current comparison result becomes large before becoming large, the second main circuit switching power element is turned off from that time until the first line current comparison result becomes large. Command the state and command the ON state to the fifth main circuit switching power element, the fourth line, the fifth, from the time when the first line current comparison result becomes large to the next update timing
Command the off state to the sixth main circuit switching power element, command the on state to the first, second, and third main circuit switching power elements, and before the second line current comparison result becomes large. When the first line current comparison result becomes large, the off state is instructed to the first main circuit switching power element from that time until the second line current comparison result becomes large. Command the ON state to the fourth main circuit switching power element, the fourth, fifth, sixth main circuit switching power between the time when the second line current comparison result becomes large and the next update timing A motor control device configured to instruct an element to be in an off state and to instruct a first, second, and third main circuit switching power elements to be in an on state.