JP2000134233A - Data transfer controller and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer controller and electronic equipment capable of reducing the overheads of processings and transferring data at a high speed with the hardware of a small scale. SOLUTION: In this data transfer controller of an IEEE1394 standard, between a link core and a CPU, a built-in RAM for storing packets capable of random access is provided other than a FIFO. The storage area of the RAM is separated into a header area, a data area and the work area of the CPU and the header area and the data area are separated into areas for reception and for transmission. By using TAG, the header of a reception packet is written in the header area and the data are written in the data area. The data area is separated into the areas for isochronous transfer and for asynchronous transfer. A pointer for variably controlling the size of the respective areas of the RAM is prepared and the size of the respective areas is dynamically and variably controlled even after supplying power. The respective areas are turned to a ring buffer structure. The size of the area for storing the header and data of one packet is fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and an electronic device including the same.

[0002]

BACKGROUND OF THE INVENTION In recent years, I
An interface standard called EEE1394 has been spotlighted. This IEEE 1394 standardizes a high-speed serial bus interface that can support next-generation multimedia. This IEEE 1394
According to this, data requiring real-time properties such as moving images can be handled. In addition, not only computer peripherals such as printers, scanners, CD-R drives, and hard disk drives, but also home appliances such as video cameras, VTRs, and TVs can be connected to the IEEE 1394 bus. For this reason, it is expected that digitalization of electronic devices can be drastically promoted.

For an overview of such IEEE 1394, for example, see “Overview of IEEE 1394 High Performance Serial Bus” (Interface Ap.
r. 1996, pp. 1-10), "Peripheral Bus Standards for PCs" (Interface Jan. 1997, pp. 106-116), "IEEE 1394-1995".
(FireWire) Real-time Transfer Mode and Multimedia-Compatible Protocol "(Interface J
an. 1997, pp. 136-146). Further, as a data transfer control device conforming to IEEE 1394, TS Instruments manufactured by Texas Instruments, Inc.
B12LV31 and the like are known.

However, it has been found that the data transfer control device conforming to IEEE 1394 has the following problems.

That is, according to the current IEEE 1394 standard, a maximum transfer rate of 400 Mbps can be realized. However, in reality, due to the presence of processing overhead, the actual transfer speed of the entire system is considerably lower. In other words, the firmware or application software operating on the CPU takes a lot of time to prepare transmission data or fetch reception data, and even if the transfer speed on the bus is high, As a result, high-speed data transfer cannot be realized.

[0006] In particular, a CPU incorporated in a peripheral device includes:
The processing capacity is lower than that of a CPU incorporated in a host system such as a personal computer. For this reason, the problem of processing overhead of firmware and application software becomes very serious. Therefore, a technique that can effectively solve such an overhead problem is desired.

The present invention has been made in view of the above technical problems, and an object of the present invention is to reduce the processing overhead of firmware and application software and to achieve high-speed processing with small-scale hardware. An object of the present invention is to provide a data transfer control device capable of realizing accurate data transfer and an electronic device using the same.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a data transfer control device for transferring data between a plurality of nodes connected to a bus, and a packet transfer between the nodes. Means for providing a service for storing, a randomly accessible storage means for storing a packet, a writing means for writing a packet transferred from each node via the link means to the storage means, And reading means for reading out the packet written in said storage means and passing it to said link means.

According to the present invention, the packet transferred from each node is written to the storage means which can be randomly accessed by the writing means. The packet written in the storage means by the upper layer such as firmware or application software is read by the reading means and passed to the link means. Then, it is transferred to each node. As described above, in the present invention, the randomly accessible storage means for storing packets is interposed between the link means and the upper layer. By doing so, it is possible to store the packet in a desired storage area of the storage unit without depending on the reception order or the transmission order of the packet. This makes it possible to store the packets separately in a plurality of areas of the storage means.

Further, the present invention is characterized in that the storage means is separated into a control information area for storing control information of the packet and a data area for storing data of the packet. By doing so, the processing load on the upper layers such as firmware and application software can be reduced, and the actual transfer speed of the entire system can be improved. Further, the process of reading a packet from the storage unit and the process of writing to the storage unit can be simplified.

Further, the present invention is characterized in that the storage means is separated into an area for storing packets and a work area for the central processing unit. By doing so, it is possible to reduce the storage capacity of the local memory of the central processing unit and to eliminate the need for the local memory itself.

Further, the present invention is characterized in that the control information area of the storage means is divided into a reception control information area and a transmission control information area. By doing so, it is possible to continuously read control information from the reception control information area and to continuously write control information to the transmission control information area, thereby simplifying the processing and reducing the processing load. Can be achieved.

Further, the present invention is characterized in that it includes a packet separating means for writing control information of a packet in the control information area and writing data of the packet in the data area. By doing so, the control information and data of the packet are automatically written into the control information area and the data area, respectively, and the overhead of the upper layer processing such as firmware can be reduced.

According to the present invention, the link means generates tag information for discriminating at least control information and data of the packet, and associates the generated tag information with the packet. And writing packet control information to the control information area and writing packet data to the data area based on the tag information associated with. This makes it possible to store the control information of the packet in the control information area and the data in the data area with a simple hardware configuration.

[0015] The present invention is characterized in that the data area of the storage means is divided into a reception data area and a transmission data area. By doing this,
It is possible to continuously read the received data from the data area for reception and write the transmission data continuously to the data area for transmission, thereby reducing the overhead of the upper layer processing.

Further, the present invention is characterized in that the data area of the storage means is divided into an isochronous transfer data area and an asynchronous transfer data area. In this way, even when an isochronous packet is transferred after an asynchronous packet, the isochronous packet can be processed first. This makes it possible to maintain real-time processing required for isochronous transfer.

Further, according to the present invention, the data area of the storage means includes a data area for asynchronous transfer, and the data area for asynchronous transfer is divided into a plurality of areas including first and second data areas for asynchronous transfer. It is characterized by having been done.
This makes it possible to separately store data for different purposes in each of the plurality of areas of the asynchronous transfer data area. That is, for example, control data such as command data and status data is stored in the first asynchronous transfer data area, and data output, stored, captured, etc. by the application is stored in the second asynchronous transfer data area. It can be stored. Therefore, for example, data output, stored, fetched, and the like by the application can be continuously stored in, for example, the second asynchronous transfer data area, and the processing load on the upper layer can be reduced.

Further, in the present invention, the data area of the storage means is divided into an isochronous transfer data area and a first asynchronous transfer data area, and the isochronous transfer data area is a second asynchronous transfer data area. It is characterized by being used as. In this way, the isochronous transfer data area can be used as the second asynchronous transfer data area when the application does not perform isochronous transfer. Then, data for different purposes can be separately stored in the first and second asynchronous transfer data areas. As a result,
The processing load on the upper layer can be reduced while effectively using the limited resources.

Further, the present invention includes means for dividing the data area of the storage means into a plurality of areas and writing packet data to any of the plurality of separated areas based on control information of the packet. It is characterized by. In this way, data for different purposes can be separately stored in a plurality of separated areas. As a result, the processing load on the upper layer can be reduced.

Further, the present invention is characterized in that when the storage means is divided into a plurality of areas, means for variably controlling the size of each area is included. In this way, it is possible to realize the optimal area division according to the application, and to effectively use limited resources.

Further, the present invention is characterized in that the size of each area is dynamically variably controlled even after power is turned on. This makes it possible to effectively use limited resources even when reception processing and transmission processing are mixed.

According to the present invention, when the storage means is divided into a plurality of areas, at least one of packet control information and data is stored from one boundary of the separated area to the other boundary. When the other boundary is reached, the process returns to one boundary and stores at least one of the control information and the data of the packet.
By doing so, it becomes possible to make the storage means that can be randomly accessed have a FIFO function. When the other boundary is reached, control information and data of a packet can be stored from one boundary, so that limited resources can be effectively used.

Further, the present invention is characterized in that the size of an area for storing at least one of control information and data of one packet is fixed. By doing so, handling of packets by firmware and the like is simplified, and the processing load on firmware and the like can be reduced.

In the present invention, a receiving FIFO and a transmitting FIFO provided between the link means and the storage means are provided.
And an IFO.

Further, in the present invention, it is desirable to perform data transfer conforming to the IEEE 1394 standard.

An electronic apparatus according to the present invention includes any one of the above data transfer control devices, a device for performing given processing on data received from another node via the data transfer control device and a bus, And a device for outputting or storing the processed data. Further, the electronic device according to the present invention, any one of the data transfer control device described above, a device that performs a given process on data to be transmitted to another node via the data transfer control device and a bus,
And a device for taking in data to be processed.

According to the present invention, the processing for outputting and storing data transferred from another node in an electronic device and the processing for transferring data fetched in the electronic device to another node are accelerated. It becomes possible.
Further, according to the present invention, the data transfer control device can be reduced in size, and the processing load of firmware and the like for controlling data transfer can be reduced, so that the cost and size of the electronic device can be reduced. become.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. IEEE 1394 First, an outline of IEEE 1394 will be briefly described.

1.1 Data transfer rate, connection topology IEEE 1394 (IEEE 1394-1995, IE
EE1394. A) enables high-speed data transfer of 100 to 400 Mbps (IEEE 1394.
800 to 3200 Mbps for B). It is also allowed to connect nodes having different transfer speeds to the bus.

Each node is connected in a tree shape.
A maximum of 63 nodes can be connected to one bus. If a bus bridge is used, about 64000 nodes can be connected.

When the power is turned on or a device is inserted or removed halfway, a bus reset occurs, and all information on the connection topology is cleared. After the bus reset, tree identification (determination of a root node) and self-identification are performed. Thereafter, management nodes such as an isochronous resource manager, a cycle master, and a bus manager are determined. Then, normal packet transfer is started.

1.2 Transfer Method In IEEE 1394, as a packet transfer method, asynchronous transfer suitable for data transfer requiring reliability,
Isochronous transfer suitable for transfer of data such as moving images and sounds that require real-time properties is prepared.

FIG. 1A shows an example of an asynchronous subaction. One sub-action consists of arbitration, packet transfer, and acknowledgment. That is, prior to data transfer, arbitration regarding the right to use the bus is first performed. Then, the packet is transferred from the source (transfer source) node to the destination (destination) node. The header of this packet has a source ID and a destination I
D is included. The destination node reads this destination ID and determines whether or not the packet is addressed to itself. Upon receiving the packet, the destination node returns an acknowledgment (ACK) packet to the source node.

There is an acknowledge gap between packet transfer and ACK. In addition, there is a subaction gap between one subaction and the next subaction. Then, the arbitration of the next subaction cannot be started unless a certain bus idle time corresponding to the subaction gap has elapsed. This avoids collision between the sub-actions.

FIG. 1B shows an example of the isochronous subaction. Since the isochronous transfer is performed by broadcast (transfer to all nodes connected to the bus), ACK is not returned when a packet is received. In the isochronous transfer, packet transfer is performed using a channel number instead of a node ID. Note that there is an isochronous gap between the sub-actions.

FIG. 1C shows the state of the bus during data transfer. The isochronous transfer starts when the cycle master generates a cycle start packet at regular intervals. Thus, 125 μm per channel
At least one packet can be transferred every s. As a result, it is possible to transfer data such as moving images and sounds that require real-time properties.

Asynchronous transfer is performed between isochronous transfers. That is, the isochronous transfer has a higher priority than the asynchronous transfer. This is shown in FIG.
As shown in (1), this is realized by making the time of the isochronous gap shorter than the time of the sub-action gap of asynchronous transfer.

1.3 Tree Identification Tree identification is performed after a bus reset. The parent-child relationship between nodes and the root node are determined by the tree identification.

First, a leaf node (a node connected to only one node) sends a parent notify to an adjacent node. For example, when the nodes A, B, C, D, and E are connected as shown in FIG. 2A, a parent notify (PN) is transmitted from the node A to the node B and from the nodes D and E to the node C. Is sent.

The node receiving the parent notify recognizes the source node as its own child. Then, it sends the child notify to that node. For example, in FIG. 2A, child notify (C) is performed from node B to node A and from node C to nodes D and E.
N) is sent. Thus, the parent-child relationship between the nodes B and A, between the nodes C and D, and between the nodes C and E are determined.

The parent-child relationship between nodes B and C is determined by which sent the parent notify first. For example, as shown in FIG. 2B, when the node C sends a parent notify first, the node B becomes a parent and the node C becomes a child.

A node in which all the nodes to which the ports are connected are their children is the root. In FIG. 2B, the node B is the root. In IEEE 1394, there is a possibility that all nodes become roots.

1.4 Self-identification After tree identification, self-identification is performed. In the self-identification, self-ID packets are sequentially transferred from a node farthest from the root node in the connection topology.

More specifically, for example, in FIG. 3, first, port 1 of the root node B (a port with a small number)
, A self-ID packet (self-identification packet) is broadcast to all nodes.

Next, the node C connected to the port 2 (the port with the larger number) of the root node B is selected, and the node D connected to the port 1 (the port with the smaller number) of the node C transmits the self ID packet. Broadcast. Next, port 2 of node C (a port with a large number)
, Broadcasts a self-ID packet, and then node C broadcasts. Finally, the root node B broadcasts a self-ID packet, and the self-identification is completed.

The self ID packet contains the ID of each node. The number of self-ID packets received from another node at the time of broadcasting is the ID of each node. For example, in FIG. 3, at the time when the node A broadcasts, since no node has issued a self ID packet, the ID of the node A becomes 0.
The node A broadcasts the ID = 0 by including it in the self ID packet. At the time when the node D broadcasts, only the node A issues the self ID packet. Therefore, the ID of the node D becomes 1. Similarly, the IDs of nodes E, C, and B are 2,
3 and 4.

FIG. 4A shows the format of the self ID packet. As shown in the figure, the self ID packet includes basic information of each node. Specifically, the ID (PHY_ID) of each node, whether the link layer is active (L), gap count (gap_cnt), transfer speed (sp), and whether the node has the ability to become an isochronous resource manager (C) , Power state (pwr),
Information about the port status (p0, p1, p2) and the like is included.

FIG. 4B shows a self ID packet # 1 used when the number of ports of the node is four or more.
The format of # 2 and # 3 is shown. 4 to 11 ports
When the number of self ID packets # 0 (# 4 (A)) and # 1 is 12 to 19, the number of self ID packets # 0, # 1, and # 2 is 20 to 27. Means that self ID packets # 0, # 1, # 2 and # 3 are used.

FIGS. 4C and 4D show the self ID.
Similarly to the packet, the format of a link-on packet, which is a physical layer packet (PHY packet), and a PHY configuration packet are shown.

1.5 Isochronous Resource Manager The isochronous resource manager (IRM) has the following management functions.

First, various resources required for isochronous transfer are provided. For example, it provides a channel number register and a bandwidth register. Second, it provides a register indicating the ID of the bus manager. Third, when there is no bus manager, it has a role to be a simple bus manager.

A node that has the ability to become an IRM (has the ability to manage isochronous resources) and that is in an active state (the link layer is active) must qualify to become an IRM. The node closest to the root (with the highest ID) becomes the IRM. More specifically, in the self-ID packet of FIG. 4A, a C (CONTENDER) bit indicating whether or not it has an IRM capability and an L (LINK_ACTIV) indicating whether or not the link layer is active.
E) The node closest to the root (the node with the largest PHY_ID) among the nodes whose bits are both 1
Becomes IRM. For example, when the C bit and the L bit of the self ID packet of the root node are 1, the root node becomes the IRM.

1.6 Cycle Master and Bus Manager The cycle master has a role of transmitting the cycle start packet shown in FIG. 1C, and the root node becomes the cycle master.

The bus manager performs tasks such as creation of a topology map (connection state of each node), creation of a speed map, bus power management, determination of a cycle master, and optimization of a gap count.

1.7 Protocol Configuration The protocol configuration (layer structure) of IEEE 1394 will be described with reference to FIG.

The IEEE 1394 protocol includes a physical layer, a link layer, and a transaction layer.
The serial bus management monitors and controls the physical layer, link layer, and transaction layer, and provides various functions for controlling nodes and managing bus resources.

The physical layer converts logical symbols used by the link layer into electric signals, performs bus arbitration, and defines a physical interface of the bus.

The link layer provides addressing, data checking, data framing, cycle control, and the like.

The transaction layer includes read, write,
Define a protocol for performing transactions such as locking.

The physical layer and the link layer are usually realized by hardware such as a data transfer control device (interface chip). The transaction layer is C
It is realized by firmware or hardware operating on the PU.

[0062] 2. Next, the overall configuration of the present embodiment will be described with reference to FIG.

In FIG. 6, the PHY interface 1
Reference numeral 0 denotes a circuit that interfaces with a PHY chip that implements a physical layer protocol.

The link core 20 (link means) is a circuit that implements a part of a link layer protocol or a transaction layer protocol, and provides various services for packet transfer between nodes. The register 22 is a register for implementing these protocols and controlling the link core 20.

The FIFO (ATF) 30 and the FIFO (IT
F) 32 and FIFO (RF) 34 are FIFOs for asynchronous transmission, isochronous transmission, and reception, respectively.
For example, it is configured by hardware such as a register and a semiconductor memory. In the present embodiment, these FIFO3
The number of stages 0, 32 and 34 is very small. For example, one F
The number of IFO stages is preferably three or less, and more preferably two or less.

The DMACs 40, 42, and 44 each have an AT
DMA controller for F, ITF and RF. By using these DMACs 40, 42, and 44, the CPU
66 and the link core 2 without intervention
Data transfer to / from 0 becomes possible. The register 46 is a register for controlling the DMACs 40, 42, 44 and the like.

The port interface 50 is a circuit for interfacing with a device in the application layer (for example, a device for performing a printing process of a printer).
In the present embodiment, for example, 8-bit data transfer is enabled using the port interface 50.

The FIFO (PF) 52 is a FIFO for transferring data to and from an application layer device.
And the DMAC 54 is a DMA controller for the PF. The register 56 includes the port interface 50
And a register for controlling the DMAC 54.

The CPU interface 60 is a circuit for interfacing with the CPU 66 that controls the data transfer control device. CPU interface 6
0 indicates an address decoder 62, a data synchronization circuit 63,
An interrupt controller 64 is included. Clock control circuit 6
Reference numeral 8 denotes a clock for controlling the clock used in the present embodiment, to which the SCLK sent from the PHY chip and the HCLK as the master clock are input.

The buffer manager 70 is a circuit for managing an interface with the RAM 80. The buffer manager 70 includes a register 72 for controlling the buffer manager, an arbitration circuit 74 for arbitrating bus connection to the RAM 80, and a sequencer 76 for generating various control signals.

The RAM 80 functions as a randomly accessible packet storage means, and its function is realized by, for example, an SRAM, a DRAM, or the like. In the present embodiment, as shown in FIG.
0 is separated into a header area (control information area in a broad sense) and a data area. The header (control information in a broad sense) of the packet is stored in the header area of FIG. 7, and the data of the packet is stored in the data area.

In this embodiment, the RAM 80 is built in the data transfer control device. However, a part of the RAM 80 can be provided externally.

The bus 90 (or buses 92 and 94) is connected to the application (first bus). A bus 96 (or bus 98) is for controlling the data transfer control device, and is a device (for example, CP) for controlling the data transfer control device.
U) (second bus). Bus 1
00 (or buses 102, 104, 105, 106, 1
07, 108, and 109) are electrically connected to a physical layer device (for example, a PHY chip).
Bus). The bus 110 is electrically connected to a random access memory (RAM), which is a storage means (fourth bus).

The arbitration circuit 74 of the buffer manager 70
Are DMAC40, DMAC42, DMAC44, CP
Arbitration of bus access requests from the U interface 60 and the DMAC 54 is performed. Then, based on the arbitration result, a data path is established between any one of the buses 105, 107, 109, 98, and 94 and the bus 110 of the RAM 80 (first, second, and third). A data path is established between any of the buses and the fourth bus).

One feature of the present embodiment is that a random access is possible, a RAM 80 for storing packets is provided, and buses 90, 96, 100 separated from each other are provided.
And an arbitration circuit 74 for connecting these buses to the bus 110 of the RAM 80.

For example, FIG. 8 shows an example of a data transfer control device having a configuration different from that of the present embodiment. In this data transfer control device, the link core 902 is connected to the PHY chip via the PHY interface 900 and the bus 922. Further, the link core 902 includes FIFOs 904, 90
6, 908, CPU interface 910, bus 92
0 is connected to the CPU 912. And CPU
912 is connected via a bus 924 to a RAM 914 which is a memory local to the CPU.

The FIFOs 904, 906, 908
Unlike the FIFOs 30, 32, and 34 in FIG. 6, the number of stages is very large (for example, one FIFO has about 16 stages).

A data transfer method using the data transfer control device having the configuration shown in FIG. 8 will be described with reference to FIG. A received packet transmitted from another node via the PHY chip 930 is received by the CPU 912 via the bus 922, the data transfer control device 932, and the bus 920. Then, the CPU 912 writes the received packet to the RAM 914 via the bus 924. Then, the CPU 912 processes the received packet so that it can be used by the application layer, and transfers the received packet to the device 934 of the application layer via the bus 926.

On the other hand, the device 93 of the application layer
When transferring the data from No. 4, the CPU 912
This data is written to the RAM 914. And RAM
By adding a header to the data of IEEE 914, IEEE13
Generate a packet conforming to H.94. Then, the generated packet is transmitted to another node via the data transfer control device 932, the PHY chip 930, and the like.

However, according to such a data transfer method, the processing load on the CPU 912 becomes very heavy.
Therefore, even if the transfer speed of the serial bus connecting the nodes is increased, the actual transfer speed of the entire system is reduced due to the processing overhead of the CPU 912, and high-speed data transfer cannot be realized after all.

As one method for solving such a problem, as shown in FIG. 10, data transfer between the data transfer control device 932 and the RAM 914, and data transfer between the RAM 914 and the device 934 of the application layer are performed. A method of realizing data transfer by hardware DMA is also conceivable.

However, in this method, the CPU bus 928 is used for data transfer between the data transfer control device 932 and the RAM 914, data transfer between the RAM 914 and the CPU 912, and data transfer between the RAM 914 and the application layer device 934. Will be. Therefore, in order to increase the speed of data transfer in the entire system, a high-speed bus such as a PCI bus must be used as the CPU bus 928, which increases the cost of electronic equipment using the data transfer control device. Invite.

On the other hand, in this embodiment, as shown in FIG. 11, a bus 90 between the data transfer control device 120 and the application layer device 124, a CPU bus 96
And the bus 1 between the data transfer control device 120 and the RAM 80
10 are separated from each other. Therefore, the CPU bus 9
6 can be used only for controlling data transfer. Further, the bus 90 is occupied by the data transfer control device 120,
Data transfer between the application layer devices 124 can be performed. For example, when the electronic device in which the data transfer control device 120 is incorporated is a printer, the print data can be transferred while occupying the bus 90. As a result, the processing load on the CPU 66 can be reduced,
The actual transfer speed of the entire system can be increased. In addition, an inexpensive CPU 66 can be used,
The need to use a high-speed bus as the U bus 96 is eliminated. Therefore, the cost and the size of the electronic device can be reduced.

3. Storing Packets in Packet Storage RAM 3.1 Features of the Present Embodiment In the comparative example of FIG. 8, as shown in FIG. 12A, between the link core 902 and the CPU 912, a transmission IF
O904 and 906 and a receiving FIFO 908 are provided.

That is, received packets sent from other nodes are sequentially input to the FIFO 908 via the link core 902. The CPU 912 (firmware or application software running on the CPU)
Receive packets in the order input to FIFO 908
Read sequentially from FO908.

The CPU 912 sequentially inputs transmission packets to be transferred to the FIFOs 904 and 906. The transmission packets are sequentially transferred to other nodes via the link core 902 in the order input to the FIFOs 904 and 906.

On the other hand, in the present embodiment, FIG.
As shown in (B), a link core 20 for providing various services for packet transfer between nodes,
6, an RA functioning as a random access packet storage means in addition to the FIFOs 30, 32, and 34
M80 is interposed.

That is, a received packet transmitted from another node via the link core 20 is stored in the FIFO 34, and then stored in the DMAC 44 (writing means).
Written to M80. Then, the CPU 66 reads the received packet from the random accessible RAM 80.

Further, the transmission packet to be transferred is written in the RAM 80 by the CPU 66 or the like. The written transmission packet is transmitted to the DMACs 40 and 42.
(Reading means) and read out by the FIFOs 30,
2. The data is transferred to another node via the link core 20.

In FIG. 12A, the CPU 912 must receive the received packets from the FIFO 908 in the order of reception, and the FIFOs 904, 90 in the order of transmission.
6 must store the transmission packet. On the other hand, in the present embodiment in which the RAM 80 that can be randomly accessed is interposed between the link core 20 and the CPU 66,
A received packet can be written to a desired address in the RAM 80 without depending on the receiving order. Also, the CPU 66 and the like can write the transmission packet to a desired address of the RAM 80 without depending on the transmission order.

In FIG. 12A, the FIFO 90
4, 906 and 908 need to have a very large number of stages. In contrast, in the present embodiment, the FIFOs 30,
The number of stages 2, 34 can be significantly reduced, and for example, the number of stages can be reduced to three or less.

In this embodiment, the FIFOs 30, 3
Alternatively, a configuration in which the two and 34 are not provided may be adopted.

In the present embodiment, as shown in FIG. 7, the storage area of the RAM 80 is divided into a header area (control information area in a broad sense) for storing the header of the packet (control information in a broad sense) and a control area of the packet. It is separated into data areas where data is stored. This can be realized by interposing a random accessible RAM 80 between the link core 20 and the CPU 66 as shown in FIG.

That is, in FIG.
Must receive the received packets from FIFO 908 in the order in which they were received. Therefore, if an attempt is made to realize a process of separating a received packet into a header and data,
The received packet read from the IFO 908
2 needs to temporarily write to the RAM which is a local memory, and the CPU 912 needs to read the received packet from the RAM and separate it into a header and data. FIG.
In (A), the CPU 912 sets the FIFO in the order of transmission.
Transmission packets must be input to 904 and 906. For example, when transmitting packet 1 (header 1, data 1), packet 2 (header 2, data 2), and packet 3 (header 3, data 3), header 1, data 1, header 2, data 2,. Transmission packets must be input to the FIFOs 904 and 906 in the order of header 3 and data 3. Therefore, a rearrangement process by the CPU 912 is required.

As described above, in FIG.
2, the processing load becomes very heavy, which eventually leads to a reduction in the actual transfer speed of the entire system.

On the other hand, in the present embodiment, the RAM 8
The storage area of 0 is separated into a header area and a data area.
More specifically, as shown in FIG. 13, the header and data of each received packet are separated by hardware, the header is stored in the header area, and the data is stored in the data area.
Further, as shown in FIG. 14, the header stored in the header area and the data stored in the data area are combined by hardware, and a transmission packet to be transferred to each node is assembled. Therefore, the processing load of the CPU 66 is
2 (A), which is much lighter, and the actual transfer speed of the entire system can be improved. In addition, since an inexpensive CPU 66 can be employed and the bus connected to the CPU 66 can be operated at a low speed, the size and cost of the data transfer control device and the electronic device can be reduced.

Further, according to the present embodiment, the header is collected and stored in the header area, and the data is also stored and collected in the data area. Therefore, it is possible to simplify the reading process and the writing process of the header and the data,
Processing overhead can be reduced. For example, FIG.
When performing the data transfer by the method described in
The data transfer can be controlled only by accessing the header area via the PU bus 96 and reading or writing the header. Also, the device 124 of the application layer continuously transmits the data of the data area to the bus 9.
0, and data can be written continuously to the data area.

As shown in FIG. 15, it is desirable that each header stored in the header area and each data stored in the data area correspond to each other by a data pointer included in the header. In this case, for example, the link core 20 adds the data pointer to the header of the received packet, and the firmware adds the data pointer to the header of the transmitted packet.

In this embodiment, as shown in FIG. 16, a TAG for distinguishing the start (head of header), header, data, and trailer of a received packet is generated, and this TAG is associated with the received packet. I have. More specifically, the link core 20 of FIG.
16 is also transferred to the FIFO 34 at the same time. In the present embodiment, the received packet is separated into a header and data by using the TAG associated with the received packet and stored in the header area and the data area as shown in FIG. More specifically, the DMAC 44 in FIG. 6 uses the TAG output from the FIFO 34 together with the received packet to separate the received packet into a header and data, and writes it into the RAM 80. Note that the TAG only needs to be able to distinguish at least the header and the data.

For example, as a technique for separating the header and data of a received packet without using a TAG, a technique using a tcode (transaction code) included in the header can be considered. That is, by decoding tcode,
The size of the header is checked, the received packet corresponding to the size is stored in the header area, and the rest is stored in the data area.

However, in this method, tcode
Requires a circuit to decode the data, and the circuit becomes large-scale.

On the other hand, if TAG is used, DM
The AC 44 can separate the received packet into a header and data simply by looking at the TAG. Therefore, the header and the data of the received packet can be separated by simple processing without increasing the size of the circuit.

In this embodiment, as shown in FIG. 17A, in addition to the header area and the data area, a work area of the CPU 66 separated from these areas is provided in the RAM 80. This allows the CPU 66 to directly access the work area and use that area for processing by the CPU 66. Therefore, when the CPU 66 has a local memory, the memory can be reduced in capacity. Further, the necessity of providing the local memory of the CPU 66 itself can be eliminated.
As a result, the size and cost of the data transfer control device and the electronic device can be reduced.

In this embodiment, as shown in FIG. 17B, the header area is separated (divided) into a reception area and a transmission area. Each of these reception and transmission header areas may be any that can store at least one or more packets.

For example, in the configuration of FIG. 8, the CPU 912 stores a received packet and a transmitted packet in the RAM 914 as a local memory. For this reason, the CPU 912 has to hold and manage the address storing the received packet and the transmitted packet for each packet. Therefore, CPU
The process of step 912 becomes complicated, and the processing load increases. In particular,
In an application such as a CD-R drive where reception processing and transmission processing coexist, reception packets and transmission packets coexist and are stored in the RAM 914.
The problems of complicated processing and increased processing load become more serious.

On the other hand, according to the present embodiment, the header area is divided into a reception area and a transmission area. Therefore,
A reception header is provided in the reception header area of the RAM 80.
The transmission header area stores transmission headers regularly. Therefore, the CPU 66 only needs to access the reception header area during the reception processing and access the transmission header area during the transmission processing. For example, when receiving received packets continuously, the header is read continuously from the reception header area, and when transmitting transmission packets continuously, the header is continuously written in the transmission header area. It will be good. Therefore, CP
The processing load on U66 can be greatly reduced, and an improvement in the actual transfer speed of the entire system can be expected.

In this embodiment, as shown in FIG. 17C, the data area is divided into a reception area and a transmission area.

Thus, for example, in FIG. 11, the device 124 of the application layer
The reception data can be continuously read from the 0 reception data area, and the transmission data can be continuously written to the transmission data area. Then, at the time of reading or writing, since the address may be simply incremented (or decremented), the address control becomes easy. As a result, according to the present embodiment, the processing overhead can be significantly reduced, and an improvement in the actual transfer speed can be expected.

In this embodiment, the data area is divided into an area for isochronous transfer and an area for asynchronous transfer. More specifically, for example, as shown in FIG.
The data area can be used for isochronous reception, asynchronous reception,
It is divided into areas for isochronous transmission and asynchronous transmission.

For example, in the configuration of FIG. 8, an isochronous packet and an asynchronous packet are mixed and input to the FIFO 908. Then, the CPU 912 reads out the packets from the FOFO 908 in the input order. Also,
The packets are stored in the read order in the RAM 914 which is a local memory. Therefore, in the RAM 914,
Isochronous packets and asynchronous packets are stored together.

The processing of an isochronous packet requires real-time processing. Therefore, the CPU 912 must end the process related to the isochronous packet within a certain period. However, in FIG.
Reference numeral 12 denotes a FIFO 90 in the order input to the FIFO 908.
8 must be read out, and RA
In M914, an isochronous packet and an asynchronous packet are mixed. Therefore, for example, even when an isochronous packet is sent next to an asynchronous packet, the asynchronous packet must be processed first, and the isochronous packet cannot be processed first. For this reason, there is a possibility that the processing of an isochronous packet that requires real-time properties cannot be made in time.

On the other hand, in the present embodiment, the isochronous packet is stored in the area for isochronous transfer, and the asynchronous packet is stored in the area for asynchronous transfer. Therefore, even when an isochronous packet is sent next to an asynchronous packet, the isochronous packet can be read out first and processed first. As a result, the processing of the isochronous packet can be completed within a certain period, and the real-time property required for the processing of the isochronous packet can be maintained.

Further, by dividing the data area into an area for isochronous transfer and an area for asynchronous transfer, the processing of the device in the application layer can be simplified. For example, in a digital video camera, a case is considered in which a moving image that requires real-time properties is transferred isochronously, and a still image that requires reliability is transferred asynchronously. In FIG. 11, it is assumed that data of a moving image or a still image is directly transferred between the data transfer control device 120 and the device 124 of the application layer using the bus 90. In this case, by dividing the data area into an area for isochronous transfer and an area for asynchronous transfer, transfer of moving image and still image data using the bus 90 can be simplified. When transferring moving image data, collectively write the moving image data to the data area for isochronous transfer, and when transferring still image data, collect the still image data together for asynchronous transfer data. This is because writing in the area is sufficient. Also, at the time of this writing, the address may be simply incremented (or decremented), so that the address control becomes easy.

In this embodiment, the data area for asynchronous transfer is divided into a plurality of areas. More specifically, for example, as shown in FIG. 17E, the area for asynchronous reception is divided into first and second areas for asynchronous reception.
Further, the asynchronous transmission area is separated into first and second asynchronous transmission areas.

For example, in an application such as a printer, not only control data such as command data and status data but also print data is asynchronously transferred. In this case, if the data area for asynchronous transfer is not divided into a plurality of areas, the control data and the print data are mixedly stored in the data area for asynchronous transfer. Therefore, the continuity of the print data cannot be maintained, and the processing load on the upper layer increases.

As shown in FIG. 17E, if the data area for asynchronous transfer is divided into a plurality of areas, control data such as command data and status data is stored in the first data area for asynchronous transfer. Then, the print data can be stored in the second data area for asynchronous transfer. As a result, print data can be continuously stored in the second asynchronous transfer data area, and the processing load on the upper layer can be reduced.

In the present embodiment, the data area is divided into the isochronous transfer data area and the first asynchronous transfer data area, and the isochronous transfer data area is optionally divided into the second asynchronous transfer data area. Also used as. More specifically, for example, as shown in FIG. 17F, the isochronous reception area is used as a second asynchronous reception area as needed, or the isochronous transmission area is used as needed as a second asynchronous transmission area. Or

For example, in applications such as digital video, image data (especially moving image data) is transferred isochronously, while control data such as command data and status data are transferred asynchronously. Therefore, in this case, the image data is stored in the isochronous transfer data area, and the control data is stored in the first asynchronous transfer data area.

On the other hand, in an application such as a printer, both print data and control data such as command data and status data are asynchronously transferred. Therefore, in this case, as shown in FIG. 17F, the isochronous transfer data area is used as the second asynchronous transfer data area, and the print data is stored in the second asynchronous transfer data area. To do. On the other hand, the control data is stored in the first asynchronous transfer data area.

As described above, according to the application,
By using the isochronous transfer data area as the second asynchronous transfer data area as needed, effective use of limited resources can be achieved.

In the present embodiment, when the RAM 80 is divided into a plurality of areas, the size of each area is variably controlled. More specifically, as shown in FIG. 18, a pointer P pointing to the address of the boundary of each area
1 to P6 are variably controlled.

In this way, it is possible to realize the optimum area division according to the application. For example, in an application such as a printer in which packets are rarely transmitted and packets are frequently received, the size of the reception area is increased. In an application such as a scanner, which receives a small number of packets and frequently transmits a packet, the size of the transmission area is increased. In an application that frequently performs asynchronous transfer, the size of the area for asynchronous transfer is increased. In an application that frequently performs isochronous transfer, the size of the area for isochronous transfer is increased. Alternatively, in an application that performs only asynchronous transfer, the area for isochronous transfer is set to zero. By doing so, it becomes possible to effectively use limited resources (the RAM 80 having a small storage capacity).

In the configuration shown in FIG.
The method of making each of the sizes 6 and 908 variable has a problem that the hardware configuration becomes complicated. On the other hand, in order to variably control the size of each area of the RAM 80, it is only necessary to control the addresses indicated by the pointers P1 to P6 (control the contents of the register storing the addresses indicated by the pointers). Therefore, the size of each area can be variably controlled with a simple hardware configuration.

It is desirable that the size of each area of the RAM 80 can be dynamically variably controlled even after the power is turned on. For example, in an application such as a CD-R drive, reception processing is mainly performed when writing data to a CD-R, and transmission processing is mainly performed when reading data from a CD-R. Therefore, when writing data to the CD-R, the pointer is dynamically switched so that the size of the receiving area becomes large. Also, C
When data is read from the DR, the pointer is dynamically switched so that the size of the transmission area increases. By doing so, it becomes possible to effectively use limited resources.

It is preferable that each of the regions separated in the present embodiment has a ring buffer structure. That is, as shown in FIG. 19A, the header of the packet is stored from, for example, one boundary (upper boundary) of the reception header area of the RAM 80 to the other boundary (lower boundary). Then, when the other boundary is reached as shown in FIG. 19B, the header is returned to one boundary and stored (overwritten) as shown in FIG. 19C. By doing so, the header is stored in the reception header area in the order of reception, so that the firmware and the application software can know in what order the packet was received. . That is, the advantageous functions of the FIFO can be obtained while using the RAM 80 that can be accessed randomly. In addition, when the packet reaches the other boundary, the packet header is stored from one boundary, so that limited resources (the RAM 80 with a small storage capacity) can be effectively used.

It should be noted that the transmission header area and the data area may have such a ring buffer structure.

In the present embodiment, the size of a header (control information in a broad sense) and an area for storing data (hereinafter referred to as a storage area) of one packet depends on the size of the header and data of the packet. It is desirable to be fixed without performing. For example, in FIG. 20A, the sizes of the headers are different from each other, but the size of the storage area is fixed. In this case, the size of the storage area is set, for example, in units of 8 quadlets irrespective of the size of the header of the packet. In this way, firmware address control and the like can be simplified, and processing overhead can be reduced. In particular, FIGS. 19 (A), (B),
In the case of the ring buffer structure as in (C), unless the size of the storage area is fixed, the header N is separated and stored in the lower side and the upper side as shown in FIG. This leads to an increase in the processing load of the firmware. If the size of the storage area is fixed, such a situation can be solved.

3.2 Configuration of Reception Side Next, the configuration of the reception side will be described. FIG. 21 shows an example of a detailed configuration of the link core 20, the FIFO 34, and the DMAC 44.

The link core 20 includes a bus monitoring circuit 130,
It includes a serial / parallel conversion circuit 132 and a packet shaping circuit 160. The packet shaping circuit 160 includes a packet diagnostic circuit 142, a sequencer 167, a buffer 168, and a selector 170.
G generation circuit 162, header & trailer generation circuit 16
4. Includes an error check circuit 166.

Here, the bus monitoring circuit 130 is a circuit that monitors the 8-bit data bus D and the 2-bit control bus CTL connected to the PHY chip via the PHY interface 10.

The serial / parallel conversion circuit 132 is a circuit for converting data on the data bus D into 32-bit data. For example, when the transfer speed is 400 Mbps, 8-bit data is converted to 32-bit data by 200 Mbps.
In the case of, the 4-bit data becomes 32-bit data,
In the case of 100 Mbps, 2-bit data is converted to 32-bit data.

The packet diagnostic circuit 142 is a circuit for diagnosing a packet. The TAG generation circuit 162 generates a TAG for distinguishing a header, data, a trailer, and the like.
Reference numeral 4 denotes a circuit for generating a header and a trailer (footer). The error check circuit 166 is a circuit that checks error check information such as parity included in a packet and detects an error.

The sequencer 167 generates various control signals. The buffer 168 and the selector 170
Any one of the DI from the serial / parallel conversion circuit 132, the header and trailer from the packet diagnostic circuit 142, and the data pointer from the DMAC 44 is stored in the packet diagnostic circuit 1
This is for selection by the signal SEL from the terminal.

The FIFO 34 functions as a buffer for adjusting the phase of RD which is output data from the link core 20 and the phase of WDATA which is data to be written to the RAM 80.
5 is included. The FIFO state determination circuit 35 activates EMPTY when the FIFO becomes empty, and activates FULL when the FIFO becomes full.

The DMAC 44 comprises a packet separation circuit 18
0, an access request execution circuit 190 and an access request generation circuit 192.

The packet separating circuit 180 is a circuit for separating the packet shaped by the packet shaping circuit 160, writing a header and a trailer in a header area of the RAM 80, and writing data in a data area (see FIG. 13). The packet separation circuit 180 includes the TAG determination circuit 18
2. Pointer updating circuit 184, address generating circuit 188
including.

The TAG determination circuit 182 is a circuit for determining the TAG (DTAG) generated by the TAG generation circuit 162.

The pointer update circuit 184 is a circuit for receiving the output of the TAG discrimination circuit 182 and updating a header pointer and a data pointer for writing a header and data in the RAM 80.

The address generation circuit 188 receives the output of the pointer update circuit 184 and generates a write address WADR to the RAM 80.

The access request execution circuit 190 is a circuit for executing an access request from the link core 20. When the FULL from the FIFO state determination circuit 35 becomes active, the access request execution circuit 190
Activate LL. The sequencer 167 in the packet shaping circuit 160 activates RDS, which is a strobe signal of RD (RxData), on the condition that FFULL is not active.

Note that RFAIL indicates a failure in reception,
This is a signal for the sequencer 167 to notify the access request execution circuit 190.

The access request generation circuit 192 is provided in the RAM 8
This is a circuit for generating an access request to 0. The access request generation circuit 192 receives a write acknowledgment WACK or FI from the buffer manager 70.
In response to the EMPTY from the FO state determination circuit 35, it outputs a write request WREQ to the buffer manager 70.

3.3 Operation on the Receiving Side Next, details of the operation on the receiving side will be described with reference to the timing waveform diagram of FIG.

First, the operation of the link core 20 will be described.

Upon receiving a packet from another node via the PHY chip, the packet diagnostic circuit 142 diagnoses the packet. Then, the header & trailer generation circuit 164 generates (shapes) the header. This header is
The header is input to the selector 170 via the buffer 168, and the selector 170 selects this header based on the signal SEL from the packet diagnostic circuit 142. As a result, FIG.
As shown in A1, the header (H0 to H4) is used as the RD.
Is output to the FIFO 34.

FIG. 23A shows the format (IEEE1) of an asynchronous packet transferred on the serial bus.
394 standard). On the other hand, FIG.
The format of the header portion of the asynchronous reception packet stored in the header area of 0 is shown (the shaded portion in the figure is a trailer). As described above, in the present embodiment, a packet having the format shown in FIG. 23A is shaped into a packet having the format shown in FIG. 23B so that an upper layer such as firmware can use the packet.

In this embodiment, H4 (A2 in FIG. 22), which is the fourth quadlet of the header, is a data pointer for extracting data from the data area as shown in FIG. 23B. This data pointer (H4)
Is input from the DMAC 44 (pointer update circuit 184) to the selector 170 via the buffer 168, and the selector 170 selects this. Thus, the packet shaping circuit 160 receives the data pointer from the DMAC 44 and embeds the data pointer in the header written in the RAM 80.

Next, the data portion of the packet is sent from the PHY chip via the data bus D. The serial / parallel conversion circuit 132 converts this data portion into DI which is 32-bit data and outputs the DI to the packet diagnosis circuit 142 and the buffer 168.

Note that DIE is a signal indicating whether DI is valid or invalid, and DIS is a strobe signal for notifying the timing of taking in DI.

The DI from the serial / parallel conversion circuit 132 is
The data is input to the selector 170 via the buffer 168, and the selector 170 selects this. As a result, as shown in A3, the data D0 to Dn are stored in the FIFO 34 as RD.
Is output to

Next, the header & trailer generation circuit 164
From the selector 1 via the buffer 168
70, and the selector 170 selects this. As a result, as shown in A4, the trailer (H5; the hatched portion in FIG. 23B) is output to the FIFO 34 as the RD.

The TAG generation circuit 162 generates a TAG for distinguishing information output as RD. In the present embodiment, as shown in FIG. 16, the TAG is 2 bits, and (00), (01), (10), (11)
Represents a header, a trailer, data, and a start (head of the header), respectively. Therefore, for example, in FIG.
The TAG changes as 1), (00), ..., (10), ..., (01). The FIFO 34 receives 34-bit data consisting of the 2-bit TAG and the 32-bit RD.

Next, the operation of the FIFO 34 will be described.

The FIFO 34 receives the T from the link core 20.
After receiving AG and RD, as shown in A5 and A6, DTA
G, output as WDATA.

FIFO state determination circuit 3 in FIFO 34
5 counts the number of data in the FIFO 34 (FIFO count) by a built-in counter. And F
When the IFO 34 becomes full (the number of data = 2),
FULL is made active (H level) as indicated by A7 in FIG. Also, the FIFO 34 is empty (the number of data =
When it becomes 0), EMPTY is activated as indicated by A8. The fact that the FIFO 34 is full is transmitted to the access request execution circuit 190 in the DMAC 44 and the sequencer 167 in the link core 20 by FULL and FFULLL. The fact that the FIFO 34 has become empty is transmitted to the access request generation circuit 192 in the DMAC 44 by EMPTY.

Next, the operation of the DMAC 44 will be described.

The access request generation circuit 192 sets A1 on the condition that EMPTY becomes inactive (L level) (the FIFO 34 is not empty) as shown in A9.
Activate WREQ as shown at 0. And
When a WACK is received from the buffer manager 70, W
Deactivate REQ.

In the present embodiment, in the bus arbitration at the time of reception, the priority of the access request from the DMAC 44 is the highest. Accordingly, as shown in A10 and A11, the WREQ from the DMAC 44 and the Oth from the CPU interface 60 and the DMAC 54 for the port are used.
If erWREQ conflicts, WREQ takes precedence. That is, as shown in A12 and A13, WACK
Becomes active before OtherWACK. As described above, when WREQ and OtherWREQ conflict, the WREQ is prioritized for the following reason. That is, in IEEE 1394, unlike SCSI and the like, packets from other nodes are sequentially transferred in synchronization with a transfer clock. Therefore, it is necessary to store the packets transferred without interruption in the RAM 80 one after another with priority.

In this embodiment, while the buffer manager 70 is receiving an access request from the CPU interface 60 or the DMAC 54 for a port, A
As shown at 14, the access request of the DMAC 44 is waited for a given period. Therefore, the RD from the link core 20 and the WDATA to the buffer manager 70 are not synchronized. For this reason, in the present embodiment, RD and W
A FIFO 34 for adjusting the phase of DATA is provided. In this case, the FIFO 34 may have the minimum number of stages (preferably three or less, more preferably two or less) necessary for phase adjustment.

TAG included in packet separation circuit 180
The determination circuit 182 determines the DTAG output from the FIFO 34 together with WDATA, and determines whether WDATA is a start (head of header), header, data, or a trailer. Then, the pointer update circuit 184
Updates the header pointer and the data pointer based on this determination result. Next, the address generation circuit 188
Generates WADR, which is the write address of WDATA, based on the updated header pointer and data pointer.

More specifically, for example, when it is determined based on the DTAG that WDATA is the start or the header, the pointer update circuit 184 increments the header pointer HP as shown in FIG. Update in a broad sense). Then, the address generation circuit 188
Generates a WADR corresponding to the header pointer to be incremented, as indicated by A15 in FIG.

Next, if WDATA is data, DTA
If it is determined based on G, the pointer update circuit 184
However, as shown in FIG. 24B, the data pointer DP is incremented. This data pointer DP corresponds to H4 embedded in the fourth quadlet of the header by the packet shaping circuit 160. Address generation circuit 18
8 generates a WADR corresponding to the data pointer to be incremented, as indicated by A16 in FIG.

Next, if WDATA is a trailer, D
If it is determined based on the TAG, the pointer update circuit 1
84 increments the header pointer as shown in FIG. Then, the address generation circuit 18
8 generates a WADR corresponding to the incremented header pointer, as indicated by A17 in FIG.

Finally, as shown in FIG. 24D, the header pointer points to the lower boundary of the header portion of the packet to be processed (the upper boundary of the header portion of the next packet). To point. The data pointer also points to the lower boundary of the data portion of the packet (the upper boundary of the data portion of the next packet). The final positions of the header pointer and the data pointer are determined based on the condition that reception has not failed (RFAIL is inactive).
The data is restored to the header pointer setting register and the data pointer setting register in the register 46 of FIG.

As described above, packets can be separated and written into the header area and the data area.

In particular, in this embodiment, the data pointer added to the header is transmitted from the pointer update circuit 184 to the packet shaping circuit 160. Then, the packet shaping circuit 160 adds the transmitted data pointer to the header of the packet. By doing so, the firmware or the like reading the header from the header area can easily know the storage address of the data corresponding to the header in the data area. The addition of the data pointer is performed by the packet shaping circuit 160, and the DMAC 44 does not need to be involved in this. Therefore, the DMAC 44 can concentrate on the process of writing data to the RAM 80, and the circuit configuration and the process of the DMAC 44 can be simplified.

The boundaries between the areas separating the RAM 80, such as the boundaries between the header area and the data area (P1 to P1 in FIG. 18).
P6) is set by the CPU 66 (firmware or the like) via the CPU interface 60 by the register 4 in FIG.
6 is set by setting a pointer indicating a boundary address in the pointer setting register included in the pointer setting register 6.

As shown in FIGS. 17D, 17E and 17F, when the data area is divided into a plurality of areas, the data area is separated based on the control information of the packet such as tcode. It is desirable to write the packet data in any of the plurality of areas.

More specifically, as shown in FIG.
The MAC 44 passes a plurality of data pointers, for example, the first and second data pointers, to the packet shaping circuit 160 (three or more data pointers may be passed). Then, the packet shaping circuit 160, for example,
At the time of isochronous transfer (or at the time of the second asynchronous transfer in FIG. 17F), the first data pointer from the DMAC 44 is selected, and at the time of non-same transfer (or the first data pointer of FIG. 17F).
(During asynchronous transfer), the second data pointer from the DMAC 44 is selected. That is, the packet diagnostic circuit 142 in the packet shaping circuit 160 determines whether the transfer is the isochronous transfer or the asynchronous transfer (or the second asynchronous transfer or the first asynchronous transfer) based on the control information of the packet such as tcode. Based on the result of this determination, the signal SE
Control L. Then, one of the first and second data pointers input to the selector 170 via the buffer 168 is selected. Thereby, the first data pointer is embedded in the packet of the isochronous transfer (or the second asynchronous transfer), and the second data pointer is embedded in the packet of the asynchronous transfer (or the first asynchronous transfer). Become. As a result, data can be continuously stored in a specific area separating the data area. That is, moving image data in the digital camera can be continuously stored in the isochronous transfer data area, and print data in the printer can be continuously stored in the second asynchronous transfer data area.

As shown in FIG. 17E, the data area is divided into an isochronous transfer data area and an asynchronous transfer data area, and the asynchronous transfer data area is divided into the first and second asynchronous transfer data areas. In the case where the data pointers are separated into three, it is desirable to prepare three data pointers.
That is, a first data pointer that points to the isochronous transfer data area and second and third data pointers that point to the first and second asynchronous transfer data areas are prepared. By doing so, the separation of the data area as shown in FIG. 17E can be easily realized.

3.4 Configuration of Transmission Side Next, the configuration of the transmission side will be described. FIG.
2 shows an example of a detailed configuration of O30 and DMAC40.

FI functioning as buffer for phase adjustment
The FO 30 includes a FIFO state determination circuit 31. FIF
When the FIFO becomes empty, the O state determination circuit 31
TY is activated, and when the FIFO is full, the FU
Activate LL.

The DMAC 40 includes a packet combining circuit 28
0, access request execution circuit 290, access request generation circuit 292, ACK write request generation circuit 294, ACK
A write data & address generation circuit 296 is included.

The packet combining circuit 280 converts the header into RA
This is a circuit that reads data from the M80 header area, reads data from the data area, and assembles a transmission packet that forms a frame with these headers and data (see FIG. 14). The packet combining circuit 280 includes a pointer updating circuit 284 and an address generating circuit 288.

The pointer update circuit 284 is a circuit for updating a header pointer and a data pointer for reading a header and data from the RAM 80, and includes a data pointer acquisition circuit 285. Data pointer acquisition circuit 2
Reference numeral 85 denotes a circuit for obtaining a data pointer from RDATA read from the RAM 80, and includes a tcode determination circuit 286.

The address generation circuit 288 is a circuit which receives an output of the pointer update circuit 284 and the like and generates a read address RADR of the RAM 80.

The access request execution circuit 290 has a FIFO
When EMPTY from the state determination circuit 31 becomes active, FIFOIN becomes active. Link core 20
Is T, provided that FIFOIN is not active
TDS, which is a strobe signal of D (TxData), is activated.

Note that TFAIL reports a failure in transmission,
This signal is for the link core 20 to notify the access request execution circuit 290.

The access request generation circuit 292 receives the ACK from the buffer manager 70 and the FULL from the FIFO state determination circuit 31.
Then, RREQ, which is a read request, is output to the buffer manager 70.

The ACK write request generation circuit 294 is provided for receiving the TCP message from the link core 20 or the buffer manager 70.
, And outputs a WREQ to the buffer manager 70. Further, the ACK write data & address generation circuit 296 receives the TACK from the link core 20 and writes the ACK code to be written back into the transmission packet to the WDA.
Output as TA and write the address to which ACK is written back to WAD
Output as R.

3.5 Operation on Transmission Side Next, the operation on the transmission side will be described in detail with reference to the timing waveform diagram of FIG.

First, the operation of the link core 20 will be described.

When TSTART for notifying the start of transmission is activated, as shown in B1 of FIG. 26, the link core 20 uses the TDS, which is a strobe signal, to execute a FIFO.
Take in the TD from 30. In this case, the link core 20 receives the TDS in the order of the header (H0 to H3) and the data (D0 to Dn).

FIG. 27 shows the format of the header portion of the asynchronous transmission packet stored in the header area of the RAM 80. As shown in the figure, the fourth quadlet of the header is a data pointer.

By the way, at the position indicated by B2 in FIG. 26, the phosphorus core 20 does not activate the TDS. Therefore, B
As shown in FIG. 3, the fourth quadlet of the header, H4
Are not taken into the link core 20. This is because H4 of the fourth quadlet is a data pointer as shown in FIG. 27, and the link core 20 does not need this data pointer. Then, during the period indicated by B3, the link core 20 performs a process of generating a header CRC (see FIG. 23A) and adding the header CRC to the header.

When the transmission processing of one packet is completed,
The link core 20 activates TCMP as indicated by B4. Then, the ACK code returned from the transmission destination node via the PHY chip (see FIG. 1A) is output to the DMAC 40 as TACK as indicated by B5. The code of this ACK is A
The CK write request generation circuit 294 and the ACK write data & address generation circuit 296 write back to the header stored in the header area of the RAM 80 (the seventh quadlet in FIG. 27).

Next, the operation of the FIFO 30 will be described.

The FIFO 30 includes a buffer manager 70
And outputs it to the link core 20 as TD.

FIFO state determination circuit 3 in FIFO 30
1 counts the number of data in the FIFO 30 (FIFO count) by a built-in counter. And F
When the IFO 30 becomes empty (the number of data = 0), the EMPTY is activated as indicated by B6 in FIG. When the FIFO 30 becomes full (the number of data = 2), FULL is activated (H level) as indicated by B7. The fact that the FIFO 30 is empty is communicated to the access request execution circuit 290 and the link core 20 in the DMAC 40 by EMPTY and FIFOIN. The fact that the FIFO 30 is full indicates that the F
The information is transmitted to the access request generation circuit 292 in the DMAC 40 by the ULL.

Next, the operation of the DMAC 40 will be described.

The access request generation circuit 292 sets the RRE on condition that FULL is inactive (L level) (the FIFO 34 is not full), as indicated by B8.
Activate Q. And the buffer manager 7
Receiving RACK from 0 deactivates RREQ.

In this embodiment, the priority of the access request from the DMAC 40 (or the DMAC 42) is the highest in the bus arbitration at the time of transmission. Therefore, when the RREQ from the DMAC 40 and the access request (OtherRREQ) from the CPU interface 60 and the DMAC 54 for the port conflict, the RR
EQ takes precedence. On the other hand, before RREQ, CP
When there is an access request from the U interface 60 or the DMAC 54 for the port, as shown in B9,
The DMAC 40 access request is kept waiting for a given period. Therefore, the RDATA from the buffer manager 70
Is not synchronized with the TD to the link core 20. For this reason, in the present embodiment, the FIFO 30 for adjusting the phases of RDATA and TD is provided.

When transmission starts, the pointer update circuit 284 increments (updates in a broad sense) the header pointer HP. Then, the address generation circuit 288
Generates RADR according to the incremented header pointer as shown in B10 of FIG. Thus, the header portion of RDATA is sequentially read from the RAM 80.

When H4 is read as RDATA,
The data pointer acquisition circuit 285 included in the packet combination circuit 280 acquires H4 as the data pointer DP. More specifically, when H0 is read as RDATA, tc in the data pointer acquisition circuit 285
The mode determination circuit 286 detects the tcode included in H0
(See FIG. 27). Then, when it is determined based on tcode that a data pointer is present in, for example, the fourth quadlet of the header, when H4 is read as RDATA, the data pointer acquisition circuit 285 acquires this H4. That is, as shown in B11 of FIG.
H4 of RDATA is obtained as a data pointer,
Output as RADR.

In this embodiment, as indicated by B3 and B11, the data pointer H4 is obtained from RDATA using the period during which the link core 20 generates the header CRC. That is, in the present embodiment, the header CRC is generated by the link core 20, and the DMAC 40 is not involved in this. On the other hand, acquisition of the data pointer is DM
AC 40 does, and link core 20 is not involved.
In the present embodiment, paying attention to this, a data pointer is arranged in the fourth quadlet in which the header CRC is arranged in FIG. 23A, as shown in FIG. Then, using the period in which the header CRC is generated, RDA
The data pointer H4 is obtained from the TA. This makes it possible to prevent the processing time from being wasted.

When the data pointer is obtained, the pointer update circuit 284 causes the obtained data pointer H
4 is incremented. Then, the address generation circuit 288 generates RADR according to the incremented data pointer, as indicated by B12 in FIG.
Thus, the data portion of the RDATA is stored in the RAM 80.
Are sequentially read out.

When the transmission processing of one packet is completed, B4
When the TCMP is activated as shown in (B), the ACK write request generation circuit 294 makes the WRE
Activate Q. And from the link core 20 to A
The ACK code transmitted using TACK to the CK write data & address generation circuit 296 is output as WDATA as indicated by B14. Also, at this time, the HP +
7 is output as WADR. Here, the reason why the WADR becomes HP + 7 is that the ACK code is written back to the seventh quadlet of the header as shown in FIG.

As described above, it is possible to assemble a transmission packet by combining the header in the header area and the data in the data area.

In the present embodiment, in particular, the header and data are combined by the DMAC 40, and the link 20 does not need to be involved. Therefore, the circuit configuration and processing of the link core 20 can be simplified.

Further, in the present embodiment, the data pointer acquisition circuit 285 outputs the data pointer (H
4) is obtained, RADR is generated based on the obtained data pointer, and data is read. By doing so, the header and the data corresponding to the header can be reliably connected. Further, the circuit configuration required for the process of combining the header and the data can be simplified.

4. Electronic Device Next, an example of an electronic device including the data transfer control device of the present embodiment will be described.

For example, FIG. 28A shows an internal block diagram of a printer which is one of the electronic devices, and FIG. 29A shows its external view. CPU (microcomputer) 51
0 controls the entire system. The operation unit 511 is for the user to operate the printer. ROM5
16 stores a control program, fonts, and the like.
The RAM 518 functions as a work area for the CPU 510. The display panel 519 is for notifying the user of the operation state of the printer.

Print data sent from another node such as a personal computer via the PHY chip 502 and the data transfer control device 500 is sent directly to the print processing unit 512 via the bus 504. The print data is subjected to given processing in a print processing unit 512, and is printed and output on paper by a print unit (device for outputting data) 514 including a print header and the like.

FIG. 28B shows an internal block diagram of a scanner which is one of the electronic devices, and FIG. 29B shows an external view thereof. The CPU 520 controls the entire system. The operation unit 521 is for the user to operate the scanner. The ROM 526 stores a control program and the like, and the RAM 528 functions as a work area of the CPU 520.

An image of a document is read by an image reading unit (device for reading data) 522 including a light source, a photoelectric converter, and the like, and the data of the read image is processed by an image processing unit 524. Then, the processed image data is transferred to the data transfer control device 500 via the bus 505.
Sent directly to The data transfer control device 500 generates a packet by adding a header or the like to the image data, and transmits the packet to another node such as a personal computer via the PHY chip 502.

FIG. 28C shows a CD which is one of the electronic devices.
FIG. 29C shows an internal block diagram of the -R drive, and FIG. 29C shows an external view thereof. The CPU 530 controls the entire system. The operation unit 531 is for the user to operate the CD-R. The ROM 536 stores a control program and the like, and the RAM 538 functions as a work area of the CPU 530.

The reading / writing unit (device for taking in data or device for storing data) 533 comprising a laser, a motor, an optical system, etc.
2 is input to the signal processing unit 534 and subjected to given signal processing such as error correction processing. Then, the signal-processed data is transferred to the bus 506.
Is sent directly to the data transfer control device 500 via the. The data transfer control device 500 generates a packet by adding a header or the like to this data,
To another node such as a personal computer via

On the other hand, data sent from another node via the PHY chip 502 and the data transfer control device 500 is sent directly to the signal processing unit 534 via the bus 506. Then, given signal processing is performed on the data by the signal processing unit 534, and the reading and writing unit 533 is performed.
Is stored in the CD-R 532.

In FIGS. 28 (A), (B) and (C), a CPU for controlling data transfer in the data transfer control device 500 may be separately provided in addition to the CPUs 510, 520 and 530. Good.

By using the data transfer control device of this embodiment for electronic equipment, high-speed data transfer becomes possible. Therefore, when the user gives a printout instruction using a personal computer or the like, printing is completed with a small time lag. Further, after the instruction to take in the image to the scanner, the user can view the read image with a small time lag. Also, CD-
It becomes possible to read data from R and write data to CD-R at high speed. Further, for example, it becomes easy to connect and use a plurality of electronic devices to one host system or to connect and use a plurality of electronic devices to a plurality of host systems.

Further, by using the data transfer control device of the present embodiment in an electronic device, the processing load of firmware operating on the CPU can be reduced, and an inexpensive CPU and a low-speed bus can be used. Further, since the cost and the size of the data transfer control device can be reduced, the cost and the size of the electronic device can be reduced.

The electronic apparatus to which the data transfer control device of the present embodiment can be applied is, for example, various optical disk drives (CDROM, DVD), magneto-optical disk drive (MO), hard disk drive, etc.
Various things such as a TV, VTR, video camera, audio equipment, telephone, projector, personal computer, electronic organizer, and word processor can be considered.

Note that the present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

For example, the configuration of the data transfer control device of the present invention is particularly preferably the configuration shown in FIG. 6, but is not limited thereto.

Further, in the present invention, it is particularly desirable to divide the storage means into a plurality of areas, but it is also possible to adopt a configuration in which this is not separated.

The present invention is particularly preferably applied to data transfer in the IEEE 1394 standard, but is not limited to this. For example, the present invention can be applied to data transfer based on a standard based on the same concept as IEEE 1394 or a standard developed from IEEE 1394.

[0219]

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are diagrams for explaining asynchronous transfer and isochronous transfer. FIG.

FIGS. 2A and 2B are diagrams for explaining tree identification; FIG.

FIG. 3 is a diagram for describing self-identification.

FIGS. 4A, 4B, 4C, and 4D are diagrams showing formats of physical layer packets such as self-ID packets.

FIG. 5 is a diagram showing an IEEE 1394 protocol configuration.

FIG. 6 is a diagram illustrating a configuration example of a data transfer control device according to the present embodiment.

FIG. 7 is a diagram for describing separation of a header (control information) area and a data area.

FIG. 8 is a diagram illustrating a configuration example of a comparative example of the present embodiment.

FIG. 9 is a diagram for explaining a data transfer method using the configuration of FIG. 8;

FIG. 10 is a diagram for explaining another example of a data transfer technique.

FIG. 11 is a diagram for explaining a data transfer method according to the embodiment;

FIGS. 12A and 12B show a link core and a CP.
FIG. 9 is a diagram for explaining a method of interposing a random accessible RAM between the U and the U;

FIG. 13 is a diagram illustrating a method of separating a received packet into a header and data,
FIG. 4 is a diagram for describing a method of storing data in an AM header area and a data area.

FIG. 14 is a diagram for describing a method of combining a header stored in a header area and data stored in a data area to assemble a transmission packet.

FIG. 15 is a diagram for describing a method of including a data pointer in a header stored in a header area.

FIG. 16 is a diagram illustrating a TAG.

17 (A), (B), (C), (D),
(E), (F) is a diagram for explaining a method of separating the RAM into various areas.

FIG. 18 is a diagram for describing a method of variably controlling the size of each area of a RAM.

FIGS. 19A, 19B, and 19C are diagrams for explaining a ring buffer structure.

FIGS. 20A and 20B are diagrams for explaining a method of fixing the size of an area in which a header and data of one packet are stored.

FIG. 21 is a diagram illustrating an example of a configuration on a receiving side.

FIG. 22 is a timing waveform chart for explaining the operation on the receiving side.

FIG. 23A shows the format of an asynchronous packet conforming to the IEEE 1394 standard, and FIG.
It is a format of a header portion of an asynchronous reception packet stored in a header area of a RAM.

FIGS. 24 (A), (B), (C), (D)
FIG. 9 is a diagram for describing updating of a header pointer and a data pointer.

FIG. 25 is a diagram illustrating an example of a configuration on a transmission side.

FIG. 26 is a timing waveform chart for explaining the operation on the transmission side.

FIG. 27 shows a format of a header portion of an asynchronous transmission packet stored in a header area of a RAM.

FIGS. 28A, 28B, and 28C are examples of internal block diagrams of various electronic devices.

FIGS. 29A, 29B, and 29C are examples of external views of various electronic devices.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 PHY interface 20 Link core 22 Register 30 FIFO (ATF) 32 FIFO (ITF) 34 FIFO (RF) 40 DMAC (for ATF) 42 DMAC (for ITF) 44 DMAC (for RF) 50 Port interface 52 FIFO (PF) 54 DMAC (for PF) 56 Register 60 CPU interface 62 Address decoder 63 Data synchronization circuit 64 Interrupt controller 66 CPU 68 Clock control circuit 70 Buffer manager 72 Register 74 Arbitration circuit 76 Sequencer 80 RAM (packet storage means) 90, 92, 94 Bus (First bus) 96, 98 bus (second bus) 100, 102, 104, 105, 106, 107, 108, 109 bus (third bus) 110 bus (4th bus) 120 data transfer control device 122 PHY chip 124 device of application layer 130 bus monitoring circuit 132 serial / parallel conversion circuit 142 packet diagnostic circuit 160 packet shaping circuit 162 TAG generation circuit 164 header & trailer generation circuit 166 error check circuit 167 Sequencer 168 Buffer 170 Selector 180 Packet separation circuit 182 TAG determination circuit 184 Pointer update circuit 188 Address generation circuit 190 Access request execution circuit 192 Address request generation circuit 280 Packet connection circuit 284 Pointer update circuit 285 Data pointer acquisition circuit 286 tcode determination circuit 290 Access request execution circuit 292 Address request generation circuit 294 ACK write request generation circuit 296 ACK write Only data & address generator

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshiyuki Kamihara 3-3-5 Yamato, Suwa City, Nagano Prefecture Seiko Epson Corporation F-term (reference) 5K032 AA02 AA03 CD01 DB19 DB24

Claims (19)

[Claims] 1. A data transfer control device for transferring data between a plurality of nodes connected to a bus, comprising: link means for providing a service for packet transfer between nodes; and storing packets. Storage means capable of random access, a writing means for writing a packet transferred from each node via the link means to the storage means, a packet written to the storage means by an upper layer, and the link means A data transfer control device comprising: 2. The data transfer method according to claim 1, wherein the storage unit is separated into a control information area for storing control information of the packet and a data area for storing data of the packet. Control device. 3. The data transfer control device according to claim 1, wherein said storage means is separated into an area for storing packets and a work area for a central processing unit. 4. The data transfer control according to claim 2, wherein the control information area of the storage unit is separated into a reception control information area and a transmission control information area. apparatus. 5. The data transfer control device according to claim 2, further comprising a packet separating unit that writes control information of a packet in the control information area and writes data of the packet in the data area. . 6. The communication device according to claim 5, wherein the linking means generates tag information for distinguishing at least control information and data of the packet, associates the generated tag information with the packet, and the packet separating means A data transfer control device that writes packet control information to the control information area and writes packet data to the data area based on the tag information associated with the packet. 7. The data transfer control device according to claim 2, wherein the data area of the storage unit is divided into a reception data area and a transmission data area. 8. The data transfer control device according to claim 2, wherein said data area of said storage means is separated into an isochronous transfer data area and an asynchronous transfer data area. . 9. The asynchronous transfer data area according to claim 2, wherein the data area of the storage unit includes an asynchronous transfer data area, and the asynchronous transfer data area includes a first and a second asynchronous transfer data area. A data transfer control device characterized by being divided into a plurality of areas including: 10. The data area according to claim 2, wherein the data area of the storage means is divided into an isochronous transfer data area and a first asynchronous transfer data area. 2. A data transfer control device used as an asynchronous transfer data area. 11. The data area according to claim 2, wherein the data area of the storage unit is divided into a plurality of areas, and the packet area is divided into any of the plurality of separated areas based on control information of the packet. A data transfer control device comprising means for writing data. 12. The method according to claim 1, wherein the storage unit is divided into a plurality of areas.
A data transfer control device comprising means for variably controlling the size of each area. 13. The data transfer control device according to claim 12, wherein the size of each area is dynamically variably controlled even after power is turned on. 14. The control information and data of a packet according to claim 1, wherein the storage unit is divided into a plurality of areas, from one boundary of the separated area to the other boundary. A data transfer control device wherein at least one of the control information and the data is stored, and when reaching the other boundary, the process returns to the one boundary and stores at least one of the control information and the data of the packet. 15. The data transfer control device according to claim 14, wherein the size of an area for storing at least one of control information and data of one packet is fixed. 16. The data transfer control device according to claim 1, further comprising a reception FIFO and a transmission FIFO provided between the link unit and the storage unit. 17. The data transfer control device according to claim 1, wherein the data transfer is performed in accordance with the IEEE 1394 standard. 18. A data transfer control device according to claim 1, further comprising: a device for performing a given process on data received from another node via said data transfer control device and a bus. And a device for outputting or storing the obtained data. 19. A data transfer control device according to claim 1, wherein said data transfer control device and a device for performing a given process on data to be transmitted to another node via a bus. An apparatus for capturing data to be processed.