JP2000132974A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which securely synchronizes data stored in a memory with a clock signal which is speeded up and outputting it. SOLUTION: A memory core 101 storing data, sense amplifiers 102a-102h amplifying data which the memory core 101 outputs, a dummy amplifier 104 generating a dummy signal, a holding circuit 105 holding data outputted from the memory core 101 based on the dummy signal, a row decoder 106 controlling the word line of the memory core 101, a column decoder 107 controlling respective column switches 108a-103h, a dummy column decoder 108 controlling the dummy amplifier 104, a delay circuit 109 delaying the dummy signal and a capacitor 110 are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device for outputting data stored in a memory in synchronization with a clock signal.

[0002]

2. Description of the Related Art With the spread of multimedia equipment, the performance of semiconductor devices constituting such equipment systems and equipment, especially the processing speed, has been increased. In recent years, in particular, the speed of the processor, which is the central part of the computer, has been remarkably increased, and accordingly, the processing speed of the storage device has been required to be increased.

Generally, a semiconductor memory device stores data in a capacitor inside the device and amplifies and outputs the data. Therefore, it is difficult to increase the processing speed as compared with a processor unit. Therefore, without changing the basic configuration of the semiconductor memory device, the processing speed of the memory device is increased by increasing the speed of peripheral circuits for processing input / output data by using a clock synchronous high-speed logic circuit technology. I have.

FIG. 11 is a block diagram for explaining a conventional semiconductor memory device, and shows a configuration of the semiconductor device. In the figure, reference numeral 300 denotes the semiconductor storage device, which comprises a memory core, a sense amplifier, a column switch, and a dummy amplifier, and outputs memory data 301a, 301b, 301c, and 301d;
Read amplifiers (R / A) 302a, 302b, 302c, 302 for amplifying data output from each memory block
d, a holding circuit 303 for holding data output from each read amplifier based on a clock signal, and a holding circuit 303.
, An output circuit 304 for outputting data held therein, a row decoder 306 for receiving an address signal for specifying data to be output from each memory block, and controlling a word line of each memory block, Receiving an address signal for specifying data to be output,
A column decoder 307 controls a column switch of each memory block.

Next, the operation will be described. An address signal indicating the address of the data to be output is supplied to the row decoder 3.
06 and the column decoder 307. The memory block specified by the row decoder 306 and the column decoder 307 outputs data to be output, and the read amplifier corresponding to the memory block amplifies the data. The amplified data is input to the holding circuit 303 through a global data line. The holding circuit 303 holds the input data based on the clock signal CLK, and the output circuit 304 outputs the data based on the clock signal. Thus, the conventional semiconductor memory device outputs data in the memory block specified by the address signal in synchronization with the clock signal.

[0006]

The above-mentioned semiconductor memory device 3
00, each memory block has a row decoder 30
6 and a series of operations of a word line, a bit line, a sense amplifier, a column switch, etc., are performed serially in response to an address input to the column decoder 307, and can be regarded as a so-called one large delay circuit. It is also an asynchronous circuit that is not synchronized with the clock. In general, although depending on the chip area of the memory block, the length of the wiring between each memory block and the holding circuit for holding the output data differs for each memory block. Therefore, the holding circuit 3
03, that is, when data is transferred from the memory block D301d having a short wiring, and when data is transferred from a memory block A301a that is relatively far from the holding circuit, that is, when data is transferred from the memory block A301a having a long wiring.
The time from when each memory block outputs data to when the data arrives at the holding circuit 303 (hereinafter referred to as “transfer time”) is different. That is, the data transfer time of the memory block D301d is relatively short, the data transfer time of the memory block A301a is relatively long, and the data transfer time varies among the memory blocks.

On the other hand, the holding circuit 303 outputs the clock signal C
In synchronization with LK, that is, when the clock signal changes from High to Low
, Or at the timing of transition from Low to High. As described above, when the transfer time varies, especially when the transfer time is long, the holding circuit 3 delays from the timing when the clock signal CLK transitions.
03 may be input to the holding circuit 303.
As a result, the data transfer error occurs as a result. In addition, while the frequency of the clock used in the semiconductor memory device is being increased, it is considered that the possibility of a data transfer error occurring due to the above-mentioned variation in the transfer time is further increased. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a semiconductor memory device that reliably outputs data stored in a memory block in synchronization with a speed-up clock signal.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising: a memory for outputting stored data based on an address signal; and a high or a low synchronized with the address signal. A dummy signal generating means for generating a transitional dummy signal; a delay means for adding a delay to the dummy signal; holding the output data based on the delayed dummy signal; and outputting the held data in synchronization with a clock signal. And holding means for performing the operation.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the delay means includes a dummy signal line for conducting a dummy signal from the dummy signal generation means to the holding means. The length is longer than the length of the data line for conducting data from the storage means to the holding means.

According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the delay unit loads a dummy signal line for conducting a dummy signal from the dummy signal generation unit to the holding unit. Is the load capacity that gives

The present invention (claim 4) provides a plurality of storage means for outputting stored data based on an address signal and outputting a dummy signal which transitions to High or Low in synchronization with the address signal. And when the control signal is in the comparison mode, for each of the storage means, compare the phases of the dummy signal and the clock signal, and output the result of the comparison; and when the control signal is in the comparison mode, Delay adjusting means for storing the comparison result in association with each of the storage means, and adding a delay to the clock signal based on the comparison result of the storage means corresponding to the address signal when the control signal is in the access mode; Holding means for holding and outputting the output data based on the delayed clock signal.

Further, according to the present invention (claim 5), in the semiconductor memory device according to any one of claims 1 to 4, the holding means outputs the output signal when the dummy signal transitions to high / low. A first holding circuit for holding and outputting data, a second holding circuit for holding and outputting the output data when the dummy signal transits to Low / High, and a first holding circuit for holding the output data based on a clock signal. A third holding circuit that holds and outputs the output data of the first holding circuit, a fourth holding circuit that holds and outputs the output data of the second holding circuit based on a clock signal, A selection circuit for selecting an output of the third holding circuit or the fourth holding circuit based on a signal.

[0013]

Embodiments of the present invention will be described below. (First Embodiment) FIG. 1 is a block diagram for explaining a semiconductor memory device according to a first embodiment of the present invention, and shows a configuration of the semiconductor memory device. In FIG. 1, reference numeral 100 denotes a semiconductor memory device according to the first embodiment, which includes a memory core 101 for storing data and sense amplifiers (S / A) 102a, 1 for amplifying data output from the memory core 101.
02b, 102c, 102d, 102e, 102f, 1
02g, 102h, and column switches 103a, 103b, 103c, which control the data output of each sense amplifier.
103d, 103e, 103f, 103g, 103h
A dummy amplifier 104 for generating a dummy signal; a holding circuit 105 for holding data output from the memory core 101 based on the dummy signal;
01, a row decoder 106 for controlling the word line 01, a column decoder 107 for controlling each of the column switches,
A dummy column decoder 108 for controlling the dummy amplifier 104; and a delay circuit 10 for adding a delay to the dummy signal.
9 and a capacitor 110.

Each of the column switches is connected to a data line DL, and holds data output from the memory core 101 via the output data line DL.
Output. Column decoder 1
07 is a column line YLa, YLb, YLc, YLd, Y
Each column switch is connected by Le, YLf, YLg, and YLh, and each column switch is controlled via each column line.

The dummy amplifier 104 is connected to the dummy signal line SL and outputs a dummy signal to the delay circuit 109 via the dummy signal line SL.
Reference numeral 9 denotes a configuration in which a delay is added to the dummy signal and output to the holding circuit 105. In addition, the dummy column decoder 108 uses two dummy column lines to make the dummy amplifier 1
The set signal or the reset signal is supplied to the dummy amplifier 104 by the respective dummy column lines.
Is output to

In the dummy signal line SL, the length from the connection with the dummy amplifier 104 to the connection with the holding circuit 105 is from the connection with each column switch on the data line DL to the connection with the holding circuit 105. Is configured to be longer than any of the lengths. Further, the capacitor 110 is provided on the dummy signal line SL between the dummy amplifier connection portion and the holding circuit connection portion.

FIG. 2 is a diagram for explaining the inside of the holding circuit 105, and shows the internal configuration of the holding circuit 105. The holding circuit 105 includes first and second D-type flip-flops (hereinafter, referred to as “DFFs”) 11 and 12 for holding input data based on a dummy signal, and a first DFF 11 based on a clock signal. And a third DFF 13 for holding the output of
A fourth DFF 14 that holds the output of the DFF 12 and a selector 15 that selects and outputs one of the outputs of the third or fourth DFF based on the clock signal.

Next, the operation will be described. FIG. 3 is a diagram for explaining the timing of the data output of the memory core 101 and the dummy signal output of the dummy amplifier 104. The row decoder 106 and the column decoder 107
Upon receiving an address signal designating the address of data to be output from the memory core 101, the row decoder 106 turns on the word line of the memory core 101, and the column decoder 107 outputs the signal of each column switch via each column line. A selection signal for selecting one is output, for example, in the order of the column switches 103a, 103g, 103h, and 103b. The column switch that has received the selection signal becomes conductive, and the corresponding sense amplifier outputs the data Da, Dg, Dh, and Db stored in the memory core 101. The data Da, Dg, Dh, and Db are input to the holding circuit 105 through the data line DL.

On the other hand, the dummy column decoder 108 outputs a Set signal and a Reset signal synchronized with the address signal. The dummy amplifier 104 is at a high level when receiving a set signal, and is at a low level when receiving a reset signal.
Outputs a dummy signal that has transitioned to the w level. Delay circuit 1
09 adds a delay to the dummy signal and
Output to

Here, the length of the dummy signal line SL through which the dummy signal passes from the connection portion with the dummy amplifier 104 to the connection portion with the holding circuit 105 is equal to the length of each of the output data lines DL through which the output data passes. Since the length is longer than any of the length from the connection to the column switch to the connection to the holding circuit 105, when the dummy signal and the data are output simultaneously, the dummy signal always lags behind the data. 1
05 is input.

Accordingly, a change point of the dummy signal, that is, a transition point between the high level and the low level, is input to the holding circuit 105 later than a change point of the output data, for example, a change point of the data Da and Dg. 105 holds the already input output data by transition of the dummy signal input immediately thereafter.

FIG. 4 is a diagram for explaining the timing of data holding and output of the holding circuit 105. As shown in the figure, the output data Da, Dg, Dh, Db
Is output to the holding circuit 105 in proportion to the length of the output data line DL through which the output data passes from the connection with each column switch to the connection with the holding circuit 105 and later than the output timing of the selection signal. Is entered.

The first DFF 11 holds and outputs input data when the dummy signal changes from low to high. On the other hand, the second DFF 12 outputs the dummy signal from High.
Holds and outputs input data when transitioning to Low.

When the clock signal changes from low to high, the third DFF 13 outputs the first DFF 1
1 is held and output, and the fourth DFF 14
Holds and outputs the output data of the second DFF 12 when the clock signal transitions from High to Low.
The selector 15 outputs the output of the third DFF 13 when the clock signal is high, and outputs the fourth DF when the clock signal is low.
The output of F14 is selected and output. Therefore, as shown in the figure, the holding circuit 105 holds the data output from the memory block 101 as a dummy signal, and then outputs the data in synchronization with the clock signal.

As described above, according to the semiconductor memory device of the first embodiment, a dummy signal synchronized with the data output from memory core 101 is generated, and the dummy signal is always held immediately after the output data by the holding circuit. When the data is input to the memory core 101, the data output from the memory core 101 is held in the holding circuit 105 based on the transition of the dummy signal input immediately thereafter, and is output in synchronization with the clock signal. Irrespective of the variation in the transfer time, stable data output synchronized with the speeded-up clock signal can be performed reliably.

Note that the load on the dummy signal line SL and the load on the output data line DL may be different. In FIG. 1, the load on the output data line DL is larger by the amount to which each column switch is connected. In such a case, load capacity 1
It is desirable that the load of the dummy signal line SL be equal to the load of the output data line DL by connecting the dummy signal line SL.

(Modification of First Embodiment) FIG. 5 is a block diagram for explaining a semiconductor memory device according to a modification of the first embodiment of the present invention, and shows the configuration of the semiconductor memory device. . In the figure, reference numeral 100 'denotes a semiconductor memory device according to a modification of the first embodiment, which includes a dummy amplifier 104' for generating a dummy signal, and a dummy signal from the high level to the low level or from the low level to the dummy amplifier 104 '. A dummy column decoder 108 ′ that outputs a timing signal that is a signal for transitioning to High, and a point where the dummy amplifier 104 ′ and the dummy column decoder 108 ′ are connected by one dummy column line. Except for this, the configuration is the same as that of the semiconductor memory device 100 of the first embodiment. The dummy amplifier 104 'is configured by a T-type flip-flop in which a toggle signal is fixed. The operation is the same as that of the first embodiment except that the dummy amplifier 104 'generates a dummy signal based on the timing signal output from the dummy column decoder 108'.

That is, as shown in FIG. 6, the dummy column decoder 108 'outputs a timing signal synchronized with the address signal input to the column decoder 107. The timing signal goes low in synchronization with the address signal.
To High and then to Low after a certain period of time. The dummy amplifier 104 'receives the timing signal, and when the timing signal transitions from Low to High, transitions and outputs the dummy signal from Low to High or from High to Low. The delay circuit 109 adds a delay to the dummy signal and outputs the dummy signal to the holding circuit 105.
5 holds the output data of the memory core 101 by the transition of the dummy signal input immediately thereafter. As described above, the semiconductor memory device 10 according to the modification of the first embodiment
Even with 0 ′, the same effect as in the first embodiment can be obtained.

(Embodiment 2) FIG. 7 shows Embodiment 2 of the present invention.
1 is a block diagram for explaining the semiconductor device of FIG. 1 and shows a configuration of the semiconductor memory device. In the figure, 200
Is a semiconductor device according to the second embodiment, which comprises a memory core, a sense amplifier, a column switch, and a dummy amplifier. The memory blocks 201a, 201b, 201c, and 201 output a stored signal and simultaneously output a dummy signal.
201d, a read amplifier (R / A) 202a for amplifying data and a dummy signal output from each memory block,
202b, 202c, and 202d, a holding circuit 203 that holds and outputs data output from each read amplifier based on a clock signal, and a timing of a dummy signal output from each read amplifier and a clock signal, and compares the timings. A comparison circuit 204 for outputting a result, a delay adjustment circuit 205 for holding the comparison result and adding a delay to a clock signal based on an address signal designating data to be output, and outputting the clock signal; , A row decoder 206 for controlling a word line of each memory block, and a column decoder 207 for receiving the address signal and controlling a column switch of each memory block. The comparison circuit 204 is a generally used phase comparator.

FIG. 8 is a block diagram for explaining the details of the delay adjusting circuit 205, and shows the internal structure of the circuit. The delay adjustment circuit 205 receives the address signal and controls a clock signal based on a comparison result of the comparison circuit 204 and a decoder 51 that selects and outputs only memory block information designating a memory block from the address signal. A control circuit 52 for outputting a delay amount control signal for performing the operation, receiving the memory block information and the delay amount control signal, holding the delay amount control signal for each memory block, and outputting the memory block information output from the decoder 51. , A register 53 that outputs the held delay amount control signal, a selector 54 that receives the delay amount control signal, and controls the number of buffer stages, and a clock signal that corresponds to the number of stages set by the selector 54. And a timing generator 55 that outputs the signal after passing through the buffer circuit.

Next, the operation will be described. The semiconductor memory device 200 sets a delay amount for each memory block before outputting data from the memory block. First, in order to set the semiconductor memory device 200 to the pre-access mode for setting the delay amount, the enable signal EN becomes High. In response, the comparison circuit 204 and the delay amount adjustment circuit 2
05 is a comparison mode. The address signal specifies an address in the order of the memory block A 201a, the memory block B 201b, the memory block C 201c, and the memory block D 201d, and each memory block outputs a dummy signal synchronized with the address signal. The read amplifier corresponding to the memory block that has output the dummy signal amplifies and outputs the dummy signal. The output dummy signal is
The signals are sequentially input to the comparison circuit 204.

FIG. 9 is a diagram for explaining the operation of the comparison circuit 204, and shows the timing of the clock signal CLK input to the comparison circuit 204, the input dummy signal, and the comparison result output. FIG. 9A shows a case where there is no difference between the timing of the input dummy signal and the timing of the clock signal CLK. In this case, both the Late signal and the Fast signal indicating the comparison result remain Low. FIG. 9B shows a case where the input dummy signal is later than the clock signal CLK by the time T1. In this case, La which becomes High only for the time T1
Outputs te signal. The Fast signal remains Low. On the other hand, FIG. 9C shows a case where the input dummy signal is earlier by the time T2. In this case, a Fast signal which becomes High only for the time T2 is output. Late signal remains Low.

The delay adjusting circuit 205 receives the Late signal and the Fast signal indicating the comparison result, and the register 53 holds a delay amount control signal for controlling the clock signal CLK in accordance with the memory block information.

Next, the semiconductor memory device 200 enters the access mode when the enable signal EN goes low. An address signal indicating data to be output is input to the row decoder 206, the column decoder 207, and the delay adjustment circuit 205. The memory block specified by the row decoder 206 and the column decoder 207 outputs data to be output, and the read amplifier corresponding to the memory block amplifies the output data. The amplified data is input to the holding circuit 203 through a global data line. The delay adjustment circuit 205 adds a delay to the clock signal CLK based on the input address signal.

That is, the decoder 51 outputs the memory block information to the register 53 from the input address signal. In response to this, the register 53 outputs the delay amount control information corresponding to the memory block indicated by the memory block information to the selector 54 from the stored delay amount control information. Based on the delayed dormitory control information, the selector 54
Sets the number of buffer stages through which the clock signal CLK input to the timing generator 55 passes.

FIG. 10 is a diagram for explaining the operation of the delay adjustment circuit 205.
LK and the timing of the output clock signal CLK ′.

If the delay amount control signal output from the register 53 based on the address signal indicates that there is no timing difference from the clock signal as shown in FIG. The clock signal CLK 'is a signal delayed by one clock (2π) from the input clock signal CLK (FIG. 10 (a)). On the other hand, when the delay amount control signal indicates that it is delayed from the clock signal by the time T1 as shown in FIG. 9B, a delay is added to the input clock signal CLK by one clock and the time T1. And outputs it (FIG. 10 (b)). Also, the delay amount control signal is
As shown in FIG. 9C, when it indicates that the time is earlier than the clock signal by the time T1, the input clock signal CLK
Is output with a delay of one clock.
(c)). The holding circuit 203 holds and outputs the input data based on the delayed clock signal CLK ′.

As described above, according to the semiconductor memory device of the second embodiment, before reading data from a memory block, a dummy signal synchronized with an address signal is output from each memory block, and the dummy signal is held. The timing inputted to the circuit 203 and the timing inputted to the clock signal CLK are compared for each memory block, and the delay amount control information indicating the delay amount added to the clock signal is adjusted based on the comparison result. When the data is held in the circuit 205 and the data is read from the memory block, information corresponding to the memory block indicated by the address signal is selected from the delay amount control information, and the clock signal CLK is determined based on the information.
And the holding circuit 203 holds the input data by the clock signal CLK ′ with the added delay, so that regardless of the variation in the data transfer time, the holding circuit 203 can use It is possible to perform stable and stable data output.

[0039]

According to the semiconductor memory device of the present invention (claim 1), a storage means for outputting stored data based on an address signal, and a high-speed synchronous circuit synchronized with the address signal.
a dummy signal generating means for generating a dummy signal that transitions to gh or Low; a delay means for adding a delay to the dummy signal; holding the output data based on the delayed dummy signal; and converting the held data to a clock signal. And holding means for outputting the data synchronously, so that the data output from the storage means is always held by the dummy signal input to the holding means immediately after the output data, and then synchronized with the clock signal. Thus, stable data output synchronized with the speeded-up clock signal can be performed irrespective of variation in data transfer time.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the delay unit includes a dummy signal line for conducting a dummy signal from the dummy signal generation unit to the holding unit. Since the length is longer than the length of the data line for conducting data from the storage unit to the holding unit, a dummy signal generated in synchronization with the address signal is always input to the holding unit immediately after the output data. The holding means can reliably hold the output data based on the dummy signal.

According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the delay unit loads a dummy signal line for conducting a dummy signal from the dummy signal generation unit to the holding unit. Load capacity
Since the dummy signal generated in synchronization with the address signal is always input to the holding unit immediately after the output data, the holding unit can reliably hold the output data based on the dummy signal.

Further, according to the present invention (claim 4), a plurality of storage means for outputting stored data based on an address signal and outputting a dummy signal which transitions to High or Low in synchronization with the address signal. And when the control signal is in the comparison mode, for each of the storage means, compare the phases of the dummy signal and the clock signal, and output the result of the comparison; and when the control signal is in the comparison mode, Delay adjusting means for storing the comparison result in association with each of the storage means, and adding a delay to the clock signal based on the comparison result of the storage means corresponding to the address signal when the control signal is in the access mode; Holding means for holding and outputting the output data based on the delayed clock signal, so that the clock signal is output from the data output from the storage means. By being input to the holding means immediately, regardless of the variation in the transfer time data, it is possible to perform stable data output reliably synchronized with faster clock signal.

Also, according to the present invention (claim 5), in the semiconductor memory device according to any one of claims 1 to 4, the holding means outputs the output signal when the dummy signal transitions to high or low. A first holding circuit for holding and outputting data, a second holding circuit for holding and outputting the output data when the dummy signal transits to Low / High, and a first holding circuit for holding the output data based on a clock signal. A third holding circuit that holds and outputs the output data of the first holding circuit, a fourth holding circuit that holds and outputs the output data of the second holding circuit based on a clock signal, And a selection circuit for selecting the output of the third holding circuit or the fourth holding circuit based on the signal. Therefore, after the data output from the storage means is securely held, the data is output to the clock signal. Output synchronously Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating an internal configuration of a holding circuit 105.

FIG. 3 is a diagram for explaining output timings of data and a dummy signal.

FIG. 4 is a diagram for explaining how data is held and output by a holding circuit 105;

FIG. 5 is a diagram illustrating a semiconductor memory device according to a modification of the first embodiment of the present invention.

FIG. 6 is a diagram for explaining the output timing of a data dummy signal.

FIG. 7 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention;

FIG. 8 is a diagram for describing an internal configuration of a delay adjustment circuit 205.

FIG. 9 is a diagram for explaining the operation of the comparison circuit 204.

FIG. 10 is a diagram for explaining the operation of the delay adjustment circuit 205.

FIG. 11 is a block diagram illustrating a conventional semiconductor memory device.

[Explanation of symbols]

11: First D-type flip-flop 12: Second D-type flip-flop 13: Third D-type flip-flop 14: Fourth D-type flip-flop 15: Selector 100: Semiconductor storage device 100 ': Semiconductor storage device 101: memory cores 102a, 102b, 102c, 102d, 102e,
102f, 102g, 102h: sense amplifiers 103a, 103b, 103c, 103d, 103e,
103f, 103g, 103h: column switch 104: dummy amplifier 104 ': dummy amplifier 105: holding circuit 106: row decoder 107: column decoder 108: dummy column decoder 108': dummy column decoder 109: delay circuit 110: load capacitance 200: Semiconductor storage device 201a: memory block A 201b: memory block B 201c: memory block C 201d: memory block D 202a, 202b, 202c, 202d: read amplifier 203: holding circuit 204: comparison circuit 205: delay adjustment circuit 206: row decoder 207: column decoder 300: semiconductor memory device 301a: memory block A 301b: memory block B 301c: memory block C 301d: memory block D 302a, 302b, 302c, 302d: read amplifier 303: holding circuit 304: output circuit 306: row decoder 307: column decoder 51: decoder 52: control circuit 53: register 54: selector 55: timing generator

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hironori Akamatsu 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B015 HH01 JJ16 KA38 KB09 KB23 KB35 KB52 KB89 KB91 NN03 PP02 QQ11 5B024 AA03 BA09 BA15 BA18 BA21 BA23 BA29 CA07 CA11 CA27

Claims (5)

[Claims] 1. A storage means for outputting stored data based on an address signal; a dummy signal generation means for generating a dummy signal which transitions to High or Low in synchronization with the address signal; And a delay unit for adding the output data based on the delayed dummy signal,
And a holding means for outputting the held data in synchronization with a clock signal. 2. The semiconductor memory device according to claim 1, wherein the delay means conducts a dummy signal line for conducting a dummy signal from the dummy signal generation means to the holding means, and conducts data from the storage means to the holding means. A semiconductor memory device having a length longer than the length of the data line. 3. The semiconductor memory device according to claim 1, wherein said delay means is a load capacitance for applying a load to a dummy signal line for conducting a dummy signal from said dummy signal generation means to said holding means. Semiconductor storage device. 4. Outputting stored data based on an address signal, and synchronizing with the address signal.
Alternatively, a plurality of storage means for outputting a dummy signal that transitions to Low, and when the control signal is in the comparison mode, for each of the storage means, compare the phases of the dummy signal and the clock signal and output the comparison result. When the control signal is in the comparison mode, the comparison result is stored in association with each of the storage units. When the control signal is in the access mode, the comparison result is stored in the storage unit corresponding to the address signal. A semiconductor memory device comprising: a delay adjusting unit that adds a delay to a clock signal based on the delay clock signal; and a holding unit that holds and outputs the output data based on the delayed clock signal. 5. The semiconductor memory device according to claim 1, wherein said holding means holds and outputs the output data when the dummy signal transitions to High / Low. And a second holding circuit for holding and outputting the output data when the dummy signal transitions to Low / High, and outputting the output data of the first holding circuit based on the clock signal. A third holding circuit for holding and outputting, a fourth holding circuit for holding and outputting output data of the second holding circuit based on a clock signal, and a third holding circuit for holding and outputting the output data of the second holding circuit based on a clock signal. Holding circuit or fourth
And a selection circuit for selecting an output of the holding circuit.