JP2000132495A - Dma device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA(direct memory access) device which reduces the load of data transfer by DMA on a processor and performs efficient data transfer. SOLUTION: The DMA device comprises a transfer control part 10 which sets the memory use areas for respective channels, the transfer source address and transfer destination address of data, the number of transferred bytes, and the ON/OFF state of transfer and transfers the data, a transfer request arbitration part 11 which arbitrates data transfer requests between channels according to specific priority, a memory monitor part 12 which monitors the memory consumption of each channel, and a transfer information monitor part 13 which monitors the order of data processes and other data transfer control information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA device for transferring a large amount of data in a large-scale semiconductor integrated circuit (hereinafter, "LSI").

[0002]

2. Description of the Related Art DMA (Direct Memory Access) is a method of transferring data from a place where data processing is being performed to another place without passing through a processor. With the development of multimedia in recent years, multimedia devices have come to handle image data or audio data having a very large data amount, and accordingly, various high-performance LSIs for multimedia devices have appeared. In the LSI, data transfer between LSI internal blocks, such as memory management and synchronization processing, is generally performed using a DMA device.

FIG. 2 shows the configuration of a conventional DMA device and its peripheral circuits. In the figure, 200 is the above D
The MA device has a plurality of channels corresponding to each block for which data transfer is requested, and controls data transfer between the block and the memory for each channel.

[0004] The DMA device 200 sets a memory use area of each channel, a transfer source address of data, a transfer destination address and the number of transfer bytes, and setting of on / off of transfer.
And a transfer request arbitration unit 21 for arbitrating a data transfer request between channels based on a predetermined priority.
07 and the control bus 208. In addition, the D
The MA device 200 is also connected to a data storage memory 201 that stores data of each block.

The bus 207 is also connected to blocks 203, 204, 205, and 206 for performing predetermined data processing, and data is transferred via the bus 207.

The control bus 208 includes the DMA device 200 and the blocks 203, 204, 205, and 20.
6, the DMA device 200 and the blocks 20
3, 204, 205, and 206, which are connected to a processor 202 for monitoring and controlling the status.
8, the data transfer is controlled by the processor 202.

Next, the operation will be described. Each block 2
Reference numerals 03, 204, 205, and 206 denote data necessary for each data processing from the data storage memory 201 or when data generated by data processing needs to be stored in the data storage memory 201. A transfer request signal is sent to the DMA device 200. The DMA device 200 receives the transfer request signal and causes the transfer control unit 20 to transfer data between the block that has issued the transfer request and the data storage memory 201. At this time, when a transfer request signal is received from a plurality of blocks, data transfer is performed sequentially from a channel with a higher priority based on a predetermined priority.

[0008] The processor 202 includes a block 203,
The progress of the data processing of 204, 205, and 206, the memory consumption of the data storage memory 201, the order of the data processing, and other transfer control information are monitored, and the on / off of data transfer of each channel and the setting of the priority are set. And so on.

[0009]

In the above-described DMA device, the amount of data to be transferred is large because the processor monitors the memory consumption and the transfer control information and controls the data transfer. The number of steps controlled by the processor increases as the control of the data transfer becomes more complicated. Therefore, in order to improve the data transfer speed, it is necessary to increase the speed of the processor and the bus, and as a result, an excessive load is imposed on the processor. However, when the speed of the processor and the bus is increased, L
There is a problem that the power consumption of the SI increases, and there is a limit to improving the transfer speed only depending on the processor and the bus, or performing complicated transfer control only depending on the processor.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a DMA device that reduces the load on a processor and performs efficient data transfer in data transfer by DMA.

[0011]

A DMA device according to the present invention (claim 1) has a plurality of channels for performing data transfer, and a transfer request signal output from a data processing block corresponding to each channel. A DMA device which receives the data and transfers data between the block and the data storage memory. The DMA device monitors the consumption of the data storage memory by the channel for each channel, and sets the memory consumption in advance. A memory consumption monitoring unit that outputs a signal indicating that the threshold value is equal to or greater than the threshold value and / or is equal to or less than the threshold value; Transfer control means for performing data transfer in order from the channel having the highest priority based on the transfer request signal.

Further, the present invention (claim 2) has a plurality of channels for performing data transfer, receives a transfer request signal output from a data processing block corresponding to each channel, and stores the data in a data storage block. Device for transferring data to and from a memory for monitoring data processing time of a block corresponding to a channel for each channel, wherein the data processing time is equal to or more than a predetermined threshold and / or equal to or less than a threshold. A data processing time monitoring means for outputting a signal indicating that the transfer request signal is transmitted, a transfer request arbitration means for changing the priority order indicating the data transfer order of each channel based on the signal, and a priority control based on the transfer request signal. Transfer control means for performing data transfer in order from the channel having the highest rank.

According to a third aspect of the present invention, in the DMA device according to the first aspect, the transfer request arbitration means includes:
When a signal indicating that the memory consumption of the channel is equal to or less than the threshold is received, the priority of the channel is increased.

Further, according to a fourth aspect of the present invention, in the DMA device according to the second aspect, the transfer request arbitration means includes:
When a signal indicating that the data processing time of the block corresponding to the channel is equal to or greater than the threshold is received, the priority of the channel is increased.

Further, according to the present invention (claim 5), in the DMA device according to claim 1 or 2, the transfer request arbitration means stores a channel on which data transfer has been performed for a certain period of time. The priority of the channel is lowered or the data transfer is not performed.

[0016]

Embodiments of the present invention will be described below. FIG. 1 shows the configuration of a DMA device according to the present invention and its peripheral circuits. In the figure, reference numeral 100 denotes the DMA device, which has a plurality of channels corresponding to each block requesting data transfer.
It controls data transfer between a block and a memory or between blocks.

The DMA device 100 sets a memory use area of each channel, a data transfer source address, a transfer destination address, the number of transfer bytes, and a transfer on / off setting.
And a transfer control unit 10 for transferring data, a transfer request arbitration unit 11 for arbitrating data transfer requests between channels based on a predetermined priority, and a memory monitoring unit 12 for monitoring memory consumption of each channel. And a transfer information monitoring unit 13 for monitoring data processing time, transfer order and other data transfer control information of the block.
7 and the control bus 108. Also, the DM
The A device 100 is also connected to a data storage memory 101 that stores data of each block.

The bus 207 is also connected to blocks 103, 104, 105, and 106 for performing predetermined data processing, and data is transferred through the bus 107.

The control bus 108 includes the DMA device 100 and each of the blocks 103, 104, 105, and 10.
6, the DMA device 100 and the respective blocks 10
The processor 102 for monitoring and controlling the states of the control buses 3, 104, 105, and 106 is connected to the control bus 108.
, The data transfer is controlled by the processor 102.

Next, the operation will be described. Each block 1
03, 104, 105, and 106 are used when it is necessary to take out data required for each data processing from the data storage memory 101, or to store data generated by the data processing in the data storage memory 101. , A transfer request signal to the DMA device 100. The DMA device 100 receives the transfer request signal, and
Performs data transfer between the block that has issued the transfer request and the data storage memory 101 or another block.
At this time, when a transfer request signal is received from a plurality of blocks, data transfer is performed sequentially from the block with the highest priority based on the predetermined priority held by the transfer request arbitration unit 11.

The memory consumption monitoring unit 12 monitors, for each channel, the memory consumption of the data storage memory 101 of the channel, and if the memory consumption is equal to or greater than a preset threshold or equal to or less than the threshold. Then, a signal indicating that the memory consumption of the channel is equal to or greater than the threshold or equal to or less than the threshold is output to the transfer request arbitration unit 11. Upon receiving the signal, the transfer request arbitration unit 11 changes a predetermined priority indicating the data transfer order of the channel, and when the output of the signal is stopped, changes the priority of the channel to the predetermined priority. I do. Here, a threshold value for outputting the signal,
The thresholds for stopping the signal need not be the same. The priority is changed by changing the predetermined priority so that data transfer to a channel whose memory consumption is equal to or less than the threshold is preferentially performed.

The transfer information monitoring unit 13 monitors the data processing time of the block, the transfer order and other data transfer control information for each channel, and when the data processing time is equal to or greater than a preset threshold or equal to or less than the threshold. And outputs to the transfer request arbitration unit 11 a signal indicating that the data processing time of the block corresponding to the channel is equal to or greater than the threshold or equal to or less than the threshold. Upon receiving the signal, the transfer request arbitration unit 11 changes a predetermined priority indicating the data transfer order of the channel, and when the output of the signal is stopped, changes the priority of the channel to the predetermined priority. I do. Here, the threshold value for outputting the signal and the threshold value for stopping the signal need not be the same. In the change of the priority, the predetermined priority is changed so that the data transfer to the block whose data processing time is equal to or more than the threshold is preferentially performed. The transfer control unit 10 transfers data to and from the data storage memory 101 in order from the channel with the highest priority among the blocks that transmitted the transfer request, based on the changed priority.

The transfer request arbitration unit 11 stores a channel to which data has been transferred for a certain period of time, and during that period, lowers the priority of the channel or sets so as not to perform data transfer.

As described above, the DMA device 1 of the present embodiment
00, a memory consumption monitoring unit 12 and a transfer control information monitoring unit 13 are provided to monitor the data storage memory consumption and data transfer control information for each channel, Alternatively, since the priority is changed so that the data transfer of the channel corresponding to the block whose data processing time is equal to or more than the threshold is prioritized, efficient data transfer can be performed without imposing an excessive burden on the processor.

The DMA device 100 stores the channel to which data has been transferred for a certain period of time, and decrements the priority of the channel or does not perform data transfer during that period. , And efficient data transfer can be performed without giving unnecessary priority.

In the DMA device according to the above-described embodiment, the transfer request arbitration unit 11 changes the predetermined priority while receiving the output signal of the memory consumption monitoring unit 12 or the transfer control information monitoring unit 13. Then, when the output signal is stopped, the changed priority is changed to a predetermined priority.However, regardless of the output period of the signal, the changed priority is held for a certain period of time. The priority order may be returned.

When the memory consumption monitoring unit 12 or the transfer control information monitoring unit 13 outputs a signal indicating a value equal to or greater than the set threshold value and / or equal to or less than the threshold value, the transfer request arbitration unit 11 receives the signal. The priority is changed and held, and the memory consumption monitoring unit 12 or the transfer control information monitoring unit 13 sets the
The transfer request arbitration unit 11 outputs a signal indicating the threshold value or more,
When the signal is received, the changed priority may be returned to the original priority. In this case, the threshold for changing the priority set in the memory consumption monitoring unit 12 or the transfer control information monitoring unit 13 and the threshold for restoring the priority may not be the same value.

[0028]

According to the DMA device of the present invention (claim 1), the DMA device has a plurality of channels for data transfer and receives a transfer request signal output from a data processing block corresponding to each channel. A DMA device for performing data transfer between the block and the data storage memory, wherein for each channel, a consumption amount of the data storage memory by the channel is monitored, and the memory consumption amount is set in advance. A memory consumption monitoring means for outputting a signal indicating that the value is equal to or greater than a threshold and / or equal to or less than the threshold;
Transfer request arbitration means for changing the priority order indicating the data transfer order of each channel, and based on the transfer request signal,
Transfer control means for performing data transfer in order from the channel with the highest priority, so that the priority is changed based on the amount of data storage memory consumed for each channel, thereby imposing an excessive burden on the processor. Efficient data transfer can be performed without calling.

Further, according to the present invention (claim 2), it has a plurality of channels for performing data transfer, receives a transfer request signal output from a data processing block corresponding to each channel, and A DMA device for transferring data to and from a data storage memory, wherein for each channel, a data processing time of a block corresponding to the channel is monitored, and the data processing time is equal to or greater than a preset threshold value. A data processing time monitoring unit that outputs a signal indicating that the signal is equal to or less than the threshold value; a transfer request arbitration unit that changes a priority order indicating a data transfer order of each channel based on the signal; And transfer control means for performing data transfer in order from the channel with the highest priority. Based on the transmission control information, and change the priority, it is possible to perform efficient data transfer without placing an excessive burden on the processor.

According to the present invention (claim 3), in the DMA device according to claim 1, the transfer request arbitration means receives a signal indicating that the memory consumption of the channel is equal to or less than a threshold value. In this case, the priority of the channel is increased, so that the priority can be changed so that the channel with less memory consumption is prioritized, and efficient data transfer can be performed without imposing an excessive load on the processor. it can.

According to the present invention (claim 4), in the DMA device according to claim 2, the transfer request arbitration means indicates that a data processing time of a block corresponding to a channel is equal to or longer than a threshold value. When a signal is received, the priority of the channel is increased, so that a predetermined priority is given to give priority to data transfer to a block whose data processing is delayed, without placing an excessive burden on the processor. Efficient data transfer can be performed.

Further, according to the present invention (claim 5), in the DMA device according to claim 1 or 2, the transfer request arbitration means stores the channel on which the data transfer has been performed for a fixed period, and during that period, Means that the priority of the channel is lowered or the data transfer is not performed, so that the same channel is not prioritized more than necessary, and the data transfer of the channel is adjusted efficiently. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a DMA device and its peripheral circuits according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a conventional DMA device and its peripheral circuits.

[Explanation of symbols]

 10: Transfer control unit 11: Transfer request arbitration unit 12: Memory consumption monitoring unit 13: Transfer control information monitoring unit 100: DMA device 101: Data storage memory 102: Processor 103, 104, 105, 106: Block 107: Bus 108: control bus 20: transfer control unit 21: transfer request arbitration unit 200: DMA device 201: data storage memory 202: processor 203, 204, 205, 206: block 207: bus 208: control bus

Claims (5)

[Claims] An information processing apparatus has a plurality of channels for performing data transfer, receives a transfer request signal output from a data processing block corresponding to each channel, and performs data transfer between the block and a data storage memory. A DMA device for performing, for each channel, monitoring the amount of data storage memory consumed by the channel and outputting a signal indicating that the memory consumption is greater than or equal to a preset threshold and / or less than the threshold. Memory consumption monitoring means; transfer request arbitration means for changing the priority indicating the data transfer order of each channel based on the signal; and data transfer in descending order of priority based on the transfer request signal. And a transfer control unit for performing the transfer. 2. It has a plurality of channels for performing data transfer, receives a transfer request signal output from a data processing block corresponding to each channel, and receives a transfer request signal between the block and a data storage memory or another block. A DMA device for performing data transfer by monitoring, for each channel, a data processing time of a block corresponding to the channel, and indicating that the data processing time is equal to or more than a predetermined threshold and / or equal to or less than a threshold. Data processing time monitoring means for outputting a signal; transfer request arbitration means for changing the priority indicating the data transfer order of each channel based on the signal; and A DMA device comprising: transfer control means for sequentially performing data transfer. 3. The DMA device according to claim 1, wherein the transfer request arbitration unit increases the priority of the channel when receiving a signal indicating that the memory consumption of the channel is equal to or less than a threshold value. A DMA device, characterized in that: 4. The DMA device according to claim 2, wherein said transfer request arbitration means receives a signal indicating that a data processing time of a block corresponding to the channel is equal to or longer than a threshold value, and sets a priority of said channel. A DMA device characterized by increasing the order. 5. The DMA device according to claim 1, wherein the transfer request arbitration unit stores a channel to which data has been transferred for a certain period of time, and during that period, lowers the priority of the channel. Alternatively, a DMA device that does not perform data transfer.