JP2000132143A - Image display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make correctable an unevenness of output by use of video amplifiers, by detecting a 1T difference outputted from an n-phase A/D converter, and by accumulatively adding up an absolute valve of the detected 1T difference. SOLUTION: After the gain and offset of an input analog image signal are adjusted in video amplifiers 2 and 3 controlled by a microcomputer 10 such that the analog image signal matches with dynamic ranges of A/D converters 4 and 5, the amplified analog image signals are inputted into the A/D converters 4 and 5 to be converted into digital signals. An inverter gate 1 adjusts a sampling clock CLK/2 (i.e., a half clock CLK/2 of an image signal clock CLK) such that the A/D converters 4 and 5 operate out-of-phase 180 degrees. A pixel conversion LSI 11 processes even and odd data outputted from the A/D converters 4 and 5 to display images on a liquid crystal panel module 12. An adder 7 adds the even data latched by a latch 6 to the odd data. An accumulative adder 8 accumulatively adds up the added data from the adder 7 in timing with the sampling clock CLK/2, and outputs the accumulatively added result to the microcomputer 10 as video amplifier control data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an n-phase digital video display device.

[0002]

2. Description of the Related Art (Prior Art 1) FIG. 3 is a block diagram of a video display device for digitizing an analog signal at a sampling frequency fs having a phase difference from each other. In FIG. 3, an analog signal to be digitized is input to two (two-phase) A / D converters 101 and 102. A / D converters are 1
An analog signal is sampled at a sampling frequency fs having a phase difference of 80 degrees and converted into a two-phase digital signal. This is substantially the same as sampling at a sampling frequency of 2 fs. The two-phase digital signals output from the A / D converters 1 and 2 are latched by the latch circuits 103 and 104 so that the timings of the two phases coincide with each other, and the output data of the latch 104 is output from the latch 103. The data is 180 degrees behind the data. Both output data are supplied to digital LPFs 105 and 106. The digital LPFs 105 and 106 are configured to suppress the occurrence of aliasing distortion based on the sampling theorem.

With the above configuration, the same effect as when actually sampling at 2 fs can be obtained at a low sampling frequency fs.

(Prior Art 2) FIG. 4 is a block diagram showing a dot clock reproducing apparatus for automatically adjusting a clock phase.

The signal output from the signal source 200 is such that H and L are repeated for each dot. The difference between the sampled values between adjacent samples is obtained for the result sampled by the A / D converter 201, and the absolute value of the fluctuation amount of the adjacent sample value is obtained from the latch 202, the adder 203, the absolute value detection circuit 204, and the accumulator 205. Take and accumulate. The microcomputer controls the clock phase adjustment circuit so that the accumulated value becomes maximum.

[0006]

However, in the above configuration, when there is variation in each A / D converter,
A level difference occurs in digital data output from the AD converter of each phase, which leads to deterioration of image quality. That is, even if the analog signal input of the same level is present in each A / D converter, the output value of the A / D converter differs due to the variation, and when viewed on the screen, every other vertical line in the horizontal direction is displayed. May be seen.

The present invention solves the above-mentioned problem.
It is an object of the present invention to provide a video display device capable of detecting a level difference between n phases from a T difference, automatically adjusting an analog video level of an A / D converter input, and correcting variations.

[0008]

In order to solve the above-mentioned problems, a video display device according to the present invention comprises one of n-phase AD converter outputs.
By detecting the T difference as data and accumulatively adding the absolute values, the output variation of the n-phase AD converter is corrected using a video amplifier by setting from a microcomputer. Further, the circuit configuration according to the present invention is characterized in that the configuration of the automatic phase adjustment circuit of the dot clock can be taken over as it is.

[0009]

(Embodiment 1) An image display apparatus according to Embodiment 1 of the present invention will be described with reference to FIG. However, this embodiment describes a case where AD conversion is performed in two phases.

FIG. 1 is a block diagram showing a video display apparatus according to Embodiment 1 of the present invention. In FIG. 1, input RGB, CLK, CLK / 2, VD
Are analog video signals, video signal dot clocks, video signal dot clocks divided by two, and vertical synchronization signals, which are input from the outside or from an external block.

The input analog video signal is subjected to gain adjustment and offset adjustment in the video amplifiers 2 and 3 in accordance with the dynamic ranges of the AD converters 4 and 5, respectively. The microcomputers 10 control the video amplifiers 2 and 3. The control flow will be described later.

The analog video signal whose gain has been adjusted is represented by A
The signals are input to the / D converters 4 and 5 and converted into digital signals. The sampling clock for driving the A / D converter is:
The half clock (CLK) of the dot clock of the video signal
/ 2), the A / D converter 4 and the A / D converter 5 are adjusted by the inverting gate 1 so that the phases are different by 180 degrees. Here, the data output from the A / D converter 4 is even
Data and the data output from the A / D converter 5 are odd
Let's call it data. Even data and odd data are input to the pixel conversion LSI 11, subjected to various signal processing, output to the liquid crystal panel module 12, and displayed as an image.

On the other hand, ev output from the A / D converter 4
The en data is latched by the latch 6. A dot clock of a video signal is used as a drive clock for the latch 6. The adder 7 adds the data output from the latch 6 and the odd data output from the A / D converter 5. The output of the adder 7 is cumulatively added at the timing of CLK / 2 by the cumulative adder 8 reset every frame.
The result of the cumulative addition is once latched by the latch 9 using a vertical synchronizing signal, and is input to the microcomputer 10 as data for controlling the video amplifier. The microcomputer 10 controls the video amplifier 3 based on a video amplifier control flow described later.

When a signal of the same level on the entire screen is input to the input video signal, the digital outputs of the A / D converters 4 and 5 should have the same value. Here, the output value may be different due to the influence of variation or the like. At this time, the output of the adder 7 has the following three patterns. Pattern 1 ... Positive Pattern 2 ... 0 Pattern 3 ... Negative In the case of Pattern 1, the microcomputer 11 increases the gain of the analog video signal input to the A / D converter 4 on the odd side. The video amplifier 3 is controlled. Pattern 2
In the case of, the current gain setting is maintained.

In the case of pattern 3, the microcomputer 11 controls the video amplifier 3 so as to reduce the gain of the analog video signal input to the A / D converter 4 on the odd side.

Next, a second embodiment of the present invention will be described with reference to FIG. However, this embodiment describes a case where AD conversion is performed in two phases.

(Embodiment 2) FIG. 2 is a block diagram showing a video display apparatus according to Embodiment 2 of the present invention. In FIG. 2, input RGB, CLK, CL
K / 2 and VD are an analog video signal, a video signal dot clock, a signal obtained by dividing the video signal dot clock by 2 and a vertical synchronization signal, respectively, and are input from the outside or from an external block.

The input analog video signal is subjected to gain adjustment and offset adjustment in the video amplifiers 20 and 21 in accordance with the dynamic ranges of the AD converters 22 and 23, respectively. The microcomputers 30 control the video amplifiers 22 and 23. The control flow will be described later.

The analog video signal whose gain has been adjusted is represented by A
The signals are input to the / D converters 22 and 23 and converted into digital signals. The sampling clock for driving the A / D converter is a half clock (C) of the dot clock of the video signal.
LK / 2), the A / D converter 22 and the A / D converter 23 are adjusted by the inverting gate 24 so that the phases are different by 180 degrees. Here, the data output from the A / D converter 22 is called even data, and the data output from the A / D converter 23 is called odd data. The even data and the odd data are input to the pixel conversion LSI 31, where various signal processing is performed, and the liquid crystal panel module 32
Is output to

On the other hand, e output from the A / D converter 22
The ven data is latched by the latch 25. The clock uses the dot clock of the video signal. Data output from latch 25 and o output from A / D converter 23
The adder 26 adds the dd data. This adder 2
The output of 6 is input to the absolute value detection circuit 27, and the absolute value is obtained. The absolute value is cumulatively added at the timing of CLK / 2 by the cumulative adder 28 reset every frame. The result of the cumulative addition is once latched by the vertical synchronization signal.
The data is latched at 9 and input to the microcomputer 30 as data for controlling the video amplifier. The microcomputer 30 controls the video amplifiers 20, 2 based on the video amplifier control flow described later.
1 is performed.

When a signal of the same level on the entire screen is input to the input video signal, the digital outputs of the A / D converters 22 and 23 should have the same value. Here, the output value may be different due to the influence of variation or the like. At this time, the adder 26
Are the following three patterns. Pattern 1 ... positive, pattern 2 ... 0, pattern 3
Next, this data is input to the absolute value detection circuit 27. 1
In order to perform the correction every vertical cycle, the output of the absolute value detection circuit is input to the accumulator 28, and the output is input to the latch 29 using the vertical synchronization signal as the driving clock. The microcomputer 30 controls the video amplifier 2 so that the value from the latch 29 approaches 0.
1 and 22 are controlled. When the output of the latch 29 approaches 0 most, it can be said that the correction of the two-phase variation is optimal. In addition, when H and L signals are used as input signals for each dot clock, if the control for maximizing the output value of the latch 29 is performed, it can be said that the clock phase is optimal.

That is, the video display device that corrects the variation of the AD converter configured here is the same as the automatic phase adjustment circuit (prior art 2), and can be completely used for the circuit.

Although only the gain is described here, it is easy to guess that the offset can be controlled.

In this embodiment, a video amplifier is used for gain adjustment and offset adjustment.
There is also a method of controlling the reference voltage of the converter. AD
When the control is performed by adjusting the reference voltage of the converter, two types of input signals, that is, a high-level signal and a low-level signal, are prepared, and the high-side and low-side reference voltages of the AD converter may be adjusted, respectively. .

According to the above configuration, the output variation of the n-phase AD converter can be corrected, and even if the output of the AD converter has a level variation, an image can be naturally displayed.

[0026]

As described above, according to the video display device of the present invention, it is possible to provide a video display device capable of displaying a high-quality video even if the A / D converter has variations. Also,
According to claim 3, the circuit can be shared with the automatic phase adjustment circuit,
Variation correction can be realized in the A / D converter at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a video display device according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional video display device.

FIG. 4 is a block diagram of a conventional video display device.

[Explanation of symbols]

 1, 24 Inverting gate 2, 3, 20, 21 Video amplifier 4, 5, 22, 23 A / D converter 6, 9, 25, 29 Latch 7, 26 Adder 8, 28 Cumulative adder 10, 30 Microcomputer 11 , 31 pixel conversion LSI 12, 32 liquid crystal panel module 27 absolute value detection circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 1/10 H03M 1/10 A 1/12 1/12 C F-term (Reference) 2H093 NC13 NC24 NC26 NC50 NC90 ND05 ND09 5C006 AA01 AA22 AF44 AF46 AF51 AF52 AF53 AF61 AF72 AF81 BB11 BC16 BF04 BF11 BF14 BF15 BF16 BF23 BF25 BF27 BF28 BF49 FA16 FA18 FA22 5C080 AA10 BB05 DD05 DD09 DD12 EE17 GG08 AGG01 GG09 A0110

Claims (4)

[Claims] An analog video signal is converted into an n-phase clock (clocks having a phase difference of 2π / n from each other: n> 1).
3. A video display device which performs AD conversion by automatically detecting and correcting a variation between AD conversion n phases by taking a 1T difference. 2. An amplifier for controlling a gain of a video signal input from an external signal source, n AD converters for performing AD conversion in n phases, and a latch for delaying a digitized video signal by one clock. An image display device comprising: an adder; an accumulator; a microcomputer; a pixel conversion circuit for pixel processing; and a liquid crystal display module. 3. An analog video signal is converted into an n-phase clock (clocks having a phase difference of 2π / n from each other: n> 1).
A video display device that performs A / D conversion by automatically detecting and correcting a variation between A / D conversion n-phases by taking a 1T difference, and capable of sharing a circuit with an automatic phase adjustment of a dot clock. . 4. A digitalized amplifier which can be shared with an amplifier for controlling the gain of a video signal input from an external signal source, n AD converters for performing AD conversion in n phases, and an automatic phase adjustment circuit. An image display device comprising a latch for delaying an image signal by one clock, an adder, an absolute value detection circuit, a cumulative adder, a microcomputer, a pixel conversion circuit for pixel processing, and a liquid crystal display module.