JP2003131623A - Correction method and device for liquid crystal display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display unit which suppresses the lowering of image quality and is small in size. SOLUTION: A correcting device of a liquid crystal display unit inputs the detection signals of a minimum value detecting and holding means for the output signal of an A/D converting means and a maximum value detecting and holding means for the output signal of the A/D converting means, and a correcting means comprises an adding and subtracting circuit means which corrects an offset according to the deviation of the output signal of the minimum value detecting and holding means from a previously set minimum value expected level value and a multiplying circuit means which corrects a full-scale error according to the deviation of the output signal of the maximum value detecting and holding means from a previously set maximum value expected level value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for correcting the brightness or contrast of a liquid crystal video / graphics display device used in liquid crystal terminals, televisions and the like.

[0002]

2. Description of the Related Art FIG. 12 shows a configuration example of a liquid crystal display device using a conventional graphic controller. This example
There is a data operation processing unit 10A including a microprocessor 11, a program memory 10, and a data memory 12. Besides, it is composed of a graphic controller 13, a graphic memory 14, an A / D converter 15, and a liquid crystal display element 17 of a display portion. The liquid crystal display element 17 is a normal color TFT liquid crystal (Thin Film T
(Transistor Liquid Crystal),
LCD (Liquid Crystal Display)
y) It is composed of a panel, an LCD driver, a power supply circuit, a backlight unit, and the like. Reference numerals 18 and 14D are data buses (address bus and control signal lines are omitted).
Note that, unless otherwise specified, the same or equivalent items as those described above are represented by the same reference numerals.

The graphic controller 13 performs graphic setting and display control by a display setting and drawing command by a microprocessor, and is usually analog RGB (Red, Green, Blu) due to the limitation of the number of pins.
e) Output a signal. The A / D converter 15 converts the analog RGB signal into digital RGB data and inputs it to the liquid crystal display element 17. For example, in the case of an 18-bit RGB data signal (6 bits × RGB), it is possible to display 256k colors.

Further, conventionally, in order to improve the image quality by increasing the brightness and contrast, improvements have been made from both aspects of liquid crystal devices and signal processing technology (for liquid crystal televisions, Nikkei Microdevice, 2000, 5 " Large-sized liquid crystal televisions that are advancing toward higher image quality "(pp 110-117)). Further, as a conventional technique, Japanese Patent Laid-Open No.
There is a Japanese Laid-Open Patent Publication No. 1-34245. According to this description, image information (luminance, intensity, etc.) is transferred in addition to the digital RGB signal to achieve high image quality.

[0005]

In the above-mentioned prior art, since sufficient consideration is not given to remedy for deterioration of image quality due to variations in characteristics and performances of liquid crystal display elements and display devices themselves, brightness, contrast, There was a problem of color deterioration.
Actually, an offset occurs, and a full-scale sensitivity error also occurs. Even if they are individually inspected and shipped, it is difficult to maintain the specified performance due to aging and the like. In addition, three systems of A / D converters for RGB signals,
There is a problem that a signal processing circuit is required and the device becomes large.

An object of the present invention is to provide a liquid crystal display device capable of improving and relieving the deterioration of image quality of both graphic images and natural images. Another object is to provide a small liquid crystal display device.

[0007]

The above-mentioned problems can be solved by the following method and device. The offset and full-scale correction of a liquid crystal display device including a microprocessor, a graphic memory, a graphic controller, an A / D conversion unit having an RGB output signal of the graphic controller as an input signal, and a liquid crystal display element are performed by the graphic controller. To the test mode, preset the minimum level expected value and the maximum level expected value of the RGB output signal in the set test mode, and set the minimum value and the minimum level of the data obtained by the A / D conversion means. Correction of offset value based on deviation from expected value and correction of full-scale error based on deviation between maximum value of data obtained by A / D conversion means and maximum expected level value, or correction of either one And display the corrected signal. It is characterized in the correction method in the Nau liquid crystal display device.

In the correction, the maximum value or the minimum value is acquired in a predetermined cycle for the RGB signal converted by the A / D conversion means, and the deviation from the maximum level expected value or the minimum level expected value is obtained. It is characterized in that it is corrected and displayed based on the above, and that one A / D conversion means is prepared for the RGB signals, and it is sequentially selected by a selection signal, and the correction processing is performed after A / D conversion. There is.

Further, in the correction device of the liquid crystal display device,
Minimum value detection holding means of output signal of A / D conversion means, maximum value detection holding means of output signal of A / D conversion means, detection signal of minimum value detection holding means and maximum value detection holding means Is used as an input signal, and the correction means performs an offset correction based on the deviation between the preset minimum expected level value and the output signal of the minimum detection holding means, and the preset maximum expected value. It is characterized in that it is composed of a multiplication circuit means for correcting a full-scale error based on a deviation between a level value and an output signal of the maximum value detection holding means.

Selector means for time-divisionally selecting RGB output signals from the graphic controller and sequentially outputting them to one A / D conversion means, and time-division circuit means for generating time-division control signals for the selector means. Is characterized by having. Further, it is characterized in that it has a sample hold means for outputting the RGB output signals from the graphic controller to each one A / D conversion means, and a control signal generating means for giving an output enable signal to the sample hold means. .

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. The system configuration of the entire liquid crystal display device is shown in FIG. FIG. 1 shows a data operation processing unit 1 including a microprocessor 11, a program memory 10, and a data memory 12.
The correction processing circuit 16 is added to the 0A, the graphic controller 13, the graphic memory 14, and the A / D converter 15. Reference numeral 17 is a liquid crystal display element, 20 is a video decoder, and 22 is a video encoder. 18,14
D is also a data bus as in FIG. 12 (address bus,
Control signal lines are omitted). The video decoder and the video encoder are used for capturing a video signal and drawing and synthesizing it with graphic data (however, the effectiveness of the present invention is not impaired without this).

Next, FIG. 2 shows a block processing configuration of the correction processing circuit 16 having the features of the present invention and its surroundings. In FIG. 2, 15R, 15G, and 15B are A for each RGB signal.
A / D converter, 24R, 24G, and 24B are buffer operational amplifiers for RGB signals, 25 is a delay circuit, 16 is a correction processing circuit, and 17 is a liquid crystal display element. CLK0, CL
K1 is a drawing clock and a display clock, respectively. The graphic controller 13 uses the analog RGB signal R
The O, GO, BO, the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC, and the display period signal DISP are output at the timing of the display clock CLK1.

The correction processing circuit 16 has an A / D converter output 8
Bit RGB data DR [7: 0], DG [7: 0],
Digital correction processing is performed on DB [7: 0], and 6-bit RGB data signals DRO [5: 0] and DGO after the correction processing are performed.
[5: 0] and DBO [5: 0] are output to the liquid crystal display element 17. The delay circuit 25 controls the control signals HSYNC and VSYNC.
RGB data DRO, DGO, DBO from C, DISP
Delay signals HSYNCON, V that match the output timing of
It outputs SYNCON and ENB.

FIG. 3 shows a time chart of a signal including a delayed signal. Focusing on the bit signals of (a), (b), and (c) of FIG. 3A, a time delay occurs due to A / D conversion processing and the like. For example, for the signal (b), FIG. Since there is a time delay as shown in FIG.
YNC must be a synchronizing signal that turns on at td, not at time t. This time delay is caused by the delay circuit 25.
Formed by. The buffer amplifiers 24R, 24
G and 24B are unnecessary depending on the configuration of the graphic controller or the A / D converter, and will be omitted in the following description unless otherwise specified.

FIG. 4 is an explanatory diagram of the operating principle of the correction processing circuit. FIG. 4A is an explanatory diagram of offset correction, that is, brightness correction, and FIG. 4B is an explanatory diagram of dynamic range correction, that is, contrast correction. The former is analog RGB signal ERO (voltage amplitude of R signal: horizontal axis, EG
RGB digital data DR [7: 0] for O and EBO as well (A / D conversion result of R signal: vertical axis)
Shows the conversion characteristics of. Offset error DROF [7: 0]
Is the deviation from the expected value of the minimum level (black level), and indicates that if this value is subtracted, the ideal conversion characteristic is corrected (so that the black level is emphasized).

FIG. 4B shows a similar A / D conversion characteristic. When the full scale FS [7: 0] is lower than the expected level FSR [7: 0], the correction process is DRO.
[5: 0] = DR [7: 0] x (FSR) / (FS)
(Takes the upper 6 bits of the operation result). In this case, the white level is corrected so as to be emphasized. That is, since the straight line (a) is corrected like the straight line (b), the contrast can be corrected.

An example in which the above-mentioned correction technique is applied is shown in FIG. Since the overall configuration is the same as that of FIG. 1, the basic part of the present invention will be described with reference to FIG. 5 and the time chart FIG. In this embodiment, the test mode signal TSTMD (FIG. 6A), the black level setting signal 26 (FIG. 6C), and the white level setting signal 27 (FIG. 6) are used in the configuration of FIG.
(B)) is transmitted from the graphic controller 13 to the correction processing circuit 16, and the data acknowledge signal DAC
2 in that K ((E) in FIG. 6) is returned from the correction processing circuit 16 to the graphic controller 13.

The graphic controller 13 outputs the RGB signals RO, G at the timing of generation of the black (minimum value) level setting signal 26 or the white (maximum value) level setting signal 27.
It incorporates means (not shown) for presetting the O and BO levels to the black level or the white level. The graphic controller 13 outputs the test mode signal TSTMD
H "level ((A) of FIG. 6), the correction processing circuit 16
And the black level setting signal 26 or the white level setting signal 27 is transmitted to the “H” level ((B) of FIG. 6,
(C)) to notify the preset timing.

The correction processing circuit 16 informs the data acknowledge signal DACK that the black level or the white level is captured.
Is notified by the "H" level ((E) in FIG. 6), the graphic controller 13 returns TSTMD to the "L" level, and the preset operation is completed. This preset operation is not limited to the power-on time, and its effect can be exerted by executing it at any time by a command from the microprocessor or by executing it at a constant time interval by starting a timer. According to this embodiment, the black and white levels can be set arbitrarily, and in particular, the hardware configuration of the RGB signal generation system,
There is an effect that the conversion error due to the characteristic variation of the liquid crystal display element can be corrected ((D) of FIG. 6 is an example of the R signal).

FIG. 7 shows another embodiment of the present invention. In the circuit configuration of FIG. 2, maximum value / minimum value detection holding circuits 40R, 40
G and 40B are added. The configurations and operations of the maximum value / minimum value detection and holding circuits 40R, 40G, and 40B are the same as each other, and therefore the circuit configuration for the R signal is shown in FIG. 8 for convenience (the same applies to G and B). The maximum value / minimum value detection / holding circuit 40R is the maximum value detection / holding circuit 40R-
1, a minimum value detection holding circuit 40R-2, a maximum value holding register 41 holding a white level, and a minimum value holding register 42 holding a black level. Minimum value, R of the minimum value detector
The signal operation will be described with reference to FIG.

In FIG. 8, first, the preset signal CT
The holding register 42 is set to an initial value by L-R.
After that, the minimum value detection holding circuit 40R-2 receives the RGB signals received.
The data DR [7: 0] and the data in the holding register 42 are compared in magnitude, and if the former is smaller, the detection signal R
The contents of the holding register 42 are rewritten to smaller R data DR [7: 0] by MNDET. Thus, the latest minimum value RMIN is stored in the holding register 42 and output to the correction processing circuit 16. The operation of the maximum value detector is
It is the same as the above except that the maximum value RMAX is sequentially updated to the larger value and the maximum value RMAX is output to the correction processing circuit 16.

Next, the overall operation of FIG. 7 will be described.
A / D conversion output RGB data DR [7: 0], DG
[7: 0] and DB [7: 0] are input to the maximum value / minimum value detection holding circuits 40R, 40G, 40B and the correction processing circuit 16. Maximum value / minimum value detection / holding circuits 40R, 40G,
40B is preset signals CTL-R, CTL-G, CT
It is set to the initial value by L-B, and then the maximum value RMA
X, GMAX, BMAX, minimum values RMIN, GMIN,
BMIN is sent to the correction processing circuit 16. These transmission data are transmission signals RG from the graphic controller.
It is taken into the correction processing circuit 16 at the timing of BTMG1. The sending signal RGBTMG1 may be, for example, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, or another signal having a constant cycle.

In this embodiment, the maximum value (white level) and the minimum value (black level) can be updated every horizontal scanning cycle, every frame cycle, or at every fixed time set by the timer, so that the image data characteristic changes. There is an effect that can be followed. Further, the holding registers 41 and 42 can be set to initial values from a microprocessor or a graphic controller via a bus, so that versatility and image quality control performance can be improved.

An example of the configuration of the correction portion of the correction processing circuit 16 is
It shows in FIG. The correction processing circuit 16 includes an addition / subtraction circuit 44, a multiplication circuit 45, selector circuits 46 and 47, and a decoder circuit 4.
8 and OR gate 49. In addition, in the addition / subtraction circuit 44, a subtracted value holding register (not shown) and a multiplication circuit 45 are provided.
A multiplicand value holding register (not shown) is built therein. The added / subtracted value is determined from the maximum value RMAX and the minimum value RMIN, and the multiplicand value is preset.

The operation will be described with reference to the truth table shown in FIG. 9B. The decoder circuit 48 causes the multiplication signal MUL and the addition / subtraction / multiplication signal SUB / M by the combination of the logical values of the mode signals MD0 and MD1 (pin mode signals).
The UL signal is output like a truth table. In case 1 or case 2, addition / subtraction mode (MUL = “0”, SUB /
MUL = “0”), and the selector circuit 46 sends the adder / subtractor circuit output 50 to the R data DR0 [7: 0]. In case 3, the multiplication mode (MUL = “1”, SUB / M
UL = “0”), and the selector circuit 47 sends the R data output DR [7; 0] to the multiplication circuit input 52.

Since the control signal 53 becomes "1", the selector circuit 46 outputs the multiplication circuit output 51 to the R data DR0.
It is sent at [7: 0]. In Case 4, the addition / subtraction / multiplication mode (MUL = “0”, SUB / MUL = “1”) is set, and the R data output DR [7: 0] passes through the addition / subtraction circuit 44 and the multiplication circuit 45 and the R data DR0 [ 5: 0].

In this embodiment, mode signals MD0 and MD1
Depending on the setting, any of addition / subtraction correction, multiplication correction, and addition / subtraction / multiplication processing can be selected by the program. Further, although the example of the subtraction function is shown in this embodiment, it is obvious that the addition function and the other correction function can be easily added without being limited to this.

FIG. 10 shows an embodiment of miniaturization. In this embodiment, in addition to the graphic controller 13, the correction processing circuit 16, and the liquid crystal display element 17, the selector circuit 29, the single A / D converter 15, and the time division circuit 2 are provided.
It consists of eight. The selector circuit 29 outputs the RGB (component) output signal R of the graphic controller 13.
O, GO, BO are selected by time division, and the A / D conversion means 1
Send to 5. The frequency divider circuit 28 receives the drawing clock CK0 as the reference clock signal and the display (dot) clock CK1 for synchronization (normally, CK0 frequency> CK).
1 frequency). Then, the time-division control signals SELR, SELG, SELB of the selector circuit 29 are generated. For example, the frequency of the drawing clock CK0 is changed to the display clock CK1.
Of the four CK0 cycles and assigned to the time division control signals SELR, SELG, and SELB slots. The time allotted to A / D conversion becomes 1/4,
A / D with a cycle time of about 20 MHz in frequency conversion
Conversion is required, but this does not impair the effect of miniaturization.

FIG. 11 shows another embodiment of miniaturization. In this embodiment, the sample hold circuits 31R and 31R
The feature is that G and 31B are inserted between the graphic controller 13 and the A / D converter 15. The control signal generating circuit 30 draws a drawing clock CK0 as a reference clock signal and a display (dot) clock CK for synchronization.
1 is input, the sample hold circuits 31R, 31G,
31B output enable signals SELSH-R, SELS
H-G, SELSH-B, and RG of the correction processing circuit 16
The B data fetch timing RGBTMG3 is generated.

Similar to the embodiment of FIG. 10, output enable signals SELSH-R, SELSH-G and SELSH-B are used.
Selects and enables the outputs of the sample hold circuits 31R, 31G, and 31B in a time-division manner, and the single A / D converter A
The RGB data DRGB [7: 0] after / D conversion is sent to the correction processing circuit 16. According to this embodiment, the sample hold time can secure one cycle of the display clock CLK.
A margin can be given to the / D conversion time.

In the present invention, in order to improve the image quality, the microprocessor, the graphic memory, the graphic controller, and the R of the graphic controller are used.
A / which converts A / D conversion of GB (component) output signal
In a liquid crystal display device including a D conversion means and a liquid crystal display element, the graphic controller is provided with a test mode setting means, a means for presetting the RGB output signals to a minimum level and a maximum level in the test mode, and A of the preset value. A means for transferring the / D converted data to the correction processing means is provided. This enables offset error and full-scale error correction on the hardware configuration.

In the liquid crystal display device, the A
A minimum value / maximum value detection / holding means of the RGB output data of the D / D conversion means, a means for periodically fetching the output value of the detection / holding means, and correcting the offset and the full scale level are provided, and the correction processing means is provided. The output is supplied to the liquid crystal display device. Correction and extrapolation processing are performed at regular time intervals such as a horizontal scanning period, a field period, or a frame period. Therefore, there is an effect that the image quality can be controlled in real time according to the characteristics of the display image data.

Further, according to the present invention, in order to achieve miniaturization of the liquid crystal display device, the R of the graphic controller is reduced.
A selector means for selecting a GB (component) output signal by time division and outputting it to the A / D conversion means, and a time division control means for generating a time division control signal for the selector means are provided. As another technical means for downsizing, RGB sample hold means to which each RGB output signal of the graphic controller is input,
A sample and hold control means for generating a control signal for the GB sample and hold means, and an A / D conversion means for time-division A / D conversion of each RGB output signal to which the outputs of the RGB sample and hold means are input in time division are provided. I chose According to the above means, only one A / D converter is required, so that it is possible to achieve miniaturization and cost reduction.

A capture explanation will be given with reference to FIG. 1 in which a liquid crystal display device is provided with a video decoder and a video encoder. The video decoder converts the external video input signal into a digital video signal and then outputs the digital video signal to the graphic controller. The video encoder converts display data output from the graphic controller into a video signal. The graphic controller has a function of performing a drawing operation by using the graphic library data in the graphic memory in accordance with a drawing command from the microprocessor, synthesizing the digital video signal and the drawing data, and outputting the display data. According to the present technical means, there is an effect that it is possible to perform fine image quality control according to the characteristics of the image data of the external video input signal and the graphic (display) data.

[0035]

According to the present invention, the maximum value (white level),
Take in the minimum value (black level) regularly or at any time,
Since the brightness correction or the contrast correction is performed, the image quality can be improved. Further, even in the liquid crystal display device hardware configuration, the A / D converter for RGB signals is 1
Since only one piece is required, there is an effect that the size and cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration diagram of the present invention.

FIG. 2 is a block diagram of the present invention.

FIG. 3 is an explanatory diagram of a delay circuit of the present invention.

FIG. 4 is an explanatory diagram showing a basic principle of a correction processing circuit of the present invention.

FIG. 5 is a circuit block diagram showing an embodiment of the present invention.

FIG. 6 is a time chart of FIG.

FIG. 7 is a block diagram illustrating another embodiment of the present invention.

8 is a partial detailed view of FIG. 7. FIG.

FIG. 9 is a block diagram illustrating the configuration of another embodiment of the present invention.

FIG. 10 is a block diagram showing another embodiment of the present invention.

FIG. 11 is a block diagram showing another embodiment of the present invention.

FIG. 12 is a circuit block diagram showing a conventional example.

[Explanation of symbols]

10A; Data operation processing unit 13; Graphic controller 14; Graphic memory 15, 15R, 1
5G, 15B; A / D converter 16; Correction processing circuit 1
7; Liquid crystal display device 18, 14D; Data bus 20;
Video decoder 22; Video encoders 24R, 24
G, 24B; buffer amplifier 25; delay circuit 28;
Time division circuit 30; Control signal generation circuit 31R, 31
G, 31B; sample hold circuit 40R, 40G,
40B; maximum value minimum value detection holding circuit 40R-1; maximum value detection holding circuit 40R-2; minimum value detection holding circuit 4
1; maximum value holding register 42; minimum value holding register
44; Subtraction circuit 45; Multiplication circuit 29, 46, 47;
Selector circuit 48; Decoder circuit 49; NOR gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 611H 623 623N 641 641P (72) Inventor Toshiaki Masuda Sankocho, Hitachi City, Ibaraki Prefecture 2-2-1 Hitachi Engineering Co., Ltd. (72) Inventor Masahisa Narita 3-2-1, Saiwaicho, Hitachi City, Ibaraki F-Term (Reference) 2H093 NA51 NC24 NC28 NC49 NC62 ND04 Hitachi Engineering Co., Ltd. ND06 ND07 ND42 ND54 5C006 AA01 AA22 AF13 AF46 AF51 AF52 AF53 AF54 AF64. AA17 AA18 BB12 KK05

Claims (6)

[Claims] 1. A display correction method for a liquid crystal display device comprising a microprocessor, a graphic memory, a graphic controller, an A / D conversion means using an RGB output signal of the graphic controller as an input signal, and a liquid crystal display element. The test mode is set by the graphic controller, the minimum level expected value and the maximum level expected value of the RGB output signals are preset in the set test mode, and the minimum value of the data obtained by the A / D conversion means and the Correction of the offset value based on the deviation from the minimum level expected value and correction of the full scale error based on the deviation between the maximum value of the data obtained by the A / D conversion means and the maximum level expected value, or either Is corrected and the corrected signal is displayed. Correcting method in a liquid crystal display device, characterized in that. 2. The correction according to claim 1, wherein the correction is for an RGB signal converted by an A / D conversion means,
Acquire the maximum value or minimum value in a predetermined cycle,
A correction method in a liquid crystal display device, wherein correction is performed based on a deviation from the maximum level expected value or the minimum level expected value and display is performed. 3. The RGB according to claim 1,
A correction method in a liquid crystal display device, characterized in that one A / D conversion means is prepared for a signal, the selection signals are sequentially selected, and the correction processing is performed after A / D conversion. 4. A correction device for a liquid crystal display device, which comprises a microprocessor, a graphic memory, a graphic controller, an A / D conversion means using the RGB output signals of the graphic controller as an input signal, and a liquid crystal display element, A minimum value detection holding means of the output signal of the A / D conversion means, a maximum value detection holding means of the output signal of the A / D conversion means, a detection signal of the minimum value detection holding means and a detection signal of the maximum value detection holding means. As an input signal, the correction means is an addition / subtraction circuit means for performing offset correction based on a deviation between a preset minimum value expected level value and an output signal of the minimum value detection holding means, and a preset maximum value expected level value. And a multiplication circuit means for correcting a full-scale error based on a deviation between the output signal of the maximum value detecting and holding means. Correction apparatus in a liquid crystal display device, characterized in that. 5. The selector according to claim 4, wherein the RGB output signals from the graphic controller are selected in a time division manner and sequentially output to one A / D conversion means, and a time division control signal of the selector means. And a time-division circuit unit for generating a correction circuit in the liquid crystal display device. 6. The sample and hold means according to claim 4, wherein the RGB output signals from the graphic controller are output to one A / D conversion means, respectively.
A control signal generating means for applying an output enable signal to the sample and hold means, and a correction device in a liquid crystal display device.