JP2000125463A - Device for controlling continuity and break - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify an abnormal power element, and to reduce costs by a simple circuit configuration by controlling the continuity and break of a power element based on information regarding the abnormality of current and temperature corresponding to a nearly constant period, or a timing being set by a time interval being stored in a storage element or the like in advance. SOLUTION: When overcurrent continuously flows while a switch power element 9a is repeatedly turned on and off, heat is generated in the element by an internal on-resistor. When the heat is detected by a temperature detector 20, a temperature detection voltage 69 is changed. When the temperature detection voltage 69 exceeds a threshold, an overtemperature detection signal 12 is outputted. A latch signal 17a is outputted by the AND operation of the overtemperature detection signal 12 and an overcurrent detection signal 15a, and the Q output of a latch circuit is set to a high level. The latch circuit output 18a is inputted into a break circuit 7a via an OR gate, a gate voltage 23a is set to a low level, and the switch power element 9a is turned off, thus canceling an overcurrent state, and returning the current and temperature to a steady state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for controlling a plurality of power loads in a vehicle, and more particularly, to a safe, inexpensive and detailed protection function for an integrated circuit in which an abnormal overcurrent can flow due to a load short circuit or the like. The present invention relates to a conduction and cutoff control device having the same.

[0002]

2. Description of the Related Art As a conventional technique, a general method is to detect a current supplied to a load and automatically cut off an excessive increase in the current. This is called MOSFET (Metal Oxi
As an application to a deSemiconductor Field Effect Transistor, Japanese Patent Application Laid-Open Nos. 61-261920 and 62-11916
And a number of known techniques such as JP-A-62-143450 and JP-A-63-87128. However, these current sensing techniques sometimes suffer. For example, in a load such as a headlamp of an automobile, if a momentary large current is cut off from the off state to the start of lighting, a smooth lighting operation is impaired. That is, it takes a remarkable time until the lamp is turned on, which hinders the lighting at a required timing. Therefore, the rapid current in the steady use state is indispensable. For this reason, the operation disclosed in Japanese Patent Application No. 8-303018 discloses an operation in which a short circuit of a load or an instantaneous current of a steady load is permitted by monitoring the temperature, not the current, and the current is automatically cut off when an abnormal short circuit occurs. Embodied by However, the authors faced further problems that could not be avoided by this technology. That is when many loads are controlled by one chip integrated circuit.
When using the overcurrent abnormality detection method, every time an overcurrent abnormality occurs,
If the state is shifted to the cut-off state and the automatic return is not performed, it becomes weak against malfunction due to noise. That is, if the state is temporarily shifted to the cut-off state with a large current that is generated instantaneously or suddenly and is not restored, the usability for the user is reduced. After the transition from the overcurrent state to the cutoff state, if the current returns to below the abnormality detection current, the current can be limited to some extent, but if the load short circuit occurs continuously, the semiconductive state continues, This leads to temperature rise and element deterioration. Further, in the method of detecting an excessive temperature, it is not possible to specify which element on the same chip generates heat and is at an abnormal temperature. Also,
Generally, the variation in the circuit for realizing the temperature detection cannot be ignored, and if the accuracy is to be improved, the device must be very expensive.

[0003]

As described above, in a power element having only a single protection function depending on temperature or current, an automatic shutdown is performed by detecting an abnormality in an element for controlling conduction and interruption of current to a plurality of loads. And it is not possible to perform control to return to the appropriate state. Further, the method of detecting and interrupting an abnormality in current or temperature for each load causes a complicated and expensive circuit configuration. The present invention can identify a power element in an abnormal state while achieving both current protection in a conductive state of the power element and an over-temperature protection function that is slightly slower than this but can reliably detect an abnormality, Provided is an improved conduction / cutoff control device which can be realized at a low cost with a simple circuit configuration.

[0004]

Means for solving the above problems include a means for detecting a current abnormality of a power element, a means for monitoring a temperature abnormality near the power element, a substantially constant cycle, or a storage element. Means for controlling conduction and interruption of the power element based on the information on the current abnormality and the temperature abnormality in accordance with a timing set by a previously stored time interval.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the block diagram of FIG. In FIG. 1, reference numeral 1 denotes control signals 21a to 21d for controlling loads 10a to 10d.
A microprocessor that outputs 21d, 2 is a power supply that supplies power to the load, 3a to 3d are switches (switches) that control conduction and interruption of current to the load, and are switches that detect abnormal states of currents flowing through the power elements 9a to 9d. Current detection circuit, 4a-4d
Are over-temperature detection signals 12 output from a temperature abnormality detector 27 for detecting an abnormal heating of the switch power element 9 and over-current detection signals 15a to 15 output from the over-current detection circuit 3.
This is a gate element that performs a logical AND operation with 5d, and outputs latch set signals 17a to 17d. 5a to 5d are latch circuits for holding a state, 6a to 6d are latch signals 18a to 18d output from the latch circuit 5 and overcurrent limit signals 16a to 1 output from the overcurrent detection circuit 3.
The gate elements 7a to 7d which perform the OR operation of 6d, the gate voltages 23a to 23d of the (switch) power element 9 by the cutoff signals 19a to 19d output from the gate element 6
8a to 8d are (switch) semiconductor elements for flowing mirror currents 39a to 39d in an amount substantially equal to the size ratio to the amount of current flowing in the power element 9;
11d is an input circuit, and 22a to 22d are input signals. A logic circuit 100 clears the latch circuit 5 to an initial state in response to a reset signal 91 generated by a reset generator 90 according to a power supply voltage and a reset pulse 14 generated by a pulse generator 26. To generate latch clear signals 14a to 14d. Also, pulse generator 2
To 6, a setting signal 200 for setting the cycle of the return pulse 14 is input from the outside (for example, a microprocessor).

A communication modulator 25 receives a latch set signal 19 and outputs a serial communication signal 29 to the microprocessor 1. The communication modulator is configured to operate by a reference clock signal 81 supplied from a microprocessor.

[0007] A temperature detector 20 detects a temperature rise generated when a current flows through the switch power element 9, and outputs a temperature detection voltage 69.

Reference numeral 13 denotes an integrated circuit in which the above circuits are integrated on one chip, and reference numerals 71a to 71d denote output terminal voltages of terminals to which the load 10 is connected.

The (switch) power elements 9a, 9b, 9c and 9d in the figure can be constituted by bipolar transistors, thyristors and the like.
Description will be made using an FET. In the semiconductor elements 8a to 8d,
(Switch) By supplying currents 39a to 39d (mirror current) at a size ratio (for example, 1/100) with respect to the current flowing through the power element 9, the load current can be monitored with a very small current. It can be substituted by inserting a resistor in series with the load and monitoring the potential difference between both ends, but in this case, the wasted power consumed by the resistor is large. The method of monitoring the voltage drop of the power is advantageous in terms of power.

In FIG. 1, four similar circuits are represented by a suffix a,
Although shown as b, c, and d, the number of circuits is not limited to four and can be extended to any integer (N).

The above embodiment is composed of the respective blocks shown in the following detailed configuration diagrams, and the improved operation desired in the present invention is realized by a process generally summarized below. That is, when the load 10a is turned on as a representative of the circuit of the suffix a, the microprocessor 1 first outputs the control signal 21a. Further, 21a is recognized as a signal 22a inside the element 13. In a normal case, when the (switch) current element 9a shifts to the conducting state, the load 10a supplies a current within a predetermined current range to the element 9a. However, when an excessive current flows due to some abnormality (for example, short-circuit of the load 10a), an excessive value still flows from the predetermined value even though the current is limited to some extent in the element 3a (and the output signal 16a). To set the abnormality detection result signal 15a to the high potential. The detected abnormal signal 15a and the over-temperature detection signal 12 detected by the temperature detector 20 and the temperature abnormality detector 27
(According to the element 4a) sets the latch circuit 5a. The Q output set in the abnormal state is the element 19a
The interruption circuit 7a is shifted to the interruption state via the
a (and simultaneously 8a). If this state is continued, it is not possible to return again, but the pulse generator 26 generates the signal 14 serving as a return trigger at appropriate intervals,
Attempt to clear latch circuit 5a.

When the set signal of the latch circuit 5a is at a low potential, the abnormal state has been released, and the Q output is inverted to low with the clear signal. Here, if the input signal 22a is at the high potential, the (switch) power element 9a is shifted to the conducting state again. In this manner, malfunctions due to noise and the like can be eliminated, and moreover, reliable protection can be provided. Next, the detailed operation of each part of this embodiment will be described in the following detailed configuration diagram,
A description will be given with reference to FIGS.

FIG. 2 is a block diagram showing an example of the input circuits 11a to 11d.

In FIG. 2, 31a is a reference voltage, 32a
Is a comparator. With such a configuration, the control signal 21a from the microprocessor is input and the reference voltage 31
When the value is equal to or larger than a, the input signal 22a is output high. The comparator 32a is for strengthening the noise on the signal 21a and outputting a reliable logic signal at the output, and it is of course possible to configure the comparator 32a with a buffer circuit using transistors. The input signal 22a is input to the gate terminal of the switch power element 9a via the cutoff circuit 7a.

Next, the shutoff circuits 7a to 7d will be described with reference to FIG. As shown in FIG. 3, the shutoff circuit 7a is configured so that a switch can be switched by the shutoff signal 19a. In the normal state (19a: low), since the switch is connected to the terminal 60a, the gate voltage 23a changes according to the input signal 22a. That is, (see FIG. 8 described later)
When the input voltage 22a goes high (as shown in FIG. 4), the gate voltage 23a also goes high, the (switch) power element 9a is turned on, and current flows from the power supply 2 to the load 10a.

Referring to FIG. 4, overcurrent detection circuits 3a-3
d will be briefly described. In the figure, 33a and 35a are comparators, 34a and 36a are constant voltage sources for outputting constant voltage signals 41a and 42a, 37a and 38a are inverters (inverters), 43a is resistors (elements), and 39a is a current signal.
The current 39a is a semiconductor element (for example, a MOS-FET) 8a
Shows the current that flows through. Now, the steady load current is 100 mA, the size ratio between the element 9a and the element 8a is 100: 1,
It is assumed that the current 39a obtained by shunting as described above is 1 milliamp in a steady state, and the resistance value of the resistor 43a is 0.2 kΩ. At steady load current 39a is 1 milliamp, so the voltage drop at 43a is 0.2 volts. Here, when it is desired to limit the maximum limiting current flowing to the load by 10 times, that is, by 1 amp, it is necessary to detect a voltage drop of 2 volts in the resistor 43a. Power supply voltage 12
In the case of volts, by setting the voltage 41a to 10 volts, a signal which becomes high at the maximum limit current or more can be obtained as the signal 16a. This is because the voltage 40a has a potential of 10 volts or less when the voltage is about 10 volts or more at 10 times the steady-state current. That is, 40a is a voltage drop caused by the resistor 43a, and is equal to the power supply voltage− (the resistance 43a × the current 39
a).

Similarly, the voltage 42a is set to 11 volts. Then, when a current of about five times the steady state flows, the voltage signal 40a becomes close to 11 volts, and when the current exceeds that, the voltage signal 40a falls further below 11 volts. As a result, a high potential is generated in the signal 15a. Points 45 and 46 of this example
If an appropriate resistor is inserted in between, it is possible to unify the potential of the voltage sources 34a and 36a to one of them and to share them.

Next, in this state, as shown in the timing charts of FIGS. 1 and 8, when the both ends of the load 10a are short-circuited and the short-circuit state occurs, the following operation is performed.

If the load is shorted and the switch power element 9
Since a is ON, the switch power element 9a
An extremely large current flows in the current state.

At this time, since the switch power element 9a and the semiconductor element 8a form a circuit having a configuration as shown in FIG. 1, a mirror current 39a of an amount substantially proportional to the current flowing through the switch power element 9a due to a short circuit is generated. Element 8
Flow through a.

In the short-circuit state as described above, a very large current instantaneously flows through the switch power element 9a, and accordingly, the mirror current 39a also increases as shown in FIG. Increases, and the voltage drop 40a input to the comparators 33a and 35a also decreases. When the threshold voltages 41a and 42a set for the respective comparators are exceeded, an overcurrent limit signal 16a and an overcurrent detection signal 15a are output as shown in FIG.

Of these, the overcurrent limit signal 16a output from the overcurrent detection circuit 3a is input to the cutoff circuit via the OR gate 6a.

The shutoff circuit 7a has a configuration as shown in FIG. 3 as described above. When the overcurrent limit signal is input via the OR gate, the cutoff signal 19a becomes high, and the switch is switched to the terminal 61a. As a result, the gate voltage 23a, which has been high until now, becomes low, so that the switch power element 9a is turned off and the current amount can be prevented from further increasing. This allows
The switch power element 9a can be prevented from being damaged by overcurrent.

Next, the latch circuits 5a to 5d will be described with reference to FIG. The latch circuit has a set input and a clear input terminal. The latch is set by a latch set signal 17a, and a latch signal 18a is output from the Q output. Also, the latch clear signals 14a to 14d
, And reset to the initial state (Q output: low). Accordingly, when the load is short-circuited as described above and a current abnormality is detected by the overcurrent detection circuit 3a and the overcurrent detection signal 15a is output and the overtemperature detection signal 12 described later is output at the same time, these two The latch set signal 17a is output by the AND of the signal, the latch is set, and the Q output is output high.
The latch circuit set in this way is automatically cleared by the input of the latch clear signal 14 generated by the logic circuit 100, and is initialized (Q output:
).

Next, the temperature detector 20 shown in FIG. 6 will be described in detail.

When the load is short-circuited as described above, a very large amount of current flows through the switch power element 9a. As described above, the overcurrent limit signal 16a prevents the current from flowing more than a predetermined amount. However, the overcurrent limit signal shown in FIG. 8 lowers the gate voltage 23a so that the current does not flow more than the predetermined amount. Therefore, if the amount of current decreases after switching to low, overcurrent flows again as indicated by 39a in FIG. Therefore, the overcurrent continues to flow during the period when the input signal 22a is high.

At this time, since the switch power element 9a is an element composed of a semiconductor (for example, MOS-FET), it has a slight resistance (ON resistance) even when it is ON.
Therefore, when a very large current flows as in the case of a short circuit as described above with respect to the normal state, the switch power element itself generates heat due to its ON resistance.

Further, according to the present invention, as shown in FIG. 1, since the circuits are integrated on a one-chip circuit 13, the heat generated by the switch power element 9a in the short-circuit state as described above is transmitted through the chip to the temperature. It will be transmitted to the detector 20.

Temperature detector 20 and abnormal temperature detector 27
Operates as follows.

FIG. 6 is a configuration diagram showing an example of a circuit of the temperature detector 20 and the abnormal temperature detector 27.

In FIG. 6, 64 is a constant current circuit, 65 is a diode, and 66 is a forward voltage (diffusion voltage) of all diodes. Reference numeral 67 denotes a comparator, reference numeral 68 denotes a reference power supply, reference numeral 70 denotes a temperature threshold voltage serving as a comparison reference of the comparator, and reference numeral 69 denotes a temperature detection voltage generated by a temperature variation of the diode diffusion voltage 66.

When the load is short-circuited, an overcurrent flows and the switch power element 9a generates heat, this heat is transmitted to the vicinity of the diode 65 formed on the same chip, and the temperature near the diode 65 rises. Diode diffusion voltage 66
Since the temperature decreases when the temperature rises, the temperature detection voltage 69 input to the comparator 57 rises according to the temperature rise according to the equation ((power supply voltage) − (diffusion voltage 66)). When this voltage exceeds the temperature threshold voltage 70, the over-temperature detection signal 1
2 is output.

As described above, when the load is short-circuited and a large current flows through the switch power element 9a, the latch circuit is activated by the detection signals generated by the overcurrent detection circuit 3a, the temperature detector 20 and the temperature abnormality detector 27. 5a is set and a latch set signal is output, and the gate voltage 23a of the switch power element 9a (and the semiconductor element 8a) becomes low by the cutoff circuit 7a.

Next, the logic circuit 100, the reset generator 90, and the pulse generator 26 will be described in detail.

FIG. 7 is a circuit example showing details of the reset circuit 90. 7, reference numeral 112 denotes a power supply voltage, 101 denotes a reference voltage serving as a comparison reference of the comparator 105, and 102 denotes a reference voltage.
Is a reference power supply for generating this reference voltage, and 103 is a comparator 1
Reference numeral 06 is a reference voltage serving as a comparison reference, and reference numeral 104 is a reference power supply for generating this reference voltage. 109 and 110 are comparison output voltages output from the comparator, 107 is an inverting buffer, 111 is an inverted output of the comparator output voltage 110,
Reference numeral 108 denotes an AND gate, which outputs 10 from each comparator.
9 and 111 are ANDed and a reset output 91 is output.

FIG. 8 is a block diagram showing an example of a circuit of the pulse generator 2.

In FIG. 8, reference numeral 52 denotes a clock generation circuit,
53 is a clock generated by the clock generation circuit, 51 is a counter, and 200 is a setting signal input from the outside. The comparator 50 compares the output of the count counter 51 with the set value set by the setting signal 200, and outputs a pulse when the count counter matches a predetermined set value. Are reset synchronously to output a re-return pulse 14 in which a pulse is output every predetermined period T1.

FIG. 9 is a timing chart for explaining the operation of the reset generator 90 and the pulse generator 26.

When the power supply rises, the power supply voltage 100 gradually increases. When the power supply voltage exceeds each of the reference voltages 101 and 103, signals such as 109 and 110 (inverted output is 111) in FIG. A reset output 91 is output as an AND output.

The reset output 91 resets the count counter 51, so that a re-return pulse 14 as shown in the figure is output at a predetermined cycle T1.

Further, since the comparison reference value of the comparator can be set by the setting signal 200, the width of the predetermined period T1 can be changed to an appropriate period depending on the case.

FIG. 10 is a block diagram showing one example of the logic circuit 100.

The reset output 91 output from the reset generator ORs the reset output 91 output from the pulse generator 26, and the latch clear signal 14 is output. Thus, the latch circuit 5 is always reset when the power is turned on, and can return to the initial state.

FIG. 11 is a timing chart illustrating the above-described setting of the latch circuit and the clear operation by the re-return signal 14.

In the figure, CHa and CHb indicate one of the channels shown in FIGS. 1A to 1D.

In a normal state, when a high level is input to CHa, the MOS gate voltage of CHa becomes high accordingly, and when a low level is input, the gate voltage becomes low.

When a short circuit occurs, overcurrent and overtemperature are detected by the above operation, and the Q
High is set from the output, and
The gate voltage 23 of S becomes low. As a result, no current flows through the switch power element, and a sufficient time elapses thereafter, so that both the current and the temperature return to a steady state. Thereafter, the re-return pulse 14 output every predetermined period T1
When the cause of the short circuit is removed at this time, the MOS gate of CHa becomes high again when the latch is cleared.

On the other hand, as in the case of CHb, the recovery pulse 14
When a short circuit occurs at the timing near the input of the latch circuit 5, the Q output of the latch circuit 5 is set high and the MOS
The time from when the gate voltage 23 becomes low to when the latch is cleared by the re-return pulse 14 becomes shorter. In this case, the time required for the current or temperature to return to the steady state is not enough, and the abnormal state continues even after the latch is cleared. Therefore, the latch is set again, and the gate voltage becomes low. After a predetermined period T1 has elapsed, the latch is again cleared by the re-return pulse 14, and if the current and temperature are in a steady state at this time, the MO is cleared after the clear.
The S gate voltage becomes high in response to the input of CHb.

Therefore, even if the load is short-circuited and an abnormal state occurs and the Q output of the latch circuit is set to high, the latch circuit is cleared and the initial state is cleared at least a predetermined period T1 after the abnormal state due to the load short-circuit is resolved. Automatically, and the input signal 22 can control the gate voltage 23a.

The overall operation and effect of each block described above will be described with reference to the timing chart of FIG.

First, when a control signal is input from the microprocessor 1 and the input signal 22a becomes high, the switch power element 9a is turned on, a current flows through the load, and the output terminal voltage 7
1a becomes low. In this case, since it is in a steady state, the mirror current 39 and the temperature detection voltage are also in a steady state.

In this state, when the load 10a is short-circuited, the output terminal voltage becomes high as shown in the figure, and a large current flows through the switch voltage element 9a, and at the same time, a mirror current 39a in an amount almost proportional to this current is generated. It increases like 39a of FIG. As a result, a voltage drop occurs due to the resistor 43a in the overcurrent detection circuit 3a, and the voltage drop 40a changes as shown in the figure. When this falls below the overcurrent detection threshold 41a in the figure, the overcurrent detection signal 15a
Is output. Further, the current further increases and the voltage drop increases, and the drop voltage 40a is reduced to the current limit threshold value 42.
If it exceeds a, a current limit signal 16a is output.
The current limit signal 16a is directly input to the cutoff circuit via the OR gate 6a, and turns off the switch power element 9a and the semiconductor element 8a by setting the gate voltage 23a to low. As a result, the current, which has been increasing, starts to decrease. However, when the current drops to a predetermined amount and the drop voltage 40a becomes equal to or higher than the current limit threshold 42a, the current limit signal 16a becomes low and the gate voltage 23a becomes high. , Switch power element 9a and semiconductor element 8a
Turns ON, and the current starts to increase. Thereafter, by repeating this, the current flowing through the switch power element 9a does not flow more than a predetermined amount, and damage to the element due to overcurrent can be prevented.

As described above, the switching power element 9a is
If an overcurrent continues to flow while repeating N and OFF, the element generates heat due to the internal ON resistance. When this heat is detected by the temperature detector 20, the temperature detection voltage 6
9 changes as shown in the figure. This is the temperature detection threshold 70
Is exceeded, an over-temperature detection signal 12 is output. The latch set signal 17a is output by ANDing the overtemperature detection signal 12 and the output overcurrent detection signal 15a, and the Q output of the latch circuit is set to high as indicated by 18a. The output 18a of the latch circuit is input to the cutoff circuit 7a via the OR gate, and the gate voltage 23a is set low to turn off the switch power element 9a. Thus, the overcurrent state is eliminated, and the current and temperature return to the steady state.

After that, when the latch circuit is cleared by the re-return pulse 14 outputted every predetermined period T1, the latch circuit returns to the initial state. In the case of FIG. 12, the short-circuit state is continued. The above operation is repeated.

As described above, even when a plurality of loads are controlled by a circuit configured on one chip by the configuration as in the present embodiment, the abnormality of the element can be obtained by using both the overcurrent detection and the overtemperature detection. It is possible to reliably detect the state and prevent the destruction of the element. Further, even when the element is shut down due to an abnormal state, the state can be maintained for a predetermined time, so that the element can be prevented from being destroyed due to repeated on / off of the element when the abnormal state and the steady state are repeated. Also, after the abnormal state is resolved, the initial state is automatically returned by the re-return pulse, so that the element can be automatically cut off and returned with a simple circuit configuration. Also,
In the overcurrent detection circuit, two types of thresholds, an overcurrent detection threshold and a current limit threshold, are provided.
After the overcurrent is detected, the overtemperature is detected, and the amount of current flowing from when the latch circuit is set high to when the element is cut off can be limited to prevent the element from being destroyed. Further, only when the overcurrent and the overtemperature occur simultaneously, the latch circuit is set and the switch power element is turned off, so that malfunction due to instantaneous overcurrent due to noise or the like can be prevented.

FIG. 13 shows a second embodiment of the present invention according to the present invention.
This will be described with reference to the block diagram of FIG. In FIG. 13, 2
Numeral 04 denotes a logic circuit, which corresponds to the reset signal 91 generated by the reset generator 90 according to the power supply voltage, the reset pulse 14 generated by the pulse generator 26, and the Q outputs 18a to 18d from the latch circuit 5. And the counting circuit 20
It generates count signals 14a to 14d serving as count enable pulses 3a to 203d.

The reset signal 91 from the reset generator 90 is input to the count circuits 203a to 203d.

Reference numerals 205a to 205d denote clear outputs of the count circuit, which clear the latch circuit to an initial state.

Reference numeral 201 denotes a memory means for storing the value of the setting signal 200 input from the outside, and setting signals 202a to 202d indicating the set value to a count circuit 203a.
To 203d.

The other points are the same as in the first embodiment.

Next, the operation in this embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 14 shows a logic circuit 204 in this embodiment.
FIG. 2 is a configuration diagram for explaining details of FIG. The return pulse 14 output from the pulse generator 26 is the Q output from the latch circuit.
AND gates 18a to 18d and count signal 14a
To 14d are output. Thereby, the latch circuits 5a to 5a
The count signal is output only when 5d is set and the Q outputs 18a to 18d go high.

FIG. 15 is a configuration diagram illustrating details of the count circuit 203a.

In FIG. 15, reference numeral 202a denotes a setting signal set from outside, reference numeral 206a denotes an up counter for counting up by enabling the count signal 14a, and reference numeral 207 denotes a comparison circuit.
Is compared with the setting signal 202a, and when they match, a match signal 209a is output. The reset signal 91 output from the reset generator 90 is OR gated with the coincidence signal 209a, and a clear signal 205 is output. When the power is turned on by the clear signal 205, the latch circuit 5a is reset to the initial state by the reset signal, and also when the count value 208a matches the setting signal 202a, the latch circuit 5a is cleared to the initial state. . If they match, the clear signal 205a is also input to the up counter 206a,
The count value is reset to zero.

The effects of this embodiment are as follows.

When an overcurrent flows through the switch power element 9a due to a short circuit caused by the load 10a, the Q output of the latch circuit is set high by the above-described detection of the overcurrent and the overtemperature, and the circuit is shut off. Q of this latch circuit 5a
The output is also input to the logic circuit 204 at the same time, the AND gate is opened, and the count signal 14a is output. The cycle of the count signal is the same as the cycle of the return pulse generated by the pulse generator 26, and thus becomes the predetermined cycle T1. When the count signal of the cycle T1 is input to the count circuit 203a, the number of the count signal is counted by the up counter 206a, and when the count signal reaches a set value set by the set signal 202a, a clear output 205a is output.
The latch circuit 5a is cleared. Therefore, after a high state is set in the latch circuit due to an abnormal state, (for a predetermined period T
Since the latch is cleared after (1 × count value), according to the setting value of the setting signal 202 input from the outside,
The return time from when the latch is set in an abnormal state to when the latch is restored can be freely set.

The count signal 14 is output only when the latch circuit 5 is set to high by the AND gate in the logic circuit 204. Therefore, the up counter 206a counts up only when an abnormal state occurs. . As a result, the time from the latch setting to the return can be set individually for each of the latch circuits 5a to 5d, so that the return time can be controlled according to the type of load.

The up counter 20 shown in FIG.
For 6a, a desired operation can be realized by adopting a configuration in which, for example, the output 18a of the latch circuit is input as a reset signal of the up counter 206a. With such a configuration, the count is incremented when the Q output of the latch circuit is set to high and reset to the initial state when cleared to low, so that the switch power elements 9a to 9d The time from the setting of the latch to the return can be set individually for each, and the return time can be controlled according to the type of load.

Next, another embodiment of the present invention will be described with reference to FIG.

In FIG. 16, 159 is a microprocessor, 151 is a central processing unit, 152 is an output register, 154 is an input register, 150 is a communication demodulator,
57 is a communication modulator, 158a to 158d are input pin commands, 161 is a timer, 156 is a timer interrupt signal, 1
59 is a communication interrupt signal, 162 is an overheat state indicator lamp, 81 is a communication clock, and the same numbers are added to the elements common to the other embodiments. In the above-described embodiment, a part of the automatic shut-off operation based on the detection signals of the over-temperature abnormality and the over-current abnormality is processed outside the microprocessor, but in the present embodiment, almost all of these protection operations are controlled. Is to be completed in the microprocessor.
That is, the temperature abnormality detection signal 12 and the N-bit overcurrent detection signals 15a to 15d are modulated by the communication modulator 157 and demodulated by the communication demodulator 150 which receives the signals. Further, a signal is output to the output port by setting the output register 152 based on these demodulation results and the input pin commands 158a to 158d. These processes are performed by the central processing unit 151.
The timer 16 is used as a trigger signal for starting the processing.
1 and an interrupt signal 156 from the demodulator 150 for communication.
159 are prepared. Also, a routine for monitoring the input pin command pattern may be embedded in the main program. Examples of these processes are shown in FIGS. In general, it can be extended to an N-bit system, but for simplicity, a 4-bit example will be described. Each bit of the output register is A, B, C, D, a bit indicating a temperature abnormality is I0, and a bit indicating an overcurrent abnormality is IA, IB, IC, I
D. Further, an initial reset signal from a reset signal generating circuit (not shown) is input to the microprocessor, whereby the output register and ka, kb,
It is assumed that values such as kc and kd are zeroized. ka, k
Although details of b, kc, and kd will be described later, continuing the conduction trial forever when the load is continuously in a short-circuit state leads to deterioration of the power element. It is a counter prepared to terminate,
The description is limited to the fact that this can be realized by using a memory element in the microprocessor (which can also be externally attached) (in this embodiment, this is referred to as a trial counter value). Communication between the communication modulators and demodulators 150 and 157 is performed by serial communication (a signal sequence serially arranged on the time axis), and a clock for this is transmitted from the microprocessor 159 to the element 1.
3 via line 81, synchronously with I
It is assumed that a signal sequence such as 0, IA, IB, IC, and ID is returned to the microprocessor via the communication signal line 29. The count value set in the timer 161 counts the time T1 described above,
59 is set to be output. That is, the timer sets the interval T1 for repeating the conduction trial. In this example, the cycle of the clock 81 is the timer interrupt signal 159.
It is assumed that communication is performed at a sufficiently short speed, that is, at a sufficiently high speed. At the same time, the communication speed is such that an overtemperature and overcurrent abnormality signal is transmitted to the microprocessor 159 at a sufficiently high speed. If this speed is not fast enough, the power element will continuously conduct and break down in an overheated state. If a sufficient communication speed cannot be obtained with the configuration of the present embodiment, measures such as communicating information of each bit by multi-pin parallel transmission are taken. The operation of the overcurrent detection circuits 3a to 3d in the figure is the same as that of the embodiment of FIG. 1, and is for limiting the current by automatically interrupting the overcurrent with the signals 16a to 16d.

Now, an outline of the communication interruption processing will be described with reference to FIG. When the central processing unit 151 in the microprocessor 159 receives a series of serial data, it receives an interrupt processing element every time one unit is received. Since one unit of information includes a bit I0 indicating a temperature abnormality, this is checked first. If this bit is not set, the signal 163 in FIG. 16 is deactivated and the lamp 162 is turned off in order to cancel the overheat state display. If the user stands upside down, it is considered that the vehicle is in an over-temperature state, so IA to ID are further checked. As mentioned above, the over temperature information monitors the temperature of a certain part of the chip, but it is not possible to specify which power element is overheated,
The overcurrent state is also checked. These I
A ~ corresponding to the bit where 1 stands for A ~ ID
The bit of D is dropped to 0, that is, replaced with a cutoff signal. No processing is performed on the bit in which 1 is not set so as to maintain the previous state. Finally, the lamp indicating the overheating state is turned on. As described above, the process of prompting the interruption by the abnormal signal of both the over-temperature and the over-current is frequently performed every time a series of communication is performed.

Conversely, the operation for prompting conduction is performed by input pin command 158.
It is started at the time of change of a to 158d (particularly, change from low to high: change from cutoff command to lighting command) and at the timing of each interval T1. These frequencies are generally much lower than the communication interrupts. Hereinafter, these processes will be described with reference to the process flowcharts of FIGS. First, FIG. 18 shows a processing example for detecting a change in the input pin commands 158a to 158d. Normally, the pin state is stored in a memory, and whether or not this state has changed is monitored by a main routine or a routine having a considerably high frequency. If this time 1
When 58a changes from low to high, the number-of-trials counter value ka is checked. ka is reset to zero when 158 is low or in the initial state. Accordingly, ka is incremented to 1 at the timing when the pin command prompts the start of conduction. M is usually set to a not so large integer between 5 and 10 to define the number of conduction trials. Usually, since I0 is low, any one of the bits A to D corresponding to the changed pin is set to 1 when the input pin command changes to high by this routine. Thereafter, the operation is shifted to the automatic shut-off operation only when overtemperature and overcurrent are detected in the communication interrupt processing routine described above.

Next, the processing of the timer interrupt processing routine will be described with reference to FIG. This routine basically performs the same processing as the routine of FIG. However, the trigger of this routine is a timer interrupt signal, and the interval is T1. Here, the pin command 158 and the number-of-trials counter value (ka, kb, kc, kd) are checked, and 1 is set to bits (A to D) corresponding to the conduction command. At this time, if the number of trials exceeds M, 0 is inserted. The number of trials (ka, kb, kc, kd) is 0 for the pin command signal.
By resetting it to zero when it is (low), it prepares for counting the number of trials for the next conduction command.

The operation of the embodiment shown in FIG. 16 in which the above is integrated will be described below with reference to the waveform diagram of the main part of FIG. In addition, 1 in FIG.
Reference numerals 70 to 176 indicate time points. In this example, it is assumed that a short-circuit abnormality has occurred at both ends of the load 10c in FIG.
The input pin commands are indicated by 158a to 158d in FIG. 16, the timer interrupt cycle is T1, the waveform 156
It is assumed that a timer interrupt occurs at the rising edge of the pulse. Further, it is assumed that the change of the pin command signal is monitored in a sufficiently short cycle by the processing routine of FIG. First, for the input pin commands 158a, 158b, 158d, normal conduction and cutoff commands are transmitted to the load terminals as input signals 22a, 22b, 22d without abnormality. Meanwhile, 1
Regarding 58c, the change from low to high at time point 170 is detected by the processing routine shown in FIG.
This is shown as a conduction signal in FIG. 2c. When 22c changes to high, the trial count kt value kc has been incremented to one. At this time, since the load 10c is in a short-circuit abnormal state, it appears as a high (high potential) signal at 15c by the overcurrent detection circuit 3c (FIG. 16). Here, before and after the communication signal 29
Before the time point 170, no abnormality is detected in both the overtemperature and the overcurrent. This pattern is drawn below the communication signal. That is, a series of I0, IA, IB, IC and ID following the header portion in synchronization with the clock 81 are all zero. However, when the overcurrent detection signal 15c becomes 1 after the time 170,
Changes to 1. Needless to say, at this time, since the above-described current limiting operation is performed, the signal 16c repeats the inversion operation between the high potential and the low potential. Finally, at time 176, I0 appears in the communication signal 29, and 1 appears in the IC bit.
The microprocessor that has received this performs the zeroing processing of the output bit C by the operation of the communication interrupt processing routine shown in FIG. Thus, the potential of the signal 22c is changed from high to low. Next, 22c is inverted from low to high at the time point 171 when the timer interrupt signal 156 is generated. At this time, the timer interrupt processing routine of FIG. 19 is activated, and kc = 2 is set, and a second conduction trial operation is performed to raise 22c. Then, the above-mentioned overcurrent and overtemperature abnormalities occur, and the operation shifts to automatic shutoff again. Such a series of operations is repeated until kc = M is reached, and thereafter, it is no longer repeated even if the pin command 158c is at the high potential. In the above operation, the overheat state display lamp 162 is turned on when the overtemperature detection is abnormal. The display is performed so as to make it sound, but it is of course possible to replace this with a sound source such as a buzzer.

In the present embodiment, the number of attempts to conduct automatically is set and limited (to ka or the like). However, it is also possible to realize by limiting the time using an individual timer or the like. In the embodiment, only one temperature detector has been described. However, when the number of power elements is large and blocks are arranged in several places in a chip and distributed, a plurality of blocks are arranged in close proximity to each block. It is also possible.

As described above, the present invention can be implemented by actively using a microprocessor.

Each component in each embodiment may be implemented by hardware, or may be implemented by a high-performance arithmetic device such as a microcomputer described later and implemented by software.

In the above description, the element 65a is realized by a multi-stage series connection of a general diode as a temperature detecting element. (Switch) The portions corresponding to the power elements 9a to 9d have to flow a relatively large current, and therefore occupy a considerable area on the chip. If this is assumed to be about 40% on the chip, the pattern shown in FIG. 21 is obtained. In the figure, 180 is an integrated circuit chip, 181a to 181
d is a (switch) power element chip, 182 is a (multistage) diode, and 183 is a constant current circuit arranged on the chip. The multi-stage diode 182 is arranged to detect the heat generation of the power element block, but the prior art does not mention this arrangement. Here, an example in which the multi-stage diode can well monitor the thermal behavior of each power element will be disclosed below.

FIG. 22 shows one embodiment of the present invention devised from this viewpoint. 182a-
182d, and arranged at a position close to each (switch) power element chip. These are connected in series by wiring (made of aluminum or the like) on the chip, and are driven by a constant current source 183. By monitoring the multi-stage diode terminal potential with the above-mentioned temperature abnormality detector 27, it becomes possible to monitor the (switch) power element chip evenly. (Switch) The power element chips are not necessarily arranged on one side of the integrated chip but may be divided into two or more blocks as shown in FIGS. 23 and 24. However, the temperature of each block can be evenly monitored by disposing the multi-stage diodes equally close to the number of blocks. Note that 182ab,
182 cd is a diode.

[0080]

According to the present invention, a power element having an overcurrent protection function having an automatic cutoff function by overcurrent protection is provided with an overtemperature protection function capable of reliably detecting an abnormality while responding slightly more slowly than this. In addition, it is possible to identify and protect a power element in an abnormal state, and realize an improved conduction / cutoff control device which can be realized at a low cost with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram of components of the embodiment of FIG. 1;

FIG. 3 is a block diagram of components of the embodiment of FIG. 1;

FIG. 4 is a block diagram of components of the embodiment of FIG. 1;

FIG. 5 is a block diagram of components of the embodiment of FIG. 1;

FIG. 6 is a block diagram of components of the embodiment of FIG. 1;

FIG. 7 is a block diagram of components of the embodiment of FIG. 1;

FIG. 8 is a block diagram of components of the embodiment of FIG. 1;

FIG. 9 is a main part waveform diagram for explaining the operation of the blocks in FIGS. 7 and 8;

FIG. 10 is a block diagram of components of the embodiment of FIG. 1;

FIG. 11 is a waveform diagram of a main part of the embodiment of FIG. 1;

FIG. 12 is a main part waveform diagram of the embodiment of FIG. 1;

FIG. 13 is a block diagram showing another embodiment of the present invention.

FIG. 14 is a block diagram of components of the embodiment of FIG.

FIG. 15 is a block diagram of components of the embodiment of FIG. 13;

FIG. 16 is a block diagram showing another embodiment of the present invention.

FIG. 17 is a processing flowchart of the microprocessor of the embodiment in FIG. 16;

FIG. 18 is a processing flowchart of the microprocessor of the embodiment in FIG. 16;

FIG. 19 is a processing flowchart of the microprocessor of the embodiment in FIG. 16;

FIG. 20 is a main part waveform diagram for explaining the operation of the embodiment in FIG. 16;

FIG. 21 is a chip diagram illustrating an element of the present invention.

FIG. 22 is a chip diagram for explaining another embodiment of the present invention.

FIG. 23 is a chip diagram for explaining another embodiment of the present invention.

FIG. 24 is a chip diagram for explaining another embodiment of the present invention.

[Explanation of symbols]

1,159 ... microprocessor, 2 ... power supply, 3a-3
d: Overcurrent detection circuit, 4a to 4d: AND gate element, 5a to 5d: Latch circuit, 6a to 6d: OR gate element, 7a to 7d: Cutoff circuit, 8a to 8d: Semiconductor element, 9a to 9d ... (switch) power element, 10a-1
0d: load, 11a to 11d: input circuit, 13: integrated circuit, 14a to 14d: clear signal, 17a to 17d: set signal, 20: temperature detector, 22a to 22d: input signal, 25, 157: communication modulation , 26 ... Pulse generator, 27 ... Temperature abnormality detector, 29 ... Communication signal (line),
32a, 33a, 35a, 67 ... comparator, 64, 183 ...
Constant current circuit, 65, 182 (multistage) diode, 81 ...
Clock signal, 89 ... capacitance, 90 ... reset generator, 1
50: demodulator for communication, 151: central processing unit, 15
2: output register, 154: input register, 158a-
158d: Pin command signal, 161: Timer, 162: Overheat indicator lamp, 180: Integrated circuit chip, 181a-1
81d (switch) power element chips, 182a to 18
2d: diode.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shoji Sasaki 2520 Ojitakaba, Hitachinaka-shi, Ibaraki Co., Ltd. Inside the Automotive Equipment Division of Hitachi, Ltd. (72) Inventor Shuko Okamoto 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. (72) Inventor Ichiro Osaka 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. F term in the factory (reference) 5G030 XX01 YY13 5G053 AA01 BA01 BA06 CA02 EA01 EA03 EA04 EC03 FA05

Claims (16)

[Claims] 1. A power element for conducting or interrupting power supply to a load mounted on a vehicle, current detection means for detecting a current flowing through the power element, and a current voltage for converting the detected current amount into a voltage signal. Converting means; temperature detecting means for changing a voltage signal or a current signal in accordance with the amount of heat generated by the power element; and latch means for maintaining a predetermined state in accordance with outputs from the current detecting means and the temperature detecting means. A return pulse generating means for generating a return pulse for returning the latch means to an initial state; and a conduction / cutoff control means for controlling conduction / cutoff of the power element according to an output of the latch means. A conduction / shutoff control device characterized by comprising: 2. A plurality of power elements for conducting and interrupting power supply to a plurality of loads mounted on a vehicle, a plurality of current detection means for detecting an amount of current flowing for each of the power elements, and the detected amount of current A plurality of current-to-voltage converters, a temperature detector that varies a voltage signal or a current signal according to the amount of heat generated by the plurality of power elements, the plurality of current detectors, and the temperature detector A plurality of latch means for maintaining a predetermined state for each power element in accordance with the output from the plurality of power elements; a return pulse generating means for generating a return pulse for returning the plurality of latch means to an initial state; A plurality of conduction / interruption control means for performing conduction / interruption control for each of the plurality of power elements in accordance with the output of the latch means. 3. The device according to claim 1, further comprising current detection means for setting a plurality of detection thresholds for detecting an amount of current flowing through the power element. Conduction and cutoff control device. 4. The method according to claim 1, wherein the latch means is set to a predetermined state.
A conduction / shutoff control device, wherein the control means is controlled in accordance with an output of the current detection means. 5. The apparatus according to claim 1, further comprising: a return pulse generating means for returning the latch means to an initial state; and a reset generating means for resetting the latch means. Conduction and cutoff control device. 6. The conduction / shutoff control device according to claim 1, further comprising a variable means for varying the return pulse period. 7. The continuity circuit according to claim 1, further comprising a limiter for limiting an output of a return pulse generated by said return pulse generator in accordance with an output of said latch. , Shutoff control device. 8. A counting means according to claim 1, further comprising: a counting means for counting the number of return pulses generated by said pulse generating means; and a count threshold value for setting an output from said counting means to a predetermined value. And a comparing means for comparing with a conduction and cutoff control device. 9. A conduction / shutoff control device according to claim 8, wherein said counting means is reset to an initial state by said latch circuit output. 10. A power element for conducting or interrupting power supply to a load mounted on a vehicle, current detection means for detecting a current flowing through the power element, and a current voltage for converting the detected current amount into a voltage signal. Converting means; temperature detecting means for changing a voltage signal or a current signal in accordance with the amount of heat generated by the power element; and latch means for maintaining a predetermined state in accordance with outputs from the current detecting means and the temperature detecting means. Return pulse input terminal means for inputting a return pulse for returning the latch means to an initial state; conduction / cutoff control means for controlling conduction / cutoff of the power element in accordance with an output of the latch means; A conduction / shutoff control device characterized by comprising: 11. A plurality of power elements for conducting or interrupting power supply to a plurality of loads mounted on a vehicle, a plurality of current detecting means for detecting an amount of current flowing for each of the power elements, A plurality of current-to-voltage converters, a temperature detector that varies a voltage signal or a current signal according to the amount of heat generated by the plurality of power elements, the plurality of current detectors, and the temperature detector A plurality of latch means for maintaining a predetermined state for each power element, a return pulse input terminal means for inputting a return pulse for returning the plurality of latch means to an initial state, A conduction / shutoff control device, comprising: a plurality of conduction / shutoff control means for conducting / shutoff control for each of the plurality of power elements in accordance with outputs of a plurality of latch means. 12. A plurality of power elements for conducting and interrupting power supply to a plurality of loads mounted on a vehicle, and at least one of detecting at least one current flowing through each of the power elements.
Two current detecting means, at least one current-voltage converting means for converting the detected current amount into a voltage signal, and a temperature detecting means using a series-connected diode for changing a terminal voltage according to a heat generation amount of the power element, A microprocessor that outputs a predetermined control signal for each power element in response to outputs from the current detection means and the temperature detection means; and a conduction and cutoff for each power element in response to an output of the microprocessor A conduction / shutoff control device comprising at least one conduction / shutoff control means for performing control. 13. An at least one power element for conducting or interrupting power supply to at least one load mounted on a vehicle, and at least one power element for detecting an amount of current flowing for each power element.
Two current detecting means, at least one current-voltage converting means for converting the detected current amount into a voltage signal, and a temperature detecting means using a series-connected diode for changing a terminal voltage according to a heat generation amount of the power element, At least one latch means for maintaining a predetermined state for each power element according to outputs from the current detection means and the temperature detection means, and a return pulse for returning the latch means to an initial state. A conduction / interruption control device comprising: a microprocessor; and at least one conduction / interruption control means for performing conduction / interruption control for each power element according to the microprocessor output. 14. At least one power element for turning on and off power supply to at least one load mounted on a vehicle, and at least one power element for limiting an amount of current flowing for each power element.
Two current limiting means, at least one overcurrent detecting means for detecting an overcurrent for each power element, and a temperature detecting means using a series-connected diode for changing a terminal voltage according to a heat value of the power element, At least one latch means for maintaining a predetermined state for each of the power elements in response to outputs from the overcurrent detection means and the temperature detection means, and a return pulse for returning the latch means to an initial state. A conduction / interruption control device comprising: a microprocessor for performing conduction / interruption control for each power element in accordance with an output of the microprocessor. 15. At least one power element for turning on / off power supply to at least one load mounted on a vehicle, and at least one power element for limiting an amount of current flowing for each power element.
Two current limiting means, at least one overcurrent detecting means for detecting an overcurrent for each power element, and a temperature detecting means using a series-connected diode for changing a terminal voltage according to a heat value of the power element, At least one latch means for setting a predetermined state for each power element based on a product signal from the overcurrent detection means and the temperature detection means; and a microcontroller for outputting a reset pulse for resetting the latch means to an initial state. A conduction / interruption control device comprising: a processor; and at least one conduction / interruption control means for performing conduction / interruption control for each power element in accordance with the microprocessor output. 16. At least one power element for turning on / off power supply to at least one load mounted on a vehicle, and at least one power element for limiting an amount of current flowing for each power element.
Current limiting means, at least one overcurrent detecting means for detecting an overcurrent for each power element, and a temperature detecting means comprising a plurality of diodes connected in series for changing a terminal voltage in accordance with a calorific value of the power element A plurality of latch means for maintaining a predetermined state for each of the power elements in accordance with outputs from the overcurrent detection means and the temperature detection means; and a return pulse for returning the latch means to an initial state. A microprocessor for outputting, and at least one conduction / interruption control means for conducting / interrupting control for each of the power elements in accordance with the microprocessor output; A conduction / shut-off control device characterized by being distributedly arranged in different locations.