JP2000125201A - Charge detector, charge transfer device mounted therewith and solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge detector that matches the gain so as to always conduct excellent resetting even when a power supply voltage is fluctuated and can use an external small capacitance decoupling capacitor, to provide a charge transfer device mounted with the charge detector and to provide a solid-state image pickup device. SOLUTION: In the charge detector provided with a reset gate bias circuit 20 that gives a bias voltage Vrg to the gate electrode of a reset transistor(TR) 15 resetting the potential of an FD area 12 to a prescribed potential and with a reset drain bias circuit 30 that gives a bias voltage Vrd to a drain electrode of the reset TR 15, a 2-stage source follower circuit configuration is adopted for the reset drain bias circuit 30, and a 1st stage source follower circuit has a gain similar to that of the reset gate bias circuit 20 and the gain of a 2nd stage source follower circuit is similar to the gain of the reset TR 15 that has a gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a charge detecting device for detecting a signal charge and converting the signal charge into an electric signal, and a charge transfer device and a solid-state imaging device having the same.

[0002]

2. Description of the Related Art A charge transfer device and a solid-state imaging device are provided with a charge detection device for detecting a signal charge transferred by a charge transfer unit and converting the signal charge into an electric signal. The applicant of the present invention has proposed a charge detection device having a configuration capable of always guaranteeing the operating point of the reset transistor even in a wide range of power supply voltage changes (Japanese Patent Application No. 09-0928).
-015387). FIG. 3 shows the configuration of the conventional charge detection device.

In FIG. 3, for example, a signal charge transferred by the horizontal transfer register 101 is stored in an end of a horizontal transfer register (denoted as H register in the figure) 101 of a CCD solid-state image pickup device. A floating diffusion (floating capacitance) region (hereinafter, referred to as an FD region) 102 is provided. The signal charges stored in the FD region 102 are detected by the charge detection circuit 103, converted into electric signals, and output from the output terminal 104 to the outside.

Further, a reset transistor 105 for resetting the potential of the FD region 102 to a predetermined potential is provided. The reset transistor 105 has a source electrode in the FD region 102 and a gate electrode in the reset terminal 1.
06 respectively. A reset gate pulse φRG is applied to the reset terminal 106 via an external capacitor 108 provided outside the chip 107.

On the chip 107, a reset gate bias circuit 110 for applying a bias voltage Vrg to the gate electrode of the reset transistor 105, and a bias voltage Vrd for the drain electrode of the reset transistor 105
Is provided.

The reset gate bias circuit 110 includes a drive transistor (memory transistor) 111 having a drain electrode connected to the power supply terminal 109 and having a memory effect capable of accumulating charges in a gate insulating film, and a gate electrode of the drive transistor 111. A resistor 112 connected between the drive transistor 1 and the drain electrode
11 connected between the source electrode 11 and the ground
13 and a source follower circuit configuration.
The source electrode of drive transistor 111 is connected to the gate electrode of reset transistor 105, and applies a bias voltage Vrg to the gate electrode.

The reset drain bias circuit 120 also has
It has the same circuit configuration as the reset gate bias circuit 110. That is, the drain electrode is connected to the power terminal 109.
, A drive transistor 121 having a memory effect capable of storing charges in a gate insulating film, a resistor 122 connected between a gate electrode and a drain electrode of the drive transistor 121, and a source electrode of the drive transistor 121. A source follower circuit configuration including a resistor 123 connected between the reset transistor 105 and the ground is provided. The source electrode of the drive transistor 121 is connected to the drain electrode of the reset transistor 105 to apply the bias voltage Vrd to the drain electrode. It has become.

[0008]

In the conventional charge detecting device having the above configuration, the reset gate bias circuit 11
A drive transistor (source follower transistor) 111 having a memory effect of 0 has a depletion structure, and a drive transistor (source follower transistor) 12 having a memory effect of a reset drain bias circuit 120.
Gain matching is achieved by making 1 a neutral structure.

However, the reset gate bias circuit 1
Due to the depletion structure of 10, for example, in a CCD solid-state imaging device, when performing an electronic shutter operation of sweeping out signal charges of pixels to a semiconductor substrate, the reset gate bias circuit 110 is affected by a shutter pulse applied to the substrate, that is, Due to the back gate effect of the drive transistor 111, an external capacitor 10 for decoupling is used.
There is a problem that the capacitance value of the capacitor 8 becomes large, and it is difficult to incorporate the external capacitor 108 (on-chip).

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to perform gain matching so as to always perform a good reset operation even when there is a fluctuation in power supply voltage, and to perform decoupling. It is an object of the present invention to provide a charge detection device capable of reducing the external capacitance for the above, and a charge transfer device and a solid-state imaging device equipped with the same.

[0011]

According to the present invention, there is provided an FD region for storing signal charges, a detection circuit for detecting the signal charges stored in the FD region, and a reset transistor for resetting the potential of the FD region to a predetermined potential. A reset gate bias circuit that applies a bias voltage to the gate electrode of the reset transistor; and a reset drain bias circuit that applies a bias voltage to the drain electrode of the reset transistor. One source follower circuit having the same gain as the bias circuit,
The other source follower circuit having the same gain as the gate electrode of the reset transistor has a two-stage source follower configuration.

In the charge detection device having the above configuration, one of the source follower circuits of the reset drain bias circuit has the same gain as the reset gate bias circuit, and the other source follower circuit has the same gain as the gate electrode of the reset transistor. Gain matching can be achieved even if the reset gate bias circuit does not have a depletion structure. As a result, the reset gate bias circuit does not receive the influence of the shutter pulse when applying the substrate, that is, the back gate effect of the drive transistor, so that the capacitance for decoupling can be reduced. The charge detection device is used as a charge detection unit of a solid-state imaging device or a charge detection unit of a charge transfer device.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows, for example, CC
1 is a circuit diagram illustrating a configuration of a charge detection device according to an embodiment of the present invention, which is mounted on a D solid-state imaging device.

In FIG. 1, the signal charge transferred by the horizontal transfer register 11 is stored at the transfer destination end of a horizontal transfer register (referred to as an H register in the figure) 11 of the CCD solid-state imaging device. An FD (floating diffusion; floating capacitance) region 12 is provided. The signal charges stored in the FD region 12 are converted into electric signals by the charge detection circuit 13 and output from the output terminal 14 to the outside.

A reset transistor 15 for resetting the potential of the FD region 12 to a predetermined potential is provided. The reset transistor 15 has a source electrode connected to the FD region 12 and a gate electrode connected to a reset terminal 18 via a capacitor 17. Reset terminal 1
8 has a reset gate pulse φ
RG is applied.

A reset gate bias circuit 20 for applying a bias voltage Vrg to the gate electrode of the reset transistor 15 and a reset drain bias circuit 30 for applying a bias voltage Vrd to the drain electrode of the reset transistor 15 are further provided on the chip 19. I have.

The reset gate bias circuit 20 includes a drive transistor (memory transistor) 21 having a drain electrode connected to the power supply terminal 16 and having a memory effect capable of accumulating charges in a gate insulating film, and a gate electrode of the drive transistor 21. And a load resistor 23 connected between the source electrode of the drive transistor 21 and the ground, and a source follower circuit configuration including a load resistor 23 connected between the source electrode of the drive transistor 21 and the ground. Electrode is reset transistor 1
5 to apply a bias voltage Vrg to the gate electrode.

In the drive transistor 21 having a memory effect of the reset gate bias circuit 20, the gate insulating film is, for example, a MONOS in which a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN) and a silicon oxide film are sequentially laminated. (Metal Oxide Nitride Oxide Semic
onductor) structure. The reset gate bias circuit 20 functions as a low clamp circuit exhibiting diode characteristics, and the clamp potential is the output voltage of the drive transistor 21.

On the other hand, the reset drain bias circuit 30
Has a two-stage source follower circuit configuration. Then, in this reset drain bias circuit 30,
The first-stage source follower circuit has the same circuit configuration as the reset gate bias circuit 20, that is, a drive transistor 31 having a memory effect capable of storing a charge in a gate insulating film with a drain electrode connected to the power supply terminal 16, and Gate electrode of drive transistor 31 and power supply terminal 16
And a load resistor 33 connected between the source electrode of the drive transistor 31 and the ground.

The source follower circuit of the second stage includes a drive transistor 34 having a drain electrode connected to the power supply terminal 16 and a gate electrode connected to the source electrode of the drive transistor 31 of the first stage. And a load resistor 35 connected between the source electrode and the ground. Then, the source electrode of the second-stage drive transistor 34 is connected to the drain electrode of the reset transistor 15, and the bias voltage Vrd is applied to the drain electrode.

The drive transistor 31 having the memory effect of the first source follower circuit of the reset drain bias circuit 30 also has a gate insulating film such as a silicon oxide film, like the drive transistor 21 of the reset gate bias circuit 20. A MONOS structure in which a silicon nitride film and a silicon oxide film are sequentially stacked is used.

Incidentally, the reset gate bias circuit 2
In the charge detection device having 0 and the reset drain bias circuit 30, the gain of the reset drain bias circuit 30 is ideally the product of the respective gains of the reset gate bias circuit 20 and the gate electrode of the reset transistor 15. Therefore, it is necessary to make the gain very low. Considering the potential variations of the reset gate bias circuit 20 and the gate electrode of the reset transistor 15, the reset drain bias circuit 3
It is desired to use a circuit having the same variation as 0 for both.

Therefore, in the charge detection circuit according to the present embodiment, the reset drain bias circuit 30 has a two-stage configuration of a source follower as described above. In the reset drain bias circuit 30, the first-stage source follower circuit has the same circuit configuration as that of the reset gate bias circuit 20 to match gain and variation, and the second-stage source follower circuit is equivalent to the reset transistor 15. Is configured to match gains and variations.

More specifically, when a memory-type bias circuit having a MONOS structure is used as the reset gate bias circuit 20 as described above, a bias source having the same structure is also used in the first-stage source follower circuit of the reset drain bias circuit 30. Use a circuit. Here, the difference between the two is that some Vt
h (threshold voltage). Thereby, the matching of the gain and the variation can be completely achieved. Therefore, there is no problem at all even if the drive transistors 21 and 31 of the bias circuits 20 and 30 have a neutral structure to reduce the gain.

As described above, the drive transistor 21 of the reset gate bias circuit 20 and the drive transistor 3 of the first stage of the reset drain bias circuit 30
In the CCD solid-state imaging device, when the electronic shutter operation for sweeping out the signal charges of the pixels to the semiconductor substrate is performed in the CCD solid-state imaging device, the reset gate bias circuit 20 is affected by the shutter pulse applied to the substrate. That is, since the back gate effect of the drive transistor 21 is no longer received, the capacitance value of the capacitor 17 for decoupling can be small. As a result, the capacity 17 can be built in the chip 19, that is, on-chip.

The reset drain bias circuit 30
, A transistor having the same structure as the reset transistor 15 is used as the drive transistor 34 of the second-stage source follower circuit. Here, the difference between them is a slight Vth adjustment and a transistor size (channel width W / channel length L). Reset transistor 1
5 is generally formed in a small size in order to reduce the parasitic capacitance of the FD region 12 which is a charge-voltage converter. Accordingly, the size of the drive transistor 34 of the second source follower circuit of the reset drain bias circuit 30 may be reduced.

However, both are operations in which the drain-source voltage difference Vds is almost constant, the short channel effect is unlikely to appear, and the drive transistor 34 of the reset drain bias circuit 30 is large for the small size of the reset transistor 15. Good gain matching can be achieved even in terms of size. If there is a deviation in the gain, the size and profile of the transistor or the thickness of the gate oxide film may be adjusted intentionally.

For example, when the size of the reset transistor 15 is extremely small, the gain may decrease due to the narrow channel effect. In this case, the reset transistor 15 has a depletion structure, and the drive transistor 34 of the source follower circuit of the second stage of the reset drain bias circuit 30 has a neutral structure to achieve gain matching. Then, the reset drain bias circuit 30 is not affected by the shutter pulse, the gain of the reset transistor 15 is improved, and the dynamic range of the FD region 12 is easily set (or the amplitude of the reset gate pulse φRG can be reduced).

The adjustment of the variation of the operating point of the reset transistor 15 can be achieved by adjusting the reset gate bias circuit 20 or adjusting the first-stage source follower circuit of the reset drain bias circuit 30.

That is, for example, the reset transistor 1
In the case where the potential of the gate electrode 5 shifts in the positive potential direction, the reset gate bias circuit 20 may be adjusted to lower the value of the bias voltage Vrg of the gate electrode in the negative potential direction. Is shifted in the negative potential direction, the first-stage source follower circuit of the reset drain bias circuit 30 is adjusted to lower the value of the bias voltage Vrd of the drain electrode in the negative potential direction. Operating point can be guaranteed.

In this embodiment, in the reset drain bias circuit 30, the first source follower circuit has the same gain as the reset gate bias circuit 20, and the second source follower circuit has the gate of the reset transistor 15 in the reset drain bias circuit 30. Although the configuration has a gain equivalent to that of the electrode, when the variation of the reset transistor 15 does not need to be adjusted or shifts only in the positive potential direction,
Since adjustment by the reset drain bias circuit 30 is not necessary, the first-stage source follower circuit and the second-stage source follower circuit may be exchanged.

Further, the current consumption of the first-stage source follower circuit of the reset gate bias circuit 20 and the reset drain bias circuit 30 is very small only by the idling current at the time of reverse bias of the low clamp circuit.
Therefore, if an attempt is made to realize a bias circuit having the same current consumption by, for example, a resistance dividing circuit, the area occupied by the circuit becomes extremely large because a high-resistance resistor element is required. However, by employing a source follower circuit configuration, The area occupied by the circuit can be reduced.

The charge detection device according to the present embodiment described above is used as a charge detection unit provided at the subsequent stage of the horizontal transfer register in, for example, an interline transfer type CCD area sensor as shown in FIG. In addition,
The transfer method of the CCD area sensor is not limited to the interline transfer method.

In FIG. 2, a plurality of sensor units (pixels) which are arranged in a matrix in the row (vertical) direction and the column (horizontal) direction, convert incident light into signal charges having a charge amount corresponding to the light amount, and accumulate the signal charges. ) 41 and a plurality of vertical transfer registers provided for each vertical column of the sensor units 41 and for vertically transferring signal charges read from each sensor unit 41 via a read gate unit (not shown). An imaging area 43 is formed by the image processing area 42.

In the image pickup area 43, the sensor unit 4
Reference numeral 1 denotes a PN junction photodiode, for example. The vertical transfer register 42 is driven to be transferred by, for example, four-phase vertical transfer pulses φV1 to φV4, and transfers the signal charges read from each sensor unit 41 to one scanning line (one line) in a part of the horizontal blanking period. The corresponding portions are sequentially transferred in the vertical direction.

A horizontal transfer register 44 is provided below the imaging area 43 in the drawing. Signal charges corresponding to one line (one scanning line) are sequentially transferred from each of the plurality of vertical transfer registers 42 to the horizontal transfer register 44. The horizontal transfer register 44 is driven by, for example, two-phase horizontal transfer clocks φH1 and φH2, and transfers the signal charges for one line transferred from the plurality of vertical transfer registers 42 in a horizontal scanning period after the horizontal blanking period. Transfer sequentially in the horizontal direction.

At the end of the horizontal transfer register 44 on the transfer destination side, a charge detection section 45 having a floating diffusion amplifier configuration is provided. As the charge detection unit 45, the charge detection device according to the above-described embodiment is used. According to this, the charge detection device is connected to the power supply voltage VDD
Reset transistor 1 for a wide range of changes
5 operating points can be guaranteed, miniaturizing the device,
With the trend of low power consumption, the power supply voltage VDD is changed from 15V to 1
Even in the transition period when the voltage changes to 2V, a CCD area sensor that can normally operate at both 15V and 12V can be realized.

In the present application example, the case where the present invention is applied to the charge detection section of the CCD area sensor has been described. However, the present invention is not limited to this. For example, a CCD linear sensor detects a signal charge and converts it into an electric signal. The present invention is applicable to all solid-state imaging devices having a charge detection unit, and is applicable not only to the charge detection unit of the solid-state imaging device but also to a charge detection unit of a charge transfer device such as a charge detection unit of a CCD delay element. .

[0039]

As described above, according to the present invention,
The reset drain bias circuit has a two-stage source follower circuit configuration, and one source follower circuit has the same gain as the reset gate bias circuit, and the other source follower circuit has the same gain as the gate electrode of the reset transistor. A good reset operation can always be performed even if there is a power supply fluctuation, and gain matching can be achieved without using a depletion structure in the reset gate bias circuit. Accordingly, since the reset gate bias circuit is not affected by the shutter pulse when applying the substrate, the capacity of the decoupling capacitor can be reduced, and accordingly, the capacity can be made on-chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a charge detection device according to one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing a CCD area sensor according to the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

11 horizontal transfer register, 12 FD (floating diffusion) region, 13 charge detection circuit, 15
Reset transistor, 20 reset gate bias circuit, 21, 31 drive transistor having a memory effect, 23, 33, 35 load resistance, 30 reset drain bias circuit

Claims (7)

[Claims] A floating capacitor for storing the signal charge; a detection circuit for detecting the signal charge stored in the floating capacitance; a reset transistor for resetting the potential of the floating capacitance to a predetermined potential; and a gate of the reset transistor. A charge detection device comprising: a reset gate bias circuit that applies a bias voltage to an electrode; and a reset drain bias circuit that applies a bias voltage to a drain electrode of the reset transistor, wherein the reset drain bias circuit has a two-stage source follower. Charge detection, wherein one of the source follower circuits has a gain equivalent to the reset gate bias circuit and the other source follower circuit has a gain equivalent to the gate electrode of the reset transistor. apparatus. 2. The two-stage source follower circuit,
2. The first-stage source follower circuit has a gain equivalent to that of the reset gate bias circuit, and the second-stage source follower circuit has a gain equivalent to the gate electrode of the reset transistor. Charge detection device. 3. The reset gate bias circuit has a source follower circuit configuration, and each source follower transistor of the reset gate bias circuit and the reset drain bias circuit has a neutral structure. Charge detection device. 4. The charge detection device according to claim 3, wherein said reset transistor has a depletion structure. 5. The reset drain bias circuit according to claim 1,
2. The charge detection device according to claim 1, wherein a transistor having a memory effect is used in at least a first-stage source follower circuit. 6. A charge transfer unit for transferring a signal charge, a floating capacitor for storing the signal charge transferred by the charge transfer unit, a reset transistor for resetting a potential of the floating capacitor to a predetermined potential, and the reset transistor. A reset gate bias circuit for applying a bias voltage to a gate electrode of the charge transfer device, and a reset drain bias circuit for applying a bias voltage to a drain electrode of the reset transistor, wherein the reset drain bias circuit has two stages. A source follower circuit having a gain equivalent to that of the reset gate bias circuit,
A charge transfer device, wherein a second-stage source follower circuit has a gain equal to a gate electrode of the reset transistor. 7. A plurality of pixels, a charge transfer unit for transferring signal charges obtained in the pixels, a stray capacitance for accumulating the signal charges transferred by the charge transfer unit, and a potential of the stray capacitance being predetermined. A solid-state imaging device comprising: a reset transistor that resets to a potential; a reset gate bias circuit that applies a bias voltage to a gate electrode of the reset transistor; and a reset drain bias circuit that applies a bias voltage to a drain electrode of the reset transistor. The reset drain bias circuit includes a two-stage source follower circuit, and the first-stage source follower circuit has a gain equivalent to that of the reset gate bias circuit;
A solid-state imaging device, wherein the second-stage source follower circuit has a gain equivalent to that of the gate electrode of the reset transistor.