JP2000124811A - Communication data processor and data receiving system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain reduction of load upon a CPU needed for cyclic redundancy check(CRC) error decision processing by equipping a CRC operation circuit and enabling it to decide whether or not there is a CRC error by a logical value of n-th word of a CRC code. SOLUTION: Information data are separated from inputted communication data, and CRC redundancy for CRC error detection is successively calculated on the separated information data. In this case, a CRC operation circuit is had which substitutes a value coding a first to the n-th words of the whole information data CRC redundancy as a whole into a word length 1 by a logical sum for the n-th word of the CRC code. Then, it is made possible to decide whether or not there is a CRC error by the logical value of the n-th word of the CRC code. Thus, notification to a CPU is enabled by substituting existence/non-existence of the CRC error for the CRC code such as a CRC-32 field. In software processing, the CRC operation in which the amount of processing is large and which invited the decline in system performance can be provided at hardware of a communication data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CR for detecting CRC errors by separating information data from communication data in which information data including a CRC code is separated and multiplexed.
Related to C error detection technology, for example, digital satellite broadcasting I
RD (Integrated Receiver Dec)
The present invention relates to a technology that is effective when applied to a communication data processing LSI or the like for order.

[0002]

2. Description of the Related Art The main functions required for a communication data processing LSI for digital satellite broadcasting IRD are ISO / IEC.
Multiplexed TS (Transport Street) based on the 13818-1 standard (MPEG2 system standard)
am: transport stream)
PEG2 Video / Audio PES (Pack
Etched Elementary Stream) and PSI (Program Specific Info)
rmation) is to be filtered (separated). In particular, the PSI contains computerized value-added data such as EPG (electronic program information), which is stored in the CPU.
(In this specification, a CPU is a microprocessor,
By passing the data to a data processor including a central processing unit such as a data processor or a microcomputer, information other than image and sound is displayed on a screen. The PSI has a 4-byte (32-bit) CRC code added to the CRC_32 field at the end of the PSI.
By performing the calculation, the presence or absence of a communication error can be detected.

[0003] The CRC operation can be performed by software processing of the CPU. However, since the amount of processing is large, the ratio of the CPU to the resources of the CPU that controls the entire IRD system is high, and the performance of the entire system is degraded.

[0004] In addition, CR in the transport stream
As an example of a document describing the C error detection, an international application (PCT / JP96 / 027) according to International Publication No. WO98 / 12843 (International Publication on March 26, 1998).
21).

[0005]

Therefore, the present inventor has studied a technique that allows a communication error to be detected without imposing a load on a CPU by processing the CRC operation by the communication data processing LSI. In particular, the inconvenience when the CRC code straddles two or more TSs was examined. That is, data that has a meaning in the data content itself is defined as information data, and data that is formatted as a means of communication rather than data content is defined as communication data, and each format is defined as an information data format and a communication data format. By definition, generally, the format of communication data is often fixed length because of the purpose of communication, and conversely, the format of information data is often variable length because the data amount becomes uneven. As illustrated in FIG. 8, PSI corresponds to information data for converting program information and the like into data, and TS has a format for communication with a satellite and corresponds to communication data. TS is 1
The transfer packet data has a fixed length of 88 bytes. PS
I is variable length data of a maximum of 4096 bytes. For example, a PSI is divided into TSs, and the beginning of the TS has header information including a PID (Packetized ID) which is an identifier of the PSI. The PSI TS arranged by a certain PID is multiplexed together with the PSI TS arranged by another PID, and therefore has a discontinuous configuration in the sense that the adjacent TS has a different PID. Therefore, in the process of separation, the original PSI can be taken out by constructing the PSI with the same PID as opposed to multiplexing. Note that P
ES (Video PES / Audio PES) corresponds to information data for converting video data / audio data into data, and the multiplexing / demultiplexing process is the same as that of PSI. The separation of the PSI by the communication data processing LSI is performed by using a target PID or an identifier in the PSI (for example, tabl
e_id) The TS is separated, and the TS is transferred to the externally connected CPU by an interrupt in units of TS. CPU
When the transfer request interrupt is received from the communication data processing LSI, the TS is managed and stored for each identifier PID in the temporary buffer mapped to the DRAM. For storage, the PSI described above is constructed on the DRAM, and necessary information is extracted from the PSI. PSI C
When the CRC calculation for detecting an RC error is performed by the CPU after the PSI is constructed on the DRAM, the amount of processing by the software is large, and the resources of the CPU that controls the entire IRD system are heavily used. As a result, the performance of the entire system is reduced.

[0006] Suppose that the construction of PSI is based on the communication data processing L
Considering realization by SI, as shown in FIG. 9A, it is not realistic because a large memory is required to reconstruct PSI internally. Therefore, FIG.
As shown in (b), the external communication data processing LSI dedicated memory must be prepared as an external component such as a DRAM. Along with this, DRAM
It is considered that a terminal for access is required for the communication data processing LSI. The communication data processing LSI includes:
Equipped with various peripheral circuits required for IRD,
It is responsible for reducing the number of parts in the entire system.
Increasing the number of DRAM access terminals reduces the number of peripheral circuits having terminals, and the peripheral circuits deleted from the communication data processing LSI must be separately prepared as external components, resulting in an increase in the number of components. Further, it is possible to increase the number of packages so as to increase the number of terminals of the communication data processing LSI, but the cost increases.

[0007] Considering that a method of performing a CRC operation in the minimum word length unit of communication is realized by hardware of the communication data processing LSI, the minimum word length of communication in IRD is equivalent to 1 byte. In the CRC calculation at that time, as illustrated in FIG. 10, first, an initial value (for example, all byte logical value “1”) is substituted for the CRC remainder (the CRC remainder at this time is set to 0th.
The CRC remainder of the first word is calculated from the PSI of the first word and the CRC remainder of n bytes of the 0th word. The CRC remainder of the second word is calculated from the PSI of the second word and the CRC remainder of n bytes of the first word. In the following, n of the xth word
Calculating the CRC remainder of the byte from the PSI of the x-th word and the CRC remainder of the n-th byte of the (x-1) th word, and calculating up to the word length m of the PSI, the CRC remainder of the n-th byte of the m-th word becomes ,
It becomes 0 when there is no CRC error. If there is a CRC error, the m-th word n-byte CRC remainder becomes a value other than 0. FIG. 13 shows the case where there is no CRC error.
As an example of the remainder, a range from the CRC remainder of n bytes up to the (m−n + 1) th word of the PSI to the CRC remainder of n bytes up to the mth word of the PSI is shown. The value of # is determined according to the PSI. As is clear from FIG. 13, when there is no CRC error, the CRC remainder up to the m-th word of the PSI is a logical value “0” from the n-th word to the first word, and
The CRC remainder up to the -1 word is a logical value "0" from the nth word to the second word, and the CRC remainder up to the m-2th word of the PSI is a logical value "0" from the nth word to the third word. Yes, PSI m-th
As for the CRC remainder up to −n + 1 words, only the nth word has a logical value “0”. The calculation of the CRC remainder in each word is performed by modulo calculation using a generator polynomial defined in the ISO / IEC 13818-1 standard. Since sequential processing is possible as described above, it is easy to realize the CRC operation of each word by hardware, for example, by synchronizing it with a clock.

In order to notify the CPU of the presence or absence of a CRC error, a method of providing a register for indicating the presence or absence of a CRC error or a method of substituting a CRC operation result in the CRC_32 field can be considered. In the former method, taking into account the case where the word length of the PSI is shorter than the TS, registers as many as the number of CRC_32 fields that can exist in one TS as shown in FIG. Become. In addition, instead of the CPU, a bus master such as a DMA transfers the TS from the communication data processing LSI to the CPU.
When the load on the CPU is reduced by entrusting the transfer of the data, the previous register cannot be stored by the DMA alone,
The intervention of U is required, and the load due to the use of DMA cannot be reduced.

The latter method is effective because it does not have the problems of the former method and has a high degree of freedom as software.
When the CRC_32 field is divided into two or more TSs and straddles it, the CRC operation result cannot be correctly reflected on a part other than the last word of the CRC remainder. That is, as illustrated in FIG. 12, when the TSi includes the CRC code of the n words of the information data, the CRC remainder from the mth word of the PSI to the mth word of the PSI is the same from the first word to the nth word. Substituted for CRC code. On the other hand, in FIG.
A part of the code is included in TSm, and the remaining CRC code is
When Sm + 1 is included, in the process for TSm,
The first and second words of the CRC remainder up to the m-2th word are TS
is assigned to the CRC code on m. At this stage, the first and second words of the CRC remainder up to the m-2th word substituted above are
The word is not logical "0". And TSm + 1
, The CRC residue up to the m-th word is n-1
The word and the nth word are substituted for the CRC code on TSm + 1. As described above, if the CRC_32 field is divided into two or more TSs and crosses over it, even if there is no CRC error, CRC_3 existing over two or more TSs is used.
The value assigned to the two fields is not finally set to the all-word logical value "0". Since the CPU determines the presence or absence of a CRC error based on the entire contents of the n-word CRC_32 field, a determination error may occur.

As described above, in the IRD, if the CRC calculation of the PSI multiplexed in the TS is performed by the software processing of the CPU, the processing amount is large and the performance of the entire system is reduced. Therefore, the CRC operation is
I want to notify the CPU of the presence or absence of a CRC error by substituting the CRC operation result in the CRC_32 field for each TS before I construction. However, when the CRC_32 field is divided into two or more TSs and straddles, a correct CRC operation result cannot be assigned to the CRC_32 field other than the last byte (the fourth byte), so that the CPU cannot be correctly notified of the presence or absence of a CRC error. The problem was revealed by the present inventors.

An object of the present invention is to provide a communication data processing apparatus capable of reducing a load on a CPU required for a CRC error determination process.
Another object of the present invention is to provide a data receiving system.

Another object of the present invention is to reflect the CRC remainder of the PSI in the CRC code and notify the CPU of the presence or absence of the CRC error. Even when the CRC code is divided into a plurality of parts by the TS, the CRC error can be reduced. An object of the present invention is to provide a communication data processing device and a data receiving system that can correctly notify the presence or absence.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the communication data processing device performs a CRC of word length n (n> 1) added for detecting a communication error.
A communication data (TS) having a predetermined word length obtained by dividing and multiplexing information data (PSI) having a word length m including a code is input, and the information data is separated from the input communication data. The CRC remainder for CRC error detection is sequentially calculated, and the CRC remainder (CRC_CRC_
(32 fields) is substituted for the CRC code, and the information data is output to the outside. The communication data processing device includes a CRC operation circuit (42) for substituting a value obtained by encoding the first word to the n-th word of the CRC remainder of the entire information data to a word length of 1 by a logical sum into the n-th word of the CRC code. And the presence or absence of a CRC error can be determined based on the logical value of the nth word of the CRC code. The contents of the processing by the CRC operation circuit are illustrated in FIG.

As described above, the presence or absence of a CRC error is
By substituting a CRC code such as _32 field into the CRC code, it is possible to notify the CPU (7). In the software processing, the CRC calculation, which has a large processing amount and causes a decrease in system performance, is performed by the hardware of the communication data processing device. Can be realized.

Further, the CRC operation of the information data (PSI) is performed by hardware processing in a communication data processing device,
The assignment of the CRC remainder to the CRC code in the communication data (TS) targets only the end of the CRC code, and the CPU or the microprocessor can check only the end of the CRC code to determine a CRC error. According to the CRC calculation method studied by the present inventors prior to the present invention, the final CRC remainder is obtained only by the calculation including the CRC code located at the end of the data to be calculated. , If the CRC code of the PSI is divided into a plurality of pieces by multiplexing to the TS,
The C code cannot reflect the correct CRC remainder. Although the correct remainder can be reflected at least in the last word of the CRC code, the presence or absence of a CRC error can be determined from the entire word length of the CRC code.
Error cannot be determined correctly. On the other hand, according to the present invention, in the method in which the CRC remainder of the PSI is reflected in the CRC code and the presence or absence of the CRC error is notified to the CPU, even if the CRC code is divided into a plurality of parts by the TS, the CRC error is not detected. The presence or absence can be correctly notified. Therefore, the CRC error can be notified to the CPU without depending on the position of the CRC code in the TS, the CRC operation can be processed by hardware other than the CPU, and the software processing of the CPU can be reduced.

In another mode of the CRC operation circuit (42),
The CRC remainder up to the mn-th word of the information data and the value obtained by exclusive ORing each one word from the first word to the n-th word of the CRC code, respectively, are the first to n-th words of the CRC code. And a CRC operation circuit for substituting the CRC error into a CRC code. FIG. 2 illustrates the contents of the processing by the CRC operation circuit. The contents of FIG.
It can be understood by referring to the state of the CRC remainder when there is no error.

In still another mode of the CRC operation circuit (42), the CRC operation circuit converts the xth word of the CRC code into the (n + 1-x) th CRC remainder up to the (m−n + x) th word of the information data.
Substitute words. More specifically, the CRC operation circuit comprises:
From the first word to the n-th word of the CRC code, the first word is the n-th word of the CRC remainder up to the (m−n + 1) th word of the information data, and the second word is the m−n + 2th word of the information data. CR
Similarly, the first word of the CRC remainder up to the m-th word of the information data is substituted for the (n−1) th word of the C remainder, and similarly to the n-th word. C
The PU or microprocessor is the first of the CRC codes
The presence or absence of a CRC error is determined based on whether or not all the n-th words from the word are 0. The contents of the processing by the CRC operation circuit are illustrated in FIG. The contents of FIG. 3 can be understood by referring to the state of the CRC remainder when there is no error in FIG.

[0020]

FIG. 4 is a block diagram showing an example of an IRD. IRD1 is compatible with PerformecTV and Di
The receiver receives digital satellite waves of a digital satellite broadcast service represented by recTV and outputs a video signal to a receiver such as a TV2. In the IRD 1, the digital satellite wave received by the antenna 3 is transmitted to the tuner module 4
The tuner module 4 performs switching of the receiving transponder, demodulation, and error correction, and
A TS conforming to the / IEC 13818-1 standard is output. A plurality of programs are multiplexed in the TS, and are identified by a PID (Packetized ID) of a header portion in the TS. The TS is input to the communication data processing LSI 5 and separated into a PSI (program specification information), video data, and audio data. Communication data processing LSI5
Performs a CRC operation on the PSI and substitutes the CRC remainder for the PSI CRC code. The PSI reconstructed in this way is temporarily stored in the DRAM 6 and
Determines the CRC error based on the PSI CRC code. The CPU 7 causes the TV 2 to display an error-free PSI via the playback unit 8. Video data and audio data separated by the communication data processing LSI 5 are MPEG
The data is composited by the two decoders 9 and sent to the TV 2 via the reproducing unit 8. The IRD 1 has an IC card interface and a modem interface 10 as other external interface circuits. Also, the communication data processing LSI 5
Interfaced with the personal computer 11 and the digital video tape recorder 12, it is also possible to exchange video data and audio data.

FIG. 5 is a block diagram showing an example of the communication data processing LSI 5. As a configuration related to TS flow,
A MULTI2 descrambler 20 for decrypting a TS encrypted based on the MULTI2 system, necessary video data and audio data (MPEG2 Video PES and AudioPE) from PSI based on a channel selection operation of a viewer.
S), a DEMUX filter 21 for separating the data, and an M for outputting the separated data to an externally connected MPEG2 decoder.
It has a PEG2 decoder I / F22. In addition, the LSI
5 also includes peripheral I / Fs necessary for various IRD controls. The peripheral I / F includes an SCI / SMC (serial interface / smart card interface) 2 for transmitting and receiving data to and from an IC card or a modem.
3. I for controlling the tuner module and the playback unit
/ F as an IIC serial interface 24, an FRT (free running timer) 25 for generating various time timings, an optical digital output converter 26 for performing optical digital output, and a general-purpose I / O for controlling other LSIs and the like.
O port 27 and IN for interrupt control of IRD
There is a T (interrupt controller) 28. The data separated into video data and audio data by the same LSI 5 is MPE
The video data and audio data before compression are expanded by the G2 decoder 9 respectively. Each signal is Vid
It is converted into a video signal and an audio signal by an eo encoder and a DA converter, and reproduced by a receiver such as a TV2. All of the LSIs mounted on these IRDs are
It is controlled by a CPU (central processing unit) 7. In FIG. 5, reference numeral 29 denotes a CPU interface. The clock recovery 30 controls the voltage controlled oscillation circuit (VCXO) 31 to detect a clock from a PCR (Program Clock Reference) in the TS.
Regenerate a 7 MHz clock.

As a feature of the IRD 1, there is a service of various functions using EPG (electronic program information). For example, there is a function of selecting a channel from hundreds or more multi-channels on a TV screen, a function of providing program column information, and the like. EPG is P
An identifier in the SI, which is in the PSI, eg, t
Identified by an able_id field, etc.
Separated by MUX LSI. A 32-bit CRC code is added to the CRC_32 field at the end of the PSI. By performing error detection using this CRC code, a transmission error can be detected and removed.

As described above, PSI corresponds to information data for converting program information and the like into data, and TS corresponds to communication data in a format for communication with a satellite. TS is 1
The PSI has a fixed length of 88 bytes, and the PSI has a variable length of up to 4096 bytes. In the process of multiplexing the PSI into the TS, the PSI is divided into TS format word lengths and the same P
Identified by ID. Therefore, the TS of the PSI arranged by a certain PID is multiplexed with the TS of the PSI arranged by another PID, so that the adjacent TS is discontinuous. Therefore, in the process of separation by the communication data processing LSI 5, the same PID is used for the PS
By constructing I, the original PSI can be extracted.

FIG. 6 shows a CRC operation circuit (CRCKHK).
A block diagram of the DEMUX filter 21 including 42 is shown.

The TS descrambled by the MULTI2 descrambler 20 is input from the TS input to the TS buffer 40, and the hit detection circuit 41 performs filtering based on PID and PSI identifiers. The filtering result TS is transferred to the internal TS bus and
I is transmitted to the CRC operation circuit 42, and video data and audio data are transmitted to the AVPU (Audio / Video Passth).
(Rout Unit) 43. The CRC operation circuit 42 and the AVPU 43 are respectively connected to the CPU 7, MP
It has a FIFO buffer for buffering data transfer with the EG2 decoder 9 and is called a read FIFO buffer 44 and a write FIFO buffer 45, respectively. CRC
The arithmetic circuit 42 calculates the CRC of the PSI in the TS of the internal TS bus.
The operation is performed, and the operation result is assigned to the CRC_32 field and transferred to the read FIFO buffer 44. Lead FI
The FO buffer 44 generates an interrupt RDINT to the CPU 7 when the TS is arbitrarily stored in the FIFO, and the CPU 7 receives the interrupt RDINT and reads the buffer.
4 to transfer the filtered TS to the DRAM 6. The AVPU 43 extracts the PES in the TS and transfers it to the write FIFO buffer 45. The data in the write FIFO buffer 45 is transferred to the MPEG2 I / F 46 and transferred to the external MPEG2 decoder 9. Also,
The DEMUX filter 21 sends the IRD clock to the PCR (Program_Clock_Referen) in the TS.
PCR that reproduces 27 MHz by synchronizing with ce)
A recovery 47 is provided. In addition, the DEMUX filter 2
1 further includes a bus interface 48, a table RAM 49 in which reference information for detection by the hit detection circuit 41 is set, and a buffer mode register 50. WRITE is a write FIFO buffer interrupt request signal, and PCRINT is a clock recovery interrupt request signal.

FIG. 7 shows an example of the CRC operation circuit 42. The CRC operation circuit 42 receives the TS from the internal TS bus.
From the TS input, and is branched and input to the TS delay circuit 60 and the CRC operation unit 61. An independent CRC operation unit 61 is provided for each of the 27 PIDs, which is the maximum number that can be filtered by the hit detection circuit 41, so that independent CRC remainders can be calculated and stored. The TS from the TS input is the CRC of the corresponding PID among the 27 CRC operation units 61.
The arithmetic unit 61 is selected and input to the
An operation is performed. The operation enable register (CRCEN0 / 1) 62 instructing CRC operation enable / disable controls the 27 CRC operation units 61 independently of execution / non-execution of the CRC operation result. The CRC_32 control circuit 63 performs control to substitute the CRC remainder calculated by the CRC calculation unit 61 into the CRC_32 field. The operation mode is specified by the mode register 64. The mode of the substitution designated by the mode register is any of the modes shown in FIGS. The TS delay circuit 60 uses the CRC_32 control circuit 63
In order to take the timing of substitution into 32 fields, the TS output which is output to the read FIFO buffer 44 is delayed.

For example, when the operation mode shown in FIG. 1 is specified, if the last byte of the CRC_32 field exists in the TS delay circuit 60 as a result of the CRC operation,
The value obtained by ORing the 4 bytes of the CRC remainder into one byte by the —32 control circuit 63 is assigned to the corresponding portion in the TS delay circuit 60. As described above, the presence or absence of a CRC error is
By substituting into a CRC code such as the C_32 field, notification to the CPU 7 becomes possible, and in the software processing, the CRC calculation, which has a large processing amount and causes a decrease in system performance, is realized by the hardware of the communication data processing LSI 5. Can be.

The CRC operation of the information data PSI is performed by hardware processing in the communication data processing LSI 5,
Substitution of the CRC remainder into the CRC code in the communication data TS targets only the end of the CRC code, and the CPU 7 can check only the end of the CRC code to determine a CRC error. C
The correct remainder can be reflected in the last word of the RC code, and it is not necessary to determine the presence or absence of a CRC error from the entire word length of the CRC code. Therefore, the presence or absence of a CRC error can be correctly determined only from the last word. Therefore, regardless of the position in the TS where the CRC code is located, in other words, even if the CRC code is divided across a plurality of TSs, the CRC error is detected by the C code.
The PU 7 can be notified, and the CRC operation can be processed by hardware in the communication data processing LSI 5, so that IRD software processing can be reduced.

When the operation mode shown in FIG. 2 is set in the CRC mode register 64, the CRC remainder up to the mn-th word of the information data and the first word to the n-th word of the CRC code are respectively sequentially. A value obtained by encoding each word by exclusive OR is substituted from the first word to the n-th word of the CRC code,
The presence or absence of a CRC error can be determined based on whether or not all the first to n-th words of the CRC code are 0. With this, the same effect as in the case of FIG. 1 can be obtained. FIG.
Can be easily understood by referring to the state of the CRC remainder when there is no error in FIG.

When the operation mode shown in FIG. 3 is set in the CRC mode register 64, the first word of the CRC code is changed to the nth word, and the first word is respectively the (m−n + 1) th word of the information data. The second word is the nth word of the CRC remainder, and the second word is the nth word of the CRC remainder up to the (mn) + 2th word of the information data.
Similarly, the first word of the CRC remainder up to the m-th word of the information data is substituted for the n-th word. The CPU 7 has a CR
The presence or absence of a CRC error is determined based on whether the first to n-th words of the C code are all 0s. Fig. 1
The same effect as in the case of can be obtained. The contents of FIG.
It can be easily understood by referring to the state of the CRC remainder when there is no error in FIG.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No. For example, the data compression format of video and audio is not limited to MPEG2. Further, the present invention is not limited to the communication data processing LSI for digital satellite broadcasting IRD,
(Cable Television) and VOD (V
For example, the present invention can be applied to an application for transmitting and receiving digital data over a communication line, such as “video on demand”. In addition, the present invention can be widely applied to a CRC error check technique in which the CRC remainder of the entire information data is reflected in a CRC code in order to determine the presence or absence of a CRC error in the information data.

[0032]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the load on the CPU required for the CRC error determination processing can be reduced. Also, when notifying the CPU of the presence or absence of a CRC error by reflecting the CRC remainder of the PSI in the CRC code, the presence or absence of the CRC error can be correctly reported even when the CRC code is divided into a plurality of pieces by the TS. In other words, the CRC error can be notified to the CPU or the like without depending on the position of the CRC code in the communication data.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating an example of a first CRC calculation method for reflecting a CRC remainder of entire information data in a CRC code.

FIG. 2 is an explanatory diagram showing an example of a second CRC calculation method for reflecting a CRC remainder of the entire information data in a CRC code.

FIG. 3 is an explanatory diagram showing an example of a third CRC calculation method for reflecting a CRC remainder of the entire information data in a CRC code.

FIG. 4 is a block diagram illustrating an example of an IRD.

FIG. 5 is a block diagram illustrating an example of a communication data processing LSI.

FIG. 6 is a block diagram illustrating an example of a DEMUX filter including a CRC operation circuit.

FIG. 7 is a block diagram illustrating an example of a CRC operation circuit.

FIG. 8 is an explanatory diagram showing an example of a relationship between information data such as PSI and communication data such as TS.

FIG. 9 is an explanatory diagram schematically showing a problem studied by the inventor when considering that PSI is realized by a communication data processing LSI.

FIG. 10 is an explanatory diagram schematically showing a CRC remainder calculation method.

FIG. 11 is an explanatory diagram schematically showing a problem studied by the present inventor when a register for notifying the presence or absence of a CRC error is provided.

FIG. 12 is an explanatory diagram schematically showing the contents examined by the present inventor regarding the fact that the CRC code cannot be correctly reflected other than the last word of the CRC remainder when the CRC code is divided into two or more TSs and straddles it. is there.

FIG. 13 shows an example of a CRC residue when there is no CRC error, from an n-byte CRC residue up to the (m−n + 1) th word of the PSI to an n-byte C residue up to the mth word of the PSI.
It is explanatory drawing which shows RC remainder.

[Explanation of symbols]

 1 IRD 5 Communication data processing LSI 21 DEMUX filter 42 CRC operation circuit 44 Read FIFO buffer 60 TS delay circuit 61 CRC operation unit 63 CRC_32 field control circuit 64 CRC mode register

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B001 AA04 AB01 AC01 AD06 AE02 5J065 AA01 AB01 AC02 AD04 AE00 AE06 AH04 5K014 AA01 BA06 EA01

Claims (6)

[Claims] 1. Inputting communication data of a predetermined word length obtained by dividing and multiplexing information data of a word length m including a CRC code of a word length n (n> 1) added for detecting a communication error, The information data is separated from the separated communication data, the CRC remainder for CRC error detection is sequentially calculated for the separated information data, and the CRC remainder of the entire information data is calculated by the CRC.
What is claimed is: 1. A communication data processing apparatus for outputting information data to the outside by substituting into a code, a value obtained by encoding a first word to a n-th word of a CRC remainder of the entire information data to a word length of 1 by a logical sum, and A communication data processing device, comprising: a CRC operation circuit for substituting into a n-th word, wherein it is possible to determine the presence or absence of a CRC error based on a logical value of the n-th word of a CRC code. 2. Inputting communication data of a predetermined word length obtained by dividing and multiplexing information data of a word length m including a CRC code of a word length n (n> 1) added for detecting a communication error, and The information data is separated from the separated communication data, the CRC remainder for CRC error detection is sequentially calculated for the separated information data, and the CRC remainder of the entire information data is calculated by the CRC.
What is claimed is: 1. A communication data processing apparatus for outputting information data to a code by substituting into a code, a CRC remainder up to the mn-th word of the information data and a word from the first word to the n-th word of the CRC code. A CRC operation circuit for substituting the value coded by the exclusive OR into the first word to the n-th word of the CRC code, and determining whether the first word to the n-th word of the CRC code are all 0 or not. A communication data processing device capable of determining the presence or absence of an error. 3. Inputting communication data of a predetermined word length obtained by dividing and multiplexing information data of a word length m including a CRC code of a word length n (n> 1) added for detecting a communication error, The information data is separated from the separated communication data, the CRC remainder for CRC error detection is sequentially calculated for the separated information data, and the CRC remainder of the entire information data is calculated by the CRC.
A communication data processing apparatus for outputting information data to the outside by substituting into a code, a CRC substituting the (n + 1-x) th word of a CRC remainder up to the (m−n + x) th word of the information data into the xth word of the CRC code A communication data processing device comprising an arithmetic circuit and capable of determining the presence or absence of a CRC error based on whether all of the first to n-th words of the CRC code are 0. 4. The CRC arithmetic circuit according to claim 1, wherein the first word is a CRC code from the first word to the n-th word of the CRC code, and the first word is an n-th word of the CRC remainder from the (m−n + 1) th word of the information data to the second word. Is the n-th part of the CRC remainder up to the (mn) -th word of the information data.
4. The communication data processing device according to claim 3, wherein the first word of the CRC remainder up to the m-th word of the information data is substituted into the n-th word for one word. 5. The communication data has header information at the beginning, the header information includes an identifier of the information data, and the CRC operation circuit performs the CRC remainder for each data information relating to the communication data having the same identifier. 5. The method according to claim 1, wherein the calculation is performed and substitution into a CRC code is performed.
The communication data processing device according to any one of the above. 6. A communication data processing device according to claim 5, further comprising: a processor that fetches data information from the communication data processing device and determines whether there is a CRC error from a CRC code included in the data information. A data receiving system, characterized in that: