JP2000124066A - Microchip capacitor and method of mounting thereof - Google Patents
Microchip capacitor and method of mounting thereofInfo
- Publication number
- JP2000124066A JP2000124066A JP10290794A JP29079498A JP2000124066A JP 2000124066 A JP2000124066 A JP 2000124066A JP 10290794 A JP10290794 A JP 10290794A JP 29079498 A JP29079498 A JP 29079498A JP 2000124066 A JP2000124066 A JP 2000124066A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- microchip
- array
- microchip capacitor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、マイクロチップ
コンデンサ、特に複数の電源端子を有する集積回路等に
用いられる、複数のコンデンサをアレイ状に配置したマ
イクロチップコンデンサ及びその実装方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microchip capacitor, particularly to a microchip capacitor used for an integrated circuit having a plurality of power supply terminals, in which a plurality of capacitors are arranged in an array, and a method of mounting the same.
【０００２】[0002]
【従来の技術】文献名 Compex社、「Microwave Chip C
apacitor」カタログ、p.10 従来、アレイ状のマイクロチップコンデンサには、上記
カタログに示されるものがあった。以下、その構成を図
に従って説明する。例として、３つのコンデンサがアレ
イ状に配置されたマイクロチップコンデンサについて示
す。2. Description of the Related Art Document name Compex, Microwave Chip C
apacitor "catalog, p.10 Conventionally, there is an array-shaped microchip capacitor shown in the above catalog. Hereinafter, the configuration will be described with reference to the drawings. As an example, a microchip capacitor in which three capacitors are arranged in an array will be described.
【０００３】図１９は、従来のアレイ状マイクロチップ
コンデンサの構成を示す図である。セラミック等の誘電
体１１の上面に上部電極２１、２２及び２３が形成され
ており、１１の裏面には全面に下部電極３１が形成され
ており、２１−３１間、２２−３１間及び２３−３１間
でそれぞれ１１を誘電体とするコンデンサを構成してい
る。FIG. 19 is a diagram showing the configuration of a conventional array-shaped microchip capacitor. Upper electrodes 21, 22 and 23 are formed on the upper surface of a dielectric material 11 such as a ceramic, and a lower electrode 31 is formed on the entire back surface of 11 so as to be between 21-31, 22-31 and 23-31. Capacitors each having 31 as a dielectric are formed between the 31.
【０００４】このようなアレイ状マイクロチップコンデ
ンサは、例えば、複数の電源端子を有する集積回路等の
電源のデカップリングコンデンサとして使用される。[0004] Such an arrayed microchip capacitor is used, for example, as a decoupling capacitor for a power supply of an integrated circuit or the like having a plurality of power supply terminals.
【０００５】[0005]
【発明が解決しようとする課題】図２０に従来のアレイ
状マイクロチップコンデンサの等価回路を示す。２１−
３１間の容量Ｃ２１、２２−３１間の容量Ｃ２２及び２
３−３１間の容量Ｃ２３の他に、上部電極２１、２２及
び２３は、お互いに誘電体１１でつながっているため、
隣り合う上部電極間に容量ＣＰが存在する。これは複数
の電源端子を有する集積回路等の電源のデカップリング
コンデンサとして使用した場合、各々独立した電源端子
間を容量ＣＰで接続したことになり、カップリングによ
り集積回路の動作に悪影響を及ぼすという問題点があっ
た。FIG. 20 shows an equivalent circuit of a conventional array-type microchip capacitor. 21-
The capacitance C21 between C.31 and C22 and C2 between 22-31
In addition to the capacitance C23 between 3-31, the upper electrodes 21, 22, and 23 are connected to each other by the dielectric 11, so that
A capacitor CP exists between adjacent upper electrodes. This means that, when used as a decoupling capacitor for a power supply of an integrated circuit or the like having a plurality of power supply terminals, independent power supply terminals are connected by a capacitor CP, and the coupling adversely affects the operation of the integrated circuit. There was a problem.
【０００６】[0006]
【課題を解決するための手段】本発明では、上記課題を
解決するため、アレイ状マイクロチップコンデンサの隣
り合う上部電極の間に溝を設け、空気により隣り合うコ
ンデンサの容量ＣＰを低減するという手段を用いるもの
である。According to the present invention, in order to solve the above problems, a groove is provided between adjacent upper electrodes of an arrayed microchip capacitor, and the capacitance CP of the adjacent capacitor is reduced by air. Is used.
【０００７】また、本発明の他の手段として、アレイ状
マイクロチップコンデンサの隣り合う上部電極の間に下
部電極と電気的に接続された導電性薄膜、若しくは導電
性のブロックを設けることにより隣り合うコンデンサ間
の容量ＣＰを低減するという手段を用いるものである。Further, as another means of the present invention, a conductive thin film or a conductive block electrically connected to a lower electrode is provided between adjacent upper electrodes of an array-shaped microchip capacitor so as to be adjacent to each other. This uses a means of reducing the capacitance CP between the capacitors.
【０００８】更に、本発明の他の手段として、アレイ状
マイクロチップコンデンサの隣り合う上部電極と、隣り
合う下部電極の、いずれか一方若しくは両方の間の誘電
体に溝を設けて、マイクロチップコンデンサを実装する
ときにその溝部に沿ってコンデンサの誘電体が割れる実
装方法を用いて、各コンデンサを分離させることによ
り、隣り合うコンデンサ間の容量ＣＰを低減させるとい
う手段を用いるものである。Further, as another means of the present invention, a groove is provided in a dielectric between one or both of an adjacent upper electrode and an adjacent lower electrode of an array-shaped microchip capacitor, and Is used to reduce the capacitance CP between adjacent capacitors by separating each capacitor by using a mounting method in which the dielectric of the capacitor is broken along the groove when mounting.
【０００９】[0009]
【発明の実施の形態】以下、図面を参照し、この発明の
各実施例について説明する。なお、図面はこの発明が理
解できる程度に概略的に示してあるにすぎず、従ってこ
の発明を図示例に限定するものではない。Embodiments of the present invention will be described below with reference to the drawings. The drawings are only schematically shown to the extent that the present invention can be understood, and thus the present invention is not limited to the illustrated examples.
【００１０】＜第一の実施例＞図１は、本発明の第一の
実施例のアレイ状マイクロチップコンデンサの構成例を
示す図である。セラミック等の誘電体１１の上面に上部
電極２１、２２及び２３が形成されており、誘電体１１
の裏面には全面に下部電極３１が形成されており、２１
−２２間及び２２−２３間の誘電体１１の上部に溝４１
が形成されている。第１図では溝４１は長方形状で描か
れているが、これは長方形状に限定するものではなく、
Ｖ字形状、台形状、半円形状等でも良い。コンデンサは
２１−３１間、２２−３１間及び２３−３１間でそれぞ
れ１１を誘電体として構成されている。<First Embodiment> FIG. 1 is a diagram showing a configuration example of an array-shaped microchip capacitor according to a first embodiment of the present invention. Upper electrodes 21, 22, and 23 are formed on the upper surface of a dielectric 11 such as a ceramic.
A lower electrode 31 is formed on the entire back surface of
A groove 41 is formed in the upper part of the dielectric material 11 between -22 and 22-23.
Are formed. Although the groove 41 is drawn in a rectangular shape in FIG. 1, this is not limited to the rectangular shape.
It may be V-shaped, trapezoidal, semicircular, or the like. The capacitor is constituted by using 11 as a dielectric between 21-31, between 22-31 and between 23-31.
【００１１】図２は、第一の実施例のアレイ状マイクロ
チップコンデンサの等価回路である。この等価回路は従
来技術のものと同じ構成をしているが、上部電極間の誘
電体部分に溝を設けることにより、隣り合う上部電極間
は空気によって分離されているため、各コンデンサ間の
容量ＣＰは、従来のものより低減できる。FIG. 2 is an equivalent circuit of the array-type microchip capacitor of the first embodiment. This equivalent circuit has the same configuration as that of the prior art, but by providing a groove in the dielectric portion between the upper electrodes, the adjacent upper electrodes are separated by air, so that the capacitance between the capacitors is reduced. CP can be reduced compared to the conventional one.
【００１２】＜第二の実施例＞図３に、本発明の第二の
実施例の、アレイ状マイクロチップコンデンサの構成例
を示す。また、図４に図３に示したアレイ状マイクロチ
ップコンデンサの断面図を示す。セラミック等の誘電体
１１の上面に上部電極２１、２２及び２３が形成されて
おり、２１−２２間及び２２−２３間に上部電極３２が
形成されており、誘電体１１の裏面には全面に下部電極
３１が形成されており、３２と３１はスルーホールによ
り接続されている。スルーホールの構造は特に限定はな
い。スルーホールの内壁に導電性材料を円筒形に被着さ
せたオープンVIA、スルーホールを導電性材料で完全に
埋め込んでしまう埋め込みVIA等どちらでも構わない。
コンデンサは２１−３１間、２２−３１間及び２３−３
１間でそれぞれ１１を誘電体として構成されている。<Second Embodiment> FIG. 3 shows a configuration example of an arrayed microchip capacitor according to a second embodiment of the present invention. FIG. 4 is a cross-sectional view of the arrayed microchip capacitor shown in FIG. Upper electrodes 21, 22, and 23 are formed on the upper surface of a dielectric 11 such as a ceramic, and the upper electrode 32 is formed between 21-22 and 22-23. A lower electrode 31 is formed, and 32 and 31 are connected by a through hole. The structure of the through hole is not particularly limited. Either an open VIA in which a conductive material is applied in a cylindrical shape to the inner wall of the through hole or an embedded VIA in which the through hole is completely embedded with the conductive material may be used.
Capacitors between 21-31, 22-31 and 23-3
Each of the spaces 11 is composed of 11 as a dielectric.
【００１３】図５は、第二及び第三の実施例のアレイ状
マイクロチップコンデンサの等価回路である。上部電極
間に誘電体１１の裏面の下部電極３１と接続された上部
電極３２を設けることにより、隣り合う上部電極間の容
量ＣＰは第５図のように途中で下部電極と接続されるの
で、各コンデンサ間の容量ＣＰは低減される。FIG. 5 is an equivalent circuit of the arrayed microchip capacitors of the second and third embodiments. By providing the upper electrode 32 connected to the lower electrode 31 on the back surface of the dielectric 11 between the upper electrodes, the capacitance CP between the adjacent upper electrodes is connected to the lower electrode in the middle as shown in FIG. The capacitance CP between the capacitors is reduced.
【００１４】＜第三の実施例＞図６に、本発明の第三の
実施例のアレイ状マイクロチップコンデンサの構成例を
示す。また、図７に図６に示したアレイ状マイクロチッ
プコンデンサの断面図を示す。セラミック等の誘電体１
１の上面に上部電極２１、２２及び２３が形成されてお
り、誘電体１１の裏面には全面に下部電極３１が形成さ
れており、２１−２２間及び２２−２３間には下部電極
３１と接続された金属ブロック３４が配置されており、
３４は各々のコンデンサの誘電体１１を完全に分離して
いる。図６では金属ブロックは長方形状のものを示した
が、これは長方形状に限定するものではなく、台形状、
逆台形状等でも良い。コンデンサは２１−３１間、２２
−３１間及び２３−３１間でそれぞれ１１を誘電体とし
て構成されている。<Third Embodiment> FIG. 6 shows a configuration example of an array-shaped microchip capacitor according to a third embodiment of the present invention. FIG. 7 is a sectional view of the arrayed microchip capacitors shown in FIG. Dielectric 1 such as ceramic
1, upper electrodes 21, 22, and 23 are formed on the upper surface, and a lower electrode 31 is formed on the entire back surface of the dielectric 11, and the lower electrode 31 is provided between 21-22 and 22-23. A connected metal block 34 is arranged,
34 completely separates the dielectric 11 of each capacitor. In FIG. 6, the metal block has a rectangular shape. However, the shape is not limited to the rectangular shape.
An inverted trapezoidal shape or the like may be used. Capacitor is between 21-31, 22
11 is used as a dielectric between -31 and 23-31.
【００１５】図５は、第二及び第三の実施例のアレイ状
マイクロチップコンデンサの等価回路である。各々のコ
ンデンサの間に金属ブロック３４を設けることにより、
隣り合う上部電極間の容量ＣＰは図５のように途中で下
部電極と接続されるので、各コンデンサ間の容量ＣＰは
低減される。FIG. 5 is an equivalent circuit diagram of the arrayed microchip capacitors of the second and third embodiments. By providing a metal block 34 between each capacitor,
Since the capacitance CP between the adjacent upper electrodes is connected to the lower electrode in the middle as shown in FIG. 5, the capacitance CP between the capacitors is reduced.
【００１６】＜第四の実施例＞図８に、本発明の第四の
実施例のアレイ状マイクロチップコンデンサの構成例を
示す。セラミック等の誘電体１１の上面に上部電極２
１、２２及び２３が形成されており、誘電体１１の裏面
には２１−２２間及び２２−２３間に凹字型の溝５１が
形成されている。<Fourth Embodiment> FIG. 8 shows a configuration example of an arrayed microchip capacitor according to a fourth embodiment of the present invention. The upper electrode 2 is formed on the upper surface of a dielectric 11 such as a ceramic.
1, 22 and 23 are formed, and a concave groove 51 is formed on the back surface of the dielectric 11 between 21-22 and 22-23.
【００１７】また、誘電体１１の裏面の凹字型の溝５１
以外の部分には下部電極３１が形成されており、２１−
３１間、２２−３１間及び２３−３１間でそれぞれ１１
を誘電体とするコンデンサを構成している。これらの各
コンデンサ間の容量ＣＰを低減させる実装方法を、第五
の実施例として次に説明する。A concave groove 51 on the back surface of the dielectric 11
The lower electrode 31 is formed in a portion other than
11 between 22 and 31 and between 22 and 31 and 23 and 31 respectively
Is a dielectric material. A mounting method for reducing the capacitance CP between these capacitors will be described below as a fifth embodiment.
【００１８】＜第五の実施例＞図９は、本発明の第五の
実施例のアレイ状マイクロチップコンデンサの実装図で
ある。マイクロチップコンデンサ配置部が金メッキ等に
よりメタライズされ、基板６１に、本発明の第四の実施
例のアレイ状マイクロチップコンデンサをＡｕＳｎ等の
ハンダを使って付ける。ここで、基板６１を、誘電体１
１と熱膨張率の異なる物質とする。基板６１全体を加熱
し、マイクロチップコンデンサ配置部にハンダを溶か
し、その上にマイクロチップコンデンサをのせる。この
後、基板６１を冷却すると、基板６１と誘電体１１の熱
膨張率の違いにより、マイクロチップコンデンサは、誘
電体１１の凹溝の部分で割れ、図９のように各々個別の
マイクロチップコンデンサに切り離される。<Fifth Embodiment> FIG. 9 is a mounting diagram of an arrayed microchip capacitor according to a fifth embodiment of the present invention. The microchip capacitor arrangement portion is metallized by gold plating or the like, and the array-like microchip capacitors according to the fourth embodiment of the present invention are attached to the substrate 61 using solder such as AuSn. Here, the substrate 61 is
1 and a material having a different coefficient of thermal expansion. The entire substrate 61 is heated, the solder is melted in the microchip capacitor arrangement portion, and the microchip capacitor is placed thereon. Thereafter, when the substrate 61 is cooled, the microchip capacitors break at the concave grooves of the dielectric 11 due to the difference in the coefficient of thermal expansion between the substrate 61 and the dielectric 11, and as shown in FIG. Be cut off.
【００１９】図１０は、第五乃至第九の実施例のアレイ
状マイクロチップコンデンサを本実施例に基づいて実装
した後の等価回路図である。FIG. 10 is an equivalent circuit diagram after the array-type microchip capacitors of the fifth to ninth embodiments are mounted based on this embodiment.
【００２０】各々のコンデンサは上記に示したように完
全に切り放されるので、隣り合うコンデンサ間の容量Ｃ
Ｐはほとんど無くなる。Since each capacitor is completely cut off as shown above, the capacitance C between adjacent capacitors is
P almost disappears.
【００２１】＜第六の実施例＞図１１に、本発明の第六
の実施例のアレイ状マイクロチップコンデンサの構成例
を示す。セラミック等の誘電体１１の上面に上部電極２
１、２２及び２３が形成されており、２１−２２間及び
２２−２３間に凹字型の溝５２が形成されており、誘電
体１１の裏面には２１−２２間及び２２−２３間に相当
する部分に凹字型の溝５１が形成されている。また、誘
電体１１の裏面の凹字型の溝５１以外の部分には下部電
極３１が形成されており、２１−３１間、２２−３１間
及び２３−３１間でそれぞれ１１を誘電体とするコンデ
ンサを構成している。<Sixth Embodiment> FIG. 11 shows a configuration example of an array-shaped microchip capacitor according to a sixth embodiment of the present invention. The upper electrode 2 is formed on the upper surface of a dielectric 11 such as a ceramic.
1, 22 and 23 are formed, and a concave groove 52 is formed between 21-22 and 22-23, and on the back surface of the dielectric 11, between 21-22 and 22-23. A concave groove 51 is formed in a corresponding portion. A lower electrode 31 is formed in a portion other than the concave groove 51 on the back surface of the dielectric 11, and 11 is a dielectric between 21-31, 22-31 and 23-31. Constructs a capacitor.
【００２２】図１２に、本発明の第五の実施例を用いた
アレイ状マイクロチップコンデンサの実装図を示す。第
五の実施例に基づいて実装すれば、誘電体１１の上下の
凹溝の部分で割れ、図１２のように、アレイ状マイクロ
チップコンデンサは各々個別のマイクロチップコンデン
サに切り放される。FIG. 12 shows a mounting diagram of an array-shaped microchip capacitor using the fifth embodiment of the present invention. If the mounting is performed based on the fifth embodiment, the microchip capacitors are broken at the upper and lower concave portions of the dielectric 11, and the arrayed microchip capacitors are cut off into individual microchip capacitors as shown in FIG.
【００２３】図１０は、第五乃至第九の実施例のアレイ
状マイクロチップコンデンサの実装後の等価回路であ
る。各々のコンデンサは上記に示したように完全に切り
放されるので、隣り合うコンデンサ間の容量はほとんど
無くなる。FIG. 10 is an equivalent circuit after mounting the arrayed microchip capacitors of the fifth to ninth embodiments. Since each capacitor is completely disconnected as shown above, there is little capacity between adjacent capacitors.
【００２４】＜第七の実施例＞図１３に、本発明の第七
の実施例のアレイ状マイクロチップコンデンサの構成例
を示す。セラミック等の誘電体１１の上面に上部電極２
１、２２及び２３が形成されており、２１−２２間及び
２２−２３間の中間付近に幅の狭い凹字型の溝５２が形
成されている。この幅の狭い凹字型の溝５２は、ダイシ
ング等の技術により簡単に作成できる。また、誘電体１
１の裏面には２１−２２間及び２２−２３間に相当する
部分に凹字型の溝５１が形成されており、誘電体１１の
裏面の凹字型の溝５１以外の部分には下部電極３１が形
成されている。２１−３１間、２２−３１間及び２３−
３１間でそれぞれ１１を誘電体とするコンデンサを構成
している。<Seventh Embodiment> FIG. 13 shows a configuration example of an arrayed microchip capacitor according to a seventh embodiment of the present invention. The upper electrode 2 is formed on the upper surface of a dielectric 11 such as a ceramic.
1, 22 and 23 are formed, and a narrow concave groove 52 is formed near the middle between 21-22 and 22-23. The narrow concave groove 52 can be easily formed by a technique such as dicing. In addition, dielectric 1
A concave groove 51 is formed in a portion corresponding to between 21 and 22 and between 22 and 23 on the back surface of the lower electrode 1, and a lower electrode is formed in a portion other than the concave groove 51 on the back surface of the dielectric 11. 31 are formed. 21-31, 22-31 and 23-
Capacitors each having 31 as a dielectric are formed between the 31.
【００２５】図１４に、本発明の第五の実施例を用いた
アレイ状マイクロチップコンデンサの実装図を示す。マ
イクロチップコンデンサは、誘電体１１の凹溝の部分で
割れ、図１４のように、各々個別のマイクロチップコン
デンサに切り放される。このとき、各コンデンサは幅の
狭い凹字型の溝５２の部分が割れて分離されるため、溝
５２の位置により、割れる部分を特定することができ
る。FIG. 14 shows a mounting diagram of an array-shaped microchip capacitor using the fifth embodiment of the present invention. The microchip capacitor breaks at the concave groove portion of the dielectric 11 and is cut off into individual microchip capacitors as shown in FIG. At this time, since the portions of the narrow concave grooves 52 of each capacitor are broken and separated, the split portions can be specified by the positions of the grooves 52.
【００２６】図１０は、第五乃至第九の実施例のアレイ
状マイクロチップコンデンサの実装後の等価回路であ
る。各々のコンデンサは上記に示したように完全に切り
放されるので、隣り合うコンデンサ間の容量はほとんど
無くなる。FIG. 10 is an equivalent circuit of the fifth through ninth embodiments after mounting the arrayed microchip capacitors. Since each capacitor is completely disconnected as shown above, there is little capacity between adjacent capacitors.
【００２７】＜第八の実施例＞図１５に、本発明の第八
の実施例のアレイ状マイクロチップコンデンサの構成例
を示す。セラミック等の誘電体１１の上面に上部電極２
１、２２及び２３が形成されており、誘電体１１の裏面
には２１−２２間及び２２−２３間に相当する部分の中
間付近にＶ字型の溝５１が形成されている。また、誘電
体１１の裏面のＶ字型の溝５１以外の部分には下部電極
３１が形成されており、２１−３１間、２２−３１間及
び２３−３１間でそれぞれ１１を誘電体とするコンデン
サを構成している。<Eighth Embodiment> FIG. 15 shows an example of the configuration of an array-shaped microchip capacitor according to an eighth embodiment of the present invention. The upper electrode 2 is formed on the upper surface of a dielectric 11 such as ceramic.
1, 22, and 23 are formed, and a V-shaped groove 51 is formed on the back surface of the dielectric 11 near the middle of the portion corresponding to between 21-22 and 22-23. A lower electrode 31 is formed in a portion other than the V-shaped groove 51 on the back surface of the dielectric 11, and 11 is used as a dielectric between 21-31, 22-31 and 23-31. Constructs a capacitor.
【００２８】図１６に、本発明の第五の実施例を用いた
アレイ状マイクロチップコンデンサの実装図を示す。マ
イクロチップコンデンサは、誘電体１１のＶ溝の鋭角部
に応力が集中し、誘電体１１はＶ溝部分で割れ、図１６
のように、各々個別のマイクロチップコンデンサに切り
離される。FIG. 16 shows a mounting diagram of an arrayed microchip capacitor using the fifth embodiment of the present invention. In the microchip capacitor, stress concentrates on the acute angle portion of the V-groove of the dielectric 11, and the dielectric 11 cracks at the V-groove.
And each is separated into individual microchip capacitors.
【００２９】図１０は、第五乃至第九の実施例のアレイ
状マイクロチップコンデンサの実装後の等価回路であ
る。各々のコンデンサは上記に示したように完全に切り
放されるので、隣り合うコンデンサ間の容量はほとんど
無くなる。FIG. 10 is an equivalent circuit after mounting the arrayed microchip capacitors of the fifth to ninth embodiments. Since each capacitor is completely disconnected as shown above, there is little capacity between adjacent capacitors.
【００３０】＜第九の実施例＞図１７に、本発明の第九
の実施例を用いた実装方法を用いたアレイ状マイクロチ
ップコンデンサの構成例を示す。セラミック等の誘電体
１１の上面に上部電極２１、２２及び２３が形成されて
おり、２１−２２間及び２２−２３間の中間付近にＶ字
型の溝５２が形成されており、誘電体１１の裏面には溝
５２の真下にＶ字型の溝５１が形成されている。<Ninth Embodiment> FIG. 17 shows a configuration example of an arrayed microchip capacitor using a mounting method using a ninth embodiment of the present invention. Upper electrodes 21, 22, and 23 are formed on the upper surface of a dielectric 11 such as a ceramic, and a V-shaped groove 52 is formed near the middle between 21-22 and 22-23. A V-shaped groove 51 is formed directly below the groove 52 on the back surface of the substrate.
【００３１】また、誘電体１１の裏面のＶ字型の溝５１
以外の部分には下部電極３１が形成されており、２１−
３１間、２２−３１間及び２３−３１間でそれぞれ１１
を誘電体とするコンデンサを構成している。A V-shaped groove 51 on the back surface of the dielectric 11
The lower electrode 31 is formed in a portion other than
11 between 22 and 31 and between 22 and 31 and 23 and 31 respectively
Is a dielectric material.
【００３２】図１８に、本発明の第五の実施例を用いた
アレイ状マイクロチップコンデンサの実装図を示す。マ
イクロチップコンデンサは誘電体１１の上下のＶ溝の鋭
角部に応力が集中し、誘電体１１は上下のＶ溝の鋭角部
を結んだ線上で割れ、第２２図のようにアレイ状マイク
ロチップコンデンサは各々個別のマイクロチップコンデ
ンサに切り放される。よって上下のＶ溝の鋭角部を結ん
だ線の位置によって、割れる位置を特定することができ
る。FIG. 18 shows a mounting diagram of an arrayed microchip capacitor using the fifth embodiment of the present invention. In the microchip capacitor, stress concentrates on the acute angle portions of the upper and lower V-grooves of the dielectric 11, and the dielectric material 11 breaks on the line connecting the acute angle portions of the upper and lower V-grooves, and as shown in FIG. Are separated into individual microchip capacitors. Therefore, the position of the split can be specified by the position of the line connecting the acute angles of the upper and lower V-grooves.
【００３３】図１０は、第五乃至第九の実施例のアレイ
状マイクロチップコンデンサの実装後の等価回路であ
る。各々のコンデンサは上記に示したように完全に切り
放されるので、隣り合うコンデンサ間の容量はほとんど
無くなる。FIG. 10 is an equivalent circuit after mounting the arrayed microchip capacitors of the fifth to ninth embodiments. Since each capacitor is completely disconnected as shown above, there is little capacity between adjacent capacitors.
【００３４】[0034]
【発明の効果】以上、詳細に説明したように本発明の第
一の実施例によれば、従来のアレイ状マイクロチップコ
ンデンサと比べ、隣り合う上部電極間の容量を低減でき
るので、複数の電源端子を有する集積回路等の電源のデ
カップリングコンデンサとして使用した場合、各々の電
源端子間のカップリングが低減でき、集積回路の動作に
及ぼす悪影響を防止できる、という効果が得られる。As described in detail above, according to the first embodiment of the present invention, the capacitance between adjacent upper electrodes can be reduced as compared with a conventional array-type microchip capacitor. When used as a decoupling capacitor for a power supply of an integrated circuit or the like having terminals, the effect of reducing coupling between the power supply terminals and preventing an adverse effect on the operation of the integrated circuit can be obtained.
【００３５】また、本発明の第二の実施例によれば、従
来のアレイ状マイクロチップコンデンサと比べ、スルー
ホールにより隣り合うコンデンサ間は分離されるので、
複数の電源端子を有する集積回路等の電源のデカップリ
ングコンデンサとして使用した場合、各々の電源端子間
のカップリングが低減でき、集積回路の動作に及ぼす悪
影響を防止できる、という効果が得られる。According to the second embodiment of the present invention, adjacent capacitors are separated by through holes as compared with the conventional array-shaped microchip capacitors.
When used as a decoupling capacitor for a power supply of an integrated circuit or the like having a plurality of power supply terminals, the effect of reducing coupling between each power supply terminal and preventing an adverse effect on the operation of the integrated circuit can be obtained.
【００３６】ここで、第二の実施例では、各々のコンデ
ンサの間にスルーホールを設けることで各コンデンサ間
を分離していたが、スルーホールを用いた場合、スルー
ホールとスルーホールの間は誘電体１１があるため隣り
合うコンデンサ間は完全には分離されない。しかし、第
三の実施例では各々のコンデンサ間を金属ブロックで完
全に分離しているので、複数の電源端子を有する集積回
路等の、電源のデカップリングコンデンサとして使用し
た場合、各々の電源端子間のカップリングが低減でき、
集積回路の動作に及ぼす悪影響を防止できる、という効
果が得られる。Here, in the second embodiment, each capacitor is separated by providing a through hole between each capacitor. However, when a through hole is used, the distance between the through holes is small. Because of the presence of the dielectric 11, adjacent capacitors are not completely separated. However, in the third embodiment, since each capacitor is completely separated by a metal block, when used as a decoupling capacitor of a power supply such as an integrated circuit having a plurality of power supply terminals, each power supply terminal Coupling can be reduced,
An effect is obtained that an adverse effect on the operation of the integrated circuit can be prevented.
【００３７】本発明の第四の実施例によれば、第二の実
施例及び第三の実施例のアレイ状マイクロチップコンデ
ンサと比べ、実装後、隣り合うコンデンサ間は完全に切
り放されるので、隣り合うコンデンサ間の容量はほとん
ど無くなり、複数の電源端子を有する集積回路等の電源
のデカップリングコンデンサとして使用した場合、各々
の電源端子間のカップリングが低減でき、集積回路の動
作に及ぼす悪影響を防止できる、という効果が得られ
る。According to the fourth embodiment of the present invention, adjacent capacitors are completely separated after mounting, as compared with the arrayed microchip capacitors of the second and third embodiments. When the capacitor is used as a decoupling capacitor for a power supply of an integrated circuit having a plurality of power supply terminals, the coupling between the power supply terminals can be reduced, thereby adversely affecting the operation of the integrated circuit. Can be prevented.
【００３８】また、本発明の第五の実施例によれば、マ
イクロチップコンデンサ配置部が金メッキ等によりメタ
ライズされ、基板６１に、本発明の第四、第六乃至第九
の実施例のアレイ状マイクロチップコンデンサをＡｕＳ
ｎ等のハンダを使って配置部に付け、基板６１を、誘電
体１１と熱膨張率の異なる物質とし、基板６１全体を加
熱しる。その後、基板６１を冷却すると基板６１と誘電
体１１の熱膨張率の違いにより、マイクロチップコンデ
ンサは、誘電体１１の凹溝の部分で割れ、各々個別のマ
イクロチップコンデンサに切り離されるため、電源端子
間のカップリングが低減でき、集積回路の動作に及ぼす
悪影響を防止できる、という効果が得られる。Further, according to the fifth embodiment of the present invention, the microchip capacitor arrangement portion is metallized by gold plating or the like, and the substrate 61 is provided with an array-like structure of the fourth, sixth to ninth embodiments of the present invention. AuS microchip capacitors
The substrate 61 is made of a material having a different coefficient of thermal expansion from that of the dielectric 11, and the entire substrate 61 is heated. Thereafter, when the substrate 61 is cooled, the microchip capacitor is broken at the concave groove portion of the dielectric 11 due to the difference in the coefficient of thermal expansion between the substrate 61 and the dielectric 11, and is separated into individual microchip capacitors. The effect is that coupling between them can be reduced and adverse effects on the operation of the integrated circuit can be prevented.
【００３９】本発明の第六の実施例によれば、誘電体の
上下に凹溝が設けてあるため、第四の実施例に比べ実装
時に割れやすい、という効果が得られる。According to the sixth embodiment of the present invention, since the grooves are provided on the upper and lower sides of the dielectric, an effect is obtained that it is more likely to be broken during mounting than in the fourth embodiment.
【００４０】本発明の、第四の実施例及び第六の実施例
のアレイ状マイクロチップコンデンサの場合、実装時に
各コンデンサ間のどこで割れるか特定できなかったが、
本発明の第七の実施例によれば、誘電体１１の上面に幅
の狭い凹溝52を設けてあるのでこの溝52の位置を決める
ことで割れる位置を特定できる。例えば、誘電体１１の
上面に幅の狭い凹溝52を各コンデンサ間の中央に設けて
おけば、実装後、凹溝52部で割れ、各コンデンサは均等
に切り放すことができる、という効果が得られる。In the case of the array-type microchip capacitors according to the fourth and sixth embodiments of the present invention, it was not possible to specify where the capacitors were broken between the capacitors during mounting.
According to the seventh embodiment of the present invention, since the narrow groove 52 is provided on the upper surface of the dielectric 11, the position of the groove 52 can be specified by determining the position of the groove 52. For example, if a narrow groove 52 is provided at the center between the capacitors on the upper surface of the dielectric 11, cracks occur at the groove 52 after mounting, and each capacitor can be cut off evenly. can get.
【００４１】本発明の第八の実施例によれば、誘電体１
１の溝をＶ字型にすることによりＶ溝の鋭角部に応力が
集中するため、第四の実施例及び第六の実施例乃至第七
の実施例のアレイ状マイクロチップコンデンサに比べ、
更に実装後に割れやすく、各コンデンサの分離が容易で
ある、という効果が得られる。According to an eighth embodiment of the present invention, the dielectric 1
Since the first groove is formed in a V-shape, stress concentrates on the acute angle portion of the V-groove, so that compared to the array-shaped microchip capacitors of the fourth embodiment and the sixth to seventh embodiments,
Further, there is obtained an effect that the capacitor is easily broken after mounting and each capacitor is easily separated.
【００４２】本発明の第八の実施例では、実装後、誘電
体１１が割れるとき、下部のＶ溝の鋭角部から真上に割
れるとは限らず、誘電体の上部電極の方に向かって割れ
てしまう可能性があり、そのため実装時にコンデンサを
破壊してしまう可能性があった。しかし、第九の実施例
では、誘電体１１は上下のＶ溝の鋭角部を結んだ線上で
割れるので、各々のコンデンサを破壊することは無い、
という効果が得られる。In the eighth embodiment of the present invention, when the dielectric 11 is cracked after mounting, the dielectric 11 does not necessarily break directly from the acute angle of the lower V-groove but toward the upper electrode of the dielectric. There is a possibility that the capacitor may be broken, and thus the capacitor may be broken during mounting. However, in the ninth embodiment, since the dielectric 11 breaks on the line connecting the acute angles of the upper and lower V-grooves, each capacitor does not break.
The effect is obtained.
【００４３】[0043]
【利用の形態】本発明の実施例では、３つのコンデンサ
がアレイ状に配置されたマイクロチップコンデンサにつ
いて示したが、コンデンサの数は３つに限定されるもの
ではなく、複数のコンデンサがアレイ状に配置されたマ
イクロチップコンデンサであれば良い。また複数のコン
デンサがマトリクス状に配置されたマイクロチップコン
デンサ等に用いても好適である。In the embodiment of the present invention, a microchip capacitor in which three capacitors are arranged in an array has been described. However, the number of capacitors is not limited to three. Any microchip capacitor may be used. It is also suitable for use in a microchip capacitor or the like in which a plurality of capacitors are arranged in a matrix.
【００４４】本発明の実施例では、マイクロチップコン
デンサの誘電体としてセラミックを例にあげたが、セラ
ミック以外の誘電体に用いても好適である。In the embodiments of the present invention, ceramic has been described as an example of the dielectric of the microchip capacitor. However, it is preferable to use a dielectric other than ceramic.
【００４５】本発明の実施例で示した図では、単層のマ
イクロチップコンデンサについて示したが、単層に限ら
ず積層構造のマイクロチップコンデンサに用いても好適
である。In the drawings shown in the embodiments of the present invention, a single-layer microchip capacitor is shown. However, the present invention is not limited to a single-layer microchip capacitor and may be suitably used for a microchip capacitor having a laminated structure.
【図１】第一の実施例のアレイ状マイクロチップコンデ
ンサの構成図である。FIG. 1 is a configuration diagram of an arrayed microchip capacitor according to a first embodiment.
【図２】第一の実施例のアレイ状マイクロチップコンデ
ンサの等価回路図である。FIG. 2 is an equivalent circuit diagram of the array-type microchip capacitor of the first embodiment.
【図３】第二の実施例のアレイ状マイクロチップコンデ
ンサの構成図である。FIG. 3 is a configuration diagram of an array-shaped microchip capacitor according to a second embodiment.
【図４】第二の実施例のアレイ状マイクロチップコンデ
ンサの断面図である。FIG. 4 is a sectional view of an arrayed microchip capacitor according to a second embodiment.
【図５】第二及び第三の実施例のアレイ状マイクロチッ
プコンデンサの等価回路図である。FIG. 5 is an equivalent circuit diagram of the arrayed microchip capacitors of the second and third embodiments.
【図６】第三の実施例のアレイ状マイクロチップコンデ
ンサの構成図である。FIG. 6 is a configuration diagram of an arrayed microchip capacitor according to a third embodiment.
【図７】第三の実施例のアレイ状マイクロチップコンデ
ンサの断面図である。FIG. 7 is a sectional view of an arrayed microchip capacitor according to a third embodiment.
【図８】第四の実施例のアレイ状マイクロチップコンデ
ンサの構成図である。FIG. 8 is a configuration diagram of an arrayed microchip capacitor according to a fourth embodiment.
【図９】第五の実施例のアレイ状マイクロチップコンデ
ンサの実装図である。FIG. 9 is a mounting diagram of an arrayed microchip capacitor according to a fifth embodiment.
【図１０】第五乃至第九の実施例のアレイ状マイクロチ
ップコンデンサの等価回路図である。FIG. 10 is an equivalent circuit diagram of an arrayed microchip capacitor according to the fifth to ninth embodiments.
【図１１】第六の実施例のアレイ状マイクロチップコン
デンサの構成図である。FIG. 11 is a configuration diagram of an arrayed microchip capacitor according to a sixth embodiment.
【図１２】第六の実施例のアレイ状マイクロチップコン
デンサの実装図である。FIG. 12 is a mounting diagram of an arrayed microchip capacitor according to a sixth embodiment.
【図１３】第七の実施例のアレイ状マイクロチップコン
デンサの構成図である。FIG. 13 is a configuration diagram of an arrayed microchip capacitor according to a seventh embodiment.
【図１４】第七の実施例のアレイ状マイクロチップコン
デンサの実装図である。FIG. 14 is a mounting view of an arrayed microchip capacitor according to a seventh embodiment.
【図１５】第八の実施例のアレイ状マイクロチップコン
デンサの構成図である。FIG. 15 is a configuration diagram of an arrayed microchip capacitor according to an eighth embodiment.
【図１６】第八の実施例のアレイ状マイクロチップコン
デンサの実装図である。FIG. 16 is a mounting diagram of an arrayed microchip capacitor according to an eighth embodiment.
【図１７】第九の実施例のアレイ状マイクロチップコン
デンサの構成図である。FIG. 17 is a configuration diagram of an arrayed microchip capacitor according to a ninth embodiment.
【図１８】第九の実施例のアレイ状マイクロチップコン
デンサの実装図である。FIG. 18 is a mounting diagram of an array-shaped microchip capacitor according to a ninth embodiment.
【図１９】従来のアレイ状マイクロチップコンデンサの
構成図である。FIG. 19 is a configuration diagram of a conventional array-shaped microchip capacitor.
【図２０】従来のアレイ状マイクロチップコンデンサの
等価回路図である。FIG. 20 is an equivalent circuit diagram of a conventional array-shaped microchip capacitor.
１１ 誘電体 ２１、２２、２３ 上部電極 ３１ 下部電極 11 Dielectric 21, 22, 23 Upper electrode 31 Lower electrode
Claims (11)
なる複数のコンデンサを、アレイ状に配置したマイクロ
チップコンデンサにおいて、 前記誘電体の上面に配置された複数の前記上部電極の間
の前記誘電体部分に窪みを設けたことを特徴とするアレ
イ状マイクロチップコンデンサ。1. A microchip capacitor in which a plurality of capacitors each having a dielectric sandwiched between an upper electrode and a lower electrode are arranged in an array, wherein the plurality of capacitors are arranged between the plurality of upper electrodes disposed on the upper surface of the dielectric. An array-shaped microchip capacitor, wherein a depression is provided in the dielectric portion.
なる複数のコンデンサを、アレイ状に配置したマイクロ
チップコンデンサにおいて、 前記誘電体の上面に配置された複数の前記上部電極の間
に、前記誘電体の裏面に配置された前記下部電極とスル
ーホールにより電気的に接続された導電性薄膜を、設け
たことを特徴とするアレイ状マイクロチップコンデン
サ。2. A microchip capacitor in which a plurality of capacitors each having a dielectric sandwiched between an upper electrode and a lower electrode are arranged in an array, wherein the plurality of capacitors are arranged between the plurality of upper electrodes arranged on the upper surface of the dielectric. And a conductive thin film electrically connected to the lower electrode disposed on the back surface of the dielectric by a through hole.
なる複数のコンデンサを、アレイ状に配置したマイクロ
チップコンデンサにおいて、 前記誘電体の上面に配置された複数の前記上部電極の間
に、誘電体の裏面に配置された前記下部電極と接続され
た導電性ブロックを設けることを特徴とするアレイ状マ
イクロチップコンデンサ。3. A microchip capacitor in which a plurality of capacitors each having a dielectric sandwiched between an upper electrode and a lower electrode are arranged in an array, wherein the plurality of capacitors are arranged between the plurality of upper electrodes disposed on an upper surface of the dielectric. And an electrically conductive block connected to the lower electrode disposed on the back surface of the dielectric.
る複数のコンデンサを、アレイ状に配置したマイクロチ
ップコンデンサにおいて、 前記誘電体の上面に複数の前記上部電極が配置され、前
記誘電体の裏面の複数の前記下部電極間に凹形状の溝を
設けたことを特徴とするアレイ状マイクロチップコンデ
ンサ。4. A microchip capacitor in which a plurality of capacitors each having a dielectric sandwiched between an upper electrode and a lower electrode are arranged in an array, wherein the plurality of upper electrodes are disposed on an upper surface of the dielectric, An array-shaped microchip capacitor, wherein a concave groove is provided between the plurality of lower electrodes on the back surface of the microchip capacitor.
コンデンサにおいて、 前記誘電体の上面の複数の前記上部電極間にも凹形状の
溝を設けたことを特徴とするアレイ状マイクロチップコ
ンデンサ。5. The array-type microchip capacitor according to claim 4, wherein a concave groove is also provided between the plurality of upper electrodes on the upper surface of the dielectric.
コンデンサにおいて、 前記誘電体の上面の複数の前記上部電極間の凹形状の溝
の幅を、前記下部電極間に設けられた凹形状の溝の幅よ
りも狭くしたことを特徴とするアレイ状マイクロチップ
コンデンサ。6. The array-shaped microchip capacitor according to claim 5, wherein the width of the concave groove between the plurality of upper electrodes on the upper surface of the dielectric is set to the concave groove provided between the lower electrodes. An array-shaped microchip capacitor characterized in that the width is smaller than the width of the microchip capacitor.
コンデンサにおいて、 前記誘電体の上面に複数の前記上部電極が配置され、前
記誘電体の裏面に各々の前記下部電極間に設けた凹形状
の溝がＶ字型であることを特徴とするアレイ状マイクロ
チップコンデンサ。7. The array-shaped microchip capacitor according to claim 4, wherein a plurality of said upper electrodes are arranged on an upper surface of said dielectric, and a concave shape provided between said lower electrodes on a back surface of said dielectric. An array-shaped microchip capacitor having a V-shaped groove.
コンデンサにおいて、 前記誘電体の上面の複数の前記上部電極間にもＶ字型の
溝が設けられたことを特徴とするアレイ状マイクロチッ
プコンデンサ。8. The array-type microchip capacitor according to claim 7, wherein a V-shaped groove is also provided between the plurality of upper electrodes on the upper surface of the dielectric. .
コンデンサを実装する方法であって、 前記誘電体に、アレイ状マイクロチップコンデンサを実
装する基体に比べ熱膨張率の異なる物質を用い、前記誘
電体の上面の幅の狭い凹形状の溝を設ける位置により、
実装時に割れる位置が、前記上面の幅の狭い凹形状の溝
部に特定されることを特徴とするアレイ状マイクロチッ
プコンデンサの実装方法。9. The method for mounting an arrayed microchip capacitor according to claim 6, wherein the dielectric is made of a material having a different coefficient of thermal expansion than a substrate on which the arrayed microchip capacitor is mounted. Depending on the position of the narrow concave groove on the upper surface of the body,
A method of mounting an array-shaped microchip capacitor, wherein a position at which the chip is broken at the time of mounting is specified by a concave groove having a narrow upper surface.
プコンデンサを実装する方法であって、 前記誘電体に、アレイ状マイクロチップコンデンサを実
装する基体に比べ熱膨張率の異なる物質を用い、前記誘
電体の上面及び裏面のＶ字型の溝を設ける位置により、
実装時に割れる位置が、前記上面及び裏面のＶ字型の溝
の鋭角部を結んだ線上に特定されることを特徴とするア
レイ状マイクロチップコンデンサの実装方法。10. The method of mounting an arrayed microchip capacitor according to claim 8, wherein the dielectric is made of a material having a different coefficient of thermal expansion than a substrate on which the arrayed microchip capacitor is mounted. Depending on the location of the V-shaped grooves on the top and back of the body,
A method of mounting an array-shaped microchip capacitor, wherein a position at which the chip is broken during mounting is specified on a line connecting the acute angles of the V-shaped grooves on the upper surface and the rear surface.
マイクロチップコンデンサを実装する方法であって、前
記誘電体に、アレイ状マイクロチップコンデンサを実装
する基体に比べ熱膨張率の異なる物質を用いたことを特
徴とするアレイ状マイクロチップコンデンサの実装方
法。11. The method for mounting an arrayed microchip capacitor according to claim 4, wherein a material having a different coefficient of thermal expansion than a substrate on which the arrayed microchip capacitor is mounted is provided on the dielectric. A method for mounting an array-shaped microchip capacitor, which is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10290794A JP2000124066A (en) | 1998-10-13 | 1998-10-13 | Microchip capacitor and method of mounting thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10290794A JP2000124066A (en) | 1998-10-13 | 1998-10-13 | Microchip capacitor and method of mounting thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000124066A true JP2000124066A (en) | 2000-04-28 |
Family
ID=17760590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10290794A Abandoned JP2000124066A (en) | 1998-10-13 | 1998-10-13 | Microchip capacitor and method of mounting thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000124066A (en) |
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