JP2000122843A - Communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform smooth communication control without breaking a chain by repairing management information that chains buffer areas by correction by means of error detection and correction codes even when an error occurs. SOLUTION: Transmission and reception data are divided and stored in buffer areas 2a to 2z of a memory 1. Respective buffer areas 2a to 2z are provided with a management information area 4 and a main information area 3. The management information area 4 has information that chains each buffer area. The area 4 includes error detection and correction codes 5 and is accessed at the same time with management information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device for temporarily storing transmission / reception data in a buffer memory, sequentially reading out the data, and controlling data communication.

[0002]

2. Description of the Related Art When transmitting and receiving data through a network or the like, a communication control device temporarily stores transmission and reception data in a buffer memory, reads out the data at a predetermined timing, and performs transfer control. Such a buffer memory includes a first-in first-out (FIFO) type memory and a type in which data is read and written by supplying a read address and a write address.

In the case of a FIFO type memory, the data transfer order is automatically determined because previously written data is read first. In the latter case, the transmission / reception data is divided and stored in a plurality of buffer areas in the memory. Each buffer area is connected by a chain in the order of data transfer.

In order to perform such control, each buffer area is provided with a main information area for storing transmission / reception data and a management information area for storing management information for chaining the buffer areas. The management information area stores the relative address of the buffer area to be chained next.
While referring to the management information area, the main information area is accessed in order, and the transmission / reception data can be read from the memory in the order of transfer.

[0005]

However, the above-mentioned prior art has the following problems to be solved.
When reading / writing data from / to a memory, a write or read error may occur for various reasons. Parity bits are employed to detect such errors and prevent data errors. For example, in the case of 16-bit data, the last 16th bit is a parity bit, and information such as "0" is displayed when 1 is included in the remaining 15 bits, and "1" is displayed when an odd number is included. . As a result, control is performed such as detecting an error in the read data and reading the data from the memory again, or invalidating the read data.

However, there is a case where there is an error in the management information for chaining the buffer areas to each other, and the error does not disappear even when the data is re-read. In such a case, the chain to the next buffer area is interrupted, so that chain management becomes impossible. Therefore, there is a problem that the entire system must be temporarily stopped and initialized. That is, since the chain after the buffer area is broken, there is a problem that all the transmission / reception data already stored in the memory must be discarded and the writing must be performed again.

Further, in the parity check, when an error has an even number of bits, it cannot be distinguished from the case where there is no error. Therefore, if there is an even-bit error in the main information area, the processing proceeds without noticing the error. For this reason, the contents of a buffer area completely different from the buffer area to be chained may be read as transmission / reception data.

Moreover, when a memory is used as a buffer for transmission and reception, once data is read, that portion is used as a buffer area for writing another data. Therefore, when the erroneously read data is valid data connected to another chain, there is also a problem that new data is overwritten in the corresponding buffer area and the valid data is lost. In the communication control device, without hindering high-speed data access,
These problems need to be solved.

[0009]

The present invention employs the following structure to solve the above problems. <Structure 1> A plurality of buffer areas for storing divided transmission / reception data are provided in a memory. Each of the buffer areas includes a main information area for storing the divided transmission / reception data and the buffer area. And a management information area storing management information for mutual chaining. The management information area includes an error detection and correction code of the management information in an unused bit portion accessed simultaneously with the management information. A communication control device characterized by the above-mentioned.

<Structure 2> In the communication control apparatus according to structure 1, the management information area includes, in an unused bit portion accessed simultaneously with the management information, a parity bit for error detection of the management information and a parity bit for the management information. A communication control device including an error detection and correction code.

<Structure 3> A plurality of buffer areas for storing divided transmission / reception data are provided in a memory. Each of the buffer areas has a main information area for storing the divided transmission / reception data, A management information area storing management information for mutually chaining buffer areas is provided. The management information area includes a main information area relative address for specifying an address of the main information area, and a buffer area to be chained next. A communication control device, comprising: a next chain management area relative address for specifying an address of the management information area of (1), wherein an error detection and correction code is added to at least the next chain management area relative address.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. <Example 1> FIG. 1 is a block diagram showing a main part of a communication control apparatus according to the present invention. The memory 1 shown is provided for a buffer of a communication control device. Here, transmission / reception data is divided and stored in appropriate units. The divided transmission / reception data is sequentially stored in buffer areas 2a to 2z as shown in the figure. Each buffer area 2a-2
z has a main information area 3 and a management information area 4 as shown on the right side of the figure. Further, in the management information area 4,
An error detection and correction code 5 is added. Before specifically describing the configuration of such a memory space, first, the function of the entire communication control unit and the operation of the memory 1 will be described.

FIG. 2 is a diagram for explaining the operation of the memory of the communication control unit. In the system shown in this figure, transmission / reception data generated by the data generation unit 11 is sent to the transmission line 13 via the communication control device 12. A communication control device 14 on the receiving side is connected to the transmission line 13. The transmission / reception data received by the communication control device 14 is transferred to the data receiving unit 15 and used. The communication control device 12 and the communication control device 14 of such a system are provided with a memory 16 for temporarily storing and transferring transmission / reception data.

In the case of packet communication, a transmission packet is temporarily stored in a memory 16 as shown in FIG.
6 and transferred. Further, the received packet is temporarily stored in the memory 16, and the received packet is read out again and taken into the apparatus. When writing such transmission / reception data to the memory 16, as shown in FIG. 1, a memory space for storing the entire transmission / reception data is divided into a plurality of parts in advance, and the divided transmission / reception data is stored in each buffer in the memory 1. It is stored in the areas 2a to 2z.

The main information area 3 is a storage area for storing divided transmission / reception data. The management information area 4 stores management information for chaining the buffer areas 2a to 2z.

FIG. 3 is an explanatory diagram of a chain of such a memory space. As shown in the figure, a main information area relative address 6 and a next chain management area relative address 7 are stored in the management information area 4a. The main information area relative address 6 specifies the address of the head of the main information area 3a, and the main information is read. The main information is divided transmission / reception data.

The next address of the management information area 4b of the buffer area to be chained next to this buffer area is designated by the next chain management area relative address 7. Therefore, for example, in the case of FIG.
When the main information area relative address 6a is referred to and the main information of the main information area 3a is read, the next chain management area relative address 7 is referred to this time.

As a result, the main information area relative address 6 in the management information area 4b is referred to, and the main information in the main information area 3b is read. Thereafter, the next chain management area relative address 7 is referred to, and the main information area relative address 6 of the management information area 4c is referred to. In this manner, the main information areas 3a, 3b, 3c, 3d are sequentially read.

FIG. 4 is an explanatory diagram (part 1) of a management information error. Here, for example, consider a case where an error occurs in the main information area relative address 6 included in the management information area 4a in FIG. In this case, the main information area 3a cannot be referred to. Therefore, the transmission / reception data of this part is discarded, and the main information area relative address 6 of the management information area 4b is referred to by the next chain management area relative address 7. And
The next main information area 3b is read.

By performing such processing, the main information area 3a
Are discarded, and the remaining communication data are sequentially read. Even if a part of the communication data is lost, the communication data itself can often maintain normal communication by various error recovery functions or the like. On the other hand, even if the management information is the same, if an error occurs in the next chain management area relative address 7, the following problem occurs.

FIG. 5 is a diagram (part 2) for explaining a management information error. Assume that an error has occurred in the next chain management area relative address 7 of the management information area 4a shown in the figure. In this case, the next management information area 4b cannot be referred to.
Therefore, the chain is interrupted here, and the following main information area 3
b, 3c and 3d cannot be read. Also,
If an error in the next chain management area relative address 7 cannot be detected and the erroneous location is determined as the management information area of the next buffer area, completely invalid data may be read.

In the present invention, in order to solve this problem,
As shown in FIG. 1, an error detection and correction code 5 of the management information is included in an unused bit portion accessed simultaneously with the management information in the management information area 4. For example, it is assumed that the management information area 4 is read with 16 bits and 1 word. In this case, the main information area relative address is stored in the upper 8 bits, and the error detection and correction code is included in the lower 8 bits. The next 8 bits of the 16-bit data to be read next store the next chain management area relative address, and the lower 8 bits contain the error detection and correction code.

Since 16 bits are simultaneously read, the read relative address of the main information area and the relative address of the next chain management area are detected by the added error detection and correction codes, respectively. Can be corrected. The error detection and correction code 5 is a C code often used in the information processing field.
An RC (cyclic redundancy check) code is used.

By using this CRC code, it is possible to detect and correct a one-bit error in the target data. Further, when there is an error of two bits or more in the target data, it has a function of detecting the error. Therefore, even if a 1-bit error occurs in the relative address of the main information area or the relative address of the next chain management area, this can be automatically corrected during the memory access and the transmitted / received data can be accessed. become.

Further, when an error of 2 bits or more is present, the error can be detected and re-reading or initialization of the memory can be performed. The problem of accessing and destroying other valid data can be prevented.

In the above example, the error detection and correction codes are added to both the main information area relative address and the next chain management area relative address. However, as described with reference to FIGS. 4 and 5, since an error in the next chain management area relative address has the most serious effect, an error detection and correction code is added to the next chain management area relative address, and the As in the past, a method of adding only parity bits to the information area relative address may be employed.

The error detection and correction code is included in the unused bit portion of the management information area which is accessed simultaneously with the management information, in order to realize simultaneous access, simultaneous reference and correction processing in the same manner as the parity bit. It is. Another reason is to ensure the high speed of this type of data processing in communication control. Simultaneous means that there is no interval, and when the management information is read in multiple times,
Needless to say, even if the management information and the error detection and correction codes are read twice from the memory continuously, the process corresponds to the simultaneous reading here.

In the above example, the error detection and correction code is included in the unused bit portion of the management information. Since the number of bits of the relative address of the main information area and the relative address of the next chain management area used for the buffer area chain is relatively small, the conventional data can be obtained by including such information in the unused bit portion of the management information. The reliability of the device can be improved without changing the format.

<Effect of Specific Example 1> As described above, by including an error detection and correction code of the management information in an unused bit portion accessed simultaneously with the management information, if there is an error that can be corrected, this is corrected. And a normal chain can be secured. Further, even an uncorrectable error can be reliably detected, and access to an incorrect chain can be prevented. Thereby, the initialization processing of the memory due to the interruption of the chain can be reduced, malfunction can be prevented, and high-speed communication control can be ensured.

<Embodiment 2> FIG. 6 is a block diagram showing a modification of the memory space according to Embodiment 2. In the example in this figure,
Each of the buffer areas 2a to 2z includes a main information area 3,
The management information area 4 includes an error detection and correction code 5 and a parity bit 8. That is, in this example, a parity bit is further added to the management information area of the specific example 1. The following cases can be considered as specific combinations.

For example, there is a method of adding an error detection and correction code 5 and a parity bit 8 to the main information area relative address 6 and the next chain management area relative address 7 of the management information area 4a shown in FIG. Also, there is a method in which only a parity bit is simply added to the main information area relative address, and an error detection and correction code is added to the next chain management area relative address 7.

This is because, if an error is detected in the main information area relative address 6, even if the error is ignored, the chain will not be interrupted. Further, only the error detection and correction code 5 is included in the main information area relative address 6, and the error detection and correction code 5 and the parity bit 8 are added to the next chain management area relative address 7.

As described above, if the management information is checked using both the error detection and correction code 5 and the parity bit 8, the reliability of the check is increased, the error can be detected reliably, and the access to the erroneous area can be reliably performed. Can be prevented. Therefore, it is possible to sufficiently maintain the required performance particularly in the communication control unit which is required to have high reliability and high speed data transfer.

In the above example, the error detection and correction codes are added only to the management information area. However, if necessary, the present invention can be applied to the main information area and other memory management data areas.

<Effect of Specific Example 2> By including a parity bit together with an error detection and correction code in the management information area, the error detection capability is enhanced, and a highly reliable memory access is enabled.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a communication control device according to the present invention.

FIG. 2 is an explanatory diagram of a memory operation of a communication control unit.

FIG. 3 is an explanatory diagram of a chain of a memory space.

FIG. 4 is an explanatory diagram (part 1) of a management information error.

FIG. 5 is an explanatory diagram (part 2) of a management information error.

FIG. 6 is a block diagram showing a modified example of a memory space.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory 2a-2z buffer area 3 main information area 4 management information area 5 error detection and correction code

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tatsusaku Matsushita 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. F-term (reference) 5B089 GA04 KA12 KD01 KD04 KD06

Claims (3)

[Claims] A plurality of buffer areas for storing divided transmission / reception data are provided in a memory, wherein each of the buffer areas has a main information area for storing the divided transmission / reception data, and a buffer area. And a management information area storing management information for mutually chaining the management information. The management information area includes an error detection and correction code of the management information in an unused bit portion accessed simultaneously with the management information. A communication control device. 2. The communication control device according to claim 1, wherein in the management information area, an unused bit portion accessed simultaneously with the management information includes a parity bit for detecting an error in the management information, and an error in the management information. A communication control device including detection and correction codes. 3. A plurality of buffer areas for storing divided transmission / reception data in a memory, wherein each of the buffer areas includes a main information area for storing the divided transmission / reception data, and a buffer area. A management information area storing management information for mutually chaining, a management information area includes a main information area relative address for specifying an address of the main information area, and a management of a buffer area to be chained next. A communication control device comprising: a next chain management area relative address for specifying an address of an information area; and an error detection and correction code added to at least the next chain management area relative address.