JP2013247556A - Buffer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly reconfigure all packets in a memory area managed by storage information even when an error occurs in the storage information.SOLUTION: A buffer device comprises: a packet storage information generation unit 501 for generating storage information for each packet; an error correction code generation unit 502 for generating an error correction code for each storage information; a memory writing unit 504 for writing to a memory 505 a data block in which packet data is associated with management data; a memory reading unit 506 for reading the data block in the memory 505; a packet management data temporary storage unit 507 for storing the management data in the data block; an error correction unit 508 for correcting an error of the storage information by using the error correction code of the management data; a packet reconfiguration unit 510 for reconfiguring a packet on the basis of the storage data of the packet data and the management data in the data block; and a reconfiguration control unit 509 for designating reconfiguration of a packet after finishing of the error correction by the error correction unit 508.

Description

  The present invention relates to a buffer device that enables error correction of stored information that records the storage state of data such as packets in a memory.

  In recent years, with the rapid spread of the Internet, communication networks have been dramatically developed. In particular, data communication represented by IP (Internet Protocol) packets is becoming the mainstream of traffic of the entire communication network. In addition, an increase in the capacity of devices due to an increase in demand for communication services and an increase in communication speed have become prominent.

  On such communication networks, routers and switches for packet transfer are arranged, but when performing packet transfer processing, the data transfer rates of the transfer source and transfer destination communication networks are not always the same. Absent. Further, when congestion occurs in the transfer destination communication network, the packet cannot be transferred to the communication network.

  In such a case, a function for temporarily storing packets until packet transfer can be started is necessary. This function is called a packet buffer and is generally composed of a memory and a memory control device. Since the packet buffer needs to support data communication requiring a large capacity and a high data transfer rate, an inexpensive and large capacity DRAM is often used for the memory. The DRAM is a memory that can obtain a high data transfer rate by performing burst transfer.

  As a method of constructing a packet buffer device, Patent Document 1 as a conventional method shows a method of efficiently using a memory by changing a packet storage method in the memory according to a received packet size. Japanese Patent Application Laid-Open No. 2004-228561 shows a method for realizing high-speed access to a memory by dividing and integrating received packets so as to have a data size suitable for writing to the memory.

JP-A-8-139752 JP 2009-157680 A

  The above-mentioned prior patents create packet storage information that records the packet storage state in the memory when storing received packets in the memory in order to achieve efficient use of the memory and high-speed access to the memory. ing. In Patent Document 1, a short buffer table and a long buffer table correspond to packet storage information, and in Patent Document 2, an address management table corresponds to packet storage information. For this reason, if this packet storage information has an error due to noise around the board on which the memory is mounted, a memory soft error, etc., the packet storage state in the memory cannot be recognized correctly, so the memory managed by the packet storage information There is a problem that all packets included in the area cannot be reconstructed correctly. As a result, packets that could not be correctly reconfigured are discarded, but retransmission control of the discarded packets increases the traffic of the communication network, leading to compression of the effective bandwidth.

  The present invention has been made in order to solve the above-described problems, and even if an error occurs in the storage information recording the storage state of data such as a packet in the memory, it is included in the memory area managed by the storage information. An object of the present invention is to provide a buffer device capable of correctly reconstructing all data to be reconstructed.

  The buffer device according to the present invention includes, for each received data, a storage information generation unit that generates storage information in the memory of the data, and an error that generates an error correction code for each storage information generated by the storage information generation unit Including a correction code generation unit, integrated data in which data is collected to a size suitable for accessing the memory, storage information generated by the storage information generation unit, and an error correction code generated by the error correction code generation unit A memory writing unit for writing a data block associated with management data to the memory, a memory reading unit for reading the data block stored in the memory, and management data included in the data block read by the memory reading unit are stored. Included in the management data temporary storage section and the management data stored in the management data temporary storage section. Included in error correction unit that corrects error in stored information using error correction code, integrated data included in data block read by memory reading unit, and management data stored in management data temporary storage unit A reconfiguration unit that reconfigures data based on the stored information, a reconfiguration control unit that instructs the reconfiguration unit to reconfigure data after the error correction unit completes error correction for the stored information, and It is equipped with.

  According to this invention, since it is configured as described above, even if an error occurs in the storage information that records the storage state of data such as a packet in the memory, all the data included in the memory area managed by the storage information is stored. Data can be correctly reconstructed, and data discard due to incorrect stored information can be reduced.

It is a figure which shows the structural example of the packet transfer apparatus in Embodiment 1 of this invention. It is a figure which shows the whole structure which shows the packet buffer apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows operation | movement (packet writing) of the packet buffer apparatus based on Embodiment 1 of this invention. It is a figure which shows the internal structural example of the memory in Embodiment 1 of this invention. It is a figure which shows the example of an internal structure of the packet management data in Embodiment 1 of this invention. It is a figure which shows the example of an internal structure of the packet data in Embodiment 1 of this invention. It is a flowchart which shows operation | movement (packet reading and reconfiguration | reconstruction) of the packet buffer apparatus based on Embodiment 1 of this invention. It is a figure which shows the internal structural example of the packet management data temporary storage part in Embodiment 1 of this invention. It is a figure explaining the encoding format in the packet buffer apparatus which concerns on Embodiment 1 of this invention. It is a figure explaining another encoding format with the packet buffer apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the whole structure which shows the packet buffer apparatus based on Embodiment 2 of this invention. It is a figure which shows the example of an internal structure of the packet management data in Embodiment 2 of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, a packet buffer device 5 that temporarily stores packets is used as the buffer device.
Embodiment 1 FIG.
First, a configuration example of a packet transfer device 1 to which the packet buffer device 5 of the present invention is applied will be described with reference to FIG.
On a communication network such as the Internet, a packet transfer device 1 such as a router or a switch is arranged as an example. The packet transfer apparatus 1 connects a plurality of communication networks to each other, and has a role of transferring packets from end to end.

As shown in FIG. 1, the packet transfer apparatus 1 includes a control device 4 and a packet buffer device 5. In normal time, the packet received at the port on the packet transmission source 2 side is directly transferred to the port on the packet transmission destination 3 side. On the other hand, when congestion of the packet transmission destination 3 is detected, control is performed so that the packet transmission source 2 does not transmit the packet. However, since there is a time difference between this control and the actual packet transmission stoppage, packets already transmitted from the packet transmission source 2 continue to be received by the port on the packet transmission source 2 side. Therefore, in order not to discard this packet, it is necessary to temporarily store a packet that cannot be transferred to the port on the packet transmission destination 3 side.
Therefore, when detecting the congestion of the packet transmission destination 3, the control device 4 stores the packet arriving at the port on the packet transmission source 2 side in the packet buffer device 5. Thereafter, when the congestion of the packet transmission destination 3 is resolved and the packet can be transferred, the packet stored in the packet buffer device 5 is read and output to the port on the packet transmission destination 3 side.

Next, the overall configuration of the packet buffer device 5 will be described with reference to FIG.
As shown in FIG. 2, the packet buffer device 5 includes a packet storage information generation unit (storage information generation unit) 501, an error correction code generation unit 502, a memory control unit 503, a memory writing unit 504, a memory 505, and a memory reading unit 506. , A packet management data temporary storage unit (management data temporary storage unit) 507, an error correction unit 508, a packet reconstruction control unit (reconfiguration control unit) 509, and a packet reconstruction unit (reconstruction unit) 510.

  The packet storage information generation unit 501 generates packet storage information (storage information) in which storage information of the packet in the memory 505 is recorded for each packet received from the packet transmission source 2. The packet storage information generated by the packet storage information generation unit 501 is output to the error correction code generation unit 502 and the memory writing unit 504.

  The error correction code generation unit 502 generates an error correction code for each packet storage information from the packet storage information generation unit 501. The error correction code generated by the error correction code generation unit 502 is output to the memory writing unit 504.

  The memory control unit 503 controls reading and writing to the memory 505 with respect to the memory writing unit 504 and the memory reading unit 506 in accordance with instructions from the control device 4.

  The memory writing unit 504 accumulates packets received from the packet transmission source 2 to create packet data (integrated data), and associates the data from the packet storage information generation unit 501 and the error correction code generation unit 502 with the packet. Management data (management data) is created, and these are written as data blocks in the memory 505 under the control of the memory control unit 503.

  The memory 505 is a memory characterized by burst transfer for storing data blocks from the memory writing unit 504. Since the memory 505 can obtain a high data transfer rate by performing burst transfer, it is necessary to shape the received packet so that it is suitable for writing to the memory 505 and to return to the state of the packet before shaping at the time of reading. is there. Therefore, packet storage information is required when using a memory characterized by burst transfer.

  The memory reading unit 506 reads data blocks stored in the memory 505 under the control of the memory control unit 503. Among the data blocks read by the memory reading unit 506, packet management data is output to the packet management data temporary storage unit 507, and packet data is output to the packet reconfiguration unit 510.

The packet management data temporary storage unit 507 stores packet management data from the memory reading unit 506.
The error correction unit 508 corrects an error in the packet storage information using an error correction code included in the packet management data stored in the packet management data temporary storage unit 507.

The packet reconfiguration control unit 509 controls the packet reconfiguration unit 510 with reference to the packet management data temporary storage unit 507.
The packet reconfiguration unit 510 reconfigures a packet based on the packet management data stored in the packet management data temporary storage unit 507 and the packet data from the memory reading unit 506 in accordance with the control of the packet reconfiguration control unit 509. It is.

Next, the operation of the packet buffer device 5 configured as described above will be described. First, an operation from reception of a packet to writing into the memory 505 will be described with reference to FIG.
In the packet writing operation of the packet buffer device 5, as shown in FIG. 3, first, the packet storage information generation unit 501 generates packet storage information for each received packet, and the result is stored in the error correction code generation unit 502 and the memory. The data is output to the writing unit 504 (step ST31). Here, it is assumed that the packet storage information stores the packet size information of the received packet, and is used to record the packet storage position when the head of the data block is used as a reference position.
Next, error correction code generation section 502 generates an error correction code for each packet storage information generated by packet storage information generation section 501 and outputs the error correction code to memory writing section 504 (step ST32).

  Next, the memory writing unit 504 performs three processes of packet data creation, packet management data creation, and data block creation and writing to the memory 505 based on the input data (step ST33). Here, the packet data is created by accumulating packets that are sequentially input until a size suitable for accessing the memory 505 is obtained. The packet management data is created by storing the packet storage information from the packet storage information generation unit 501 and the error correction code from the error correction code generation unit 502 for all packets stored in the packet data. . A data block is created by storing packet data and corresponding packet management data in pairs. Then, by writing the completed data block into the memory 505 according to the control from the memory control unit 503, the operation of storing the received packet in the memory 505 is completed.

Here, FIG. 4 is a diagram illustrating an internal configuration example of the memory 505. As shown in FIG. 4, the memory 505 stores a data block 11 having a certain size, and the data block 11 stores packet management data 12 and packet data 13.
FIG. 5 is a diagram showing an example of the internal configuration of the packet management data 12. As shown in FIG. 5, the packet management data 12 stores packet storage information 14 and an error correction code 15 of the packet storage information 14 for each received packet.
FIG. 6 is a diagram showing an example of the internal configuration of the packet data 13. As shown in FIG. 6, the packet data 13 stores the received packet.

Next, the operation from reading out the data block 11 shown in FIG. 4 from the memory 505, reconstructing it as a packet, and outputting it will be described with reference to FIG.
In the packet read / reconstruction operation of the packet buffer device 5, first, as shown in FIG. 7, the memory read unit 506 reads the data block 11 from the memory 505 in accordance with the control from the memory control unit 503, The included packet management data 12 is output to the packet management data temporary storage unit 507 (step ST71). In addition, the packet data 13 included in the data block 11 is output to the packet reconstruction unit 510.
Here, FIG. 8 is a diagram illustrating an internal configuration example of the packet management data temporary storage unit 507. As shown in FIG. 8, the packet management data temporary storage unit 507 is provided with a processing state display unit 16 that stores the packet management data 12 and records the state of error correction processing for the packet storage information 14. The processing status display unit 16 can record the status of error correction processing for each packet storage information 14. Note that incomplete error correction is recorded as the initial value of the processing state display unit 16.

  Next, the error correction unit 508 performs error correction using the error correction code 15 for each packet storage information 14 included in the packet management data 12 input to the packet management data temporary storage unit 507. Then, error correction completion is written in the processing state display unit 16 (step ST72).

Independent of the operation of error correction section 508, packet reconfiguration control section 509 monitors processing status display section 16 and controls packet reconfiguration section 510 (step ST73). Here, if the processing status display unit 16 indicates completion of error correction, the packet reconfiguration unit 510 is instructed to reconstruct the packet. If the processing state display unit 16 does not indicate completion of error correction, the packet reconfiguration is temporarily performed. Instruct to stop. An instruction to resume packet reconstruction is issued when error correction is executed by the error correction unit 508 and completion of error correction is displayed on the processing status display unit 16.
Next, packet reconfiguration section 510 reconfigures the packet based on the packet storage information for which error correction has been completed and packet data 13 from memory reading section 506 in accordance with instructions from packet reconfiguration control section 509 (step ST74). . The memory area after the data block 11 is read is in a state where a new data block can be written.

  As described above, according to the first embodiment, since the error correction code 15 is added to the individual packet storage information 14 included in the packet management data 12, the packet storage information before the packet reconfiguration is configured. 14 can be corrected, and the packet buffer device 5 capable of reducing packet discard due to erroneous packet storage information 14 can be constructed.

  In the first embodiment, the description has been made on the assumption that the encoded data stored in the packet management data includes the original data (packet storage information) as it is. The encoding format may not include data as it is. That is, in the first embodiment, as shown in FIG. 9, the error correction code generation unit 502 generates an error correction code based on the packet storage information, and adds the error correction code to the packet storage information to manage the packet. Data is being generated. On the other hand, as shown in FIG. 10, the error correction code generation unit 502 generates packet storage information after error correction encoding based on the packet storage information, and uses the packet storage information after error correction encoding. Then, packet management data may be generated.

Embodiment 2. FIG.
FIG. 11 is a diagram showing the configuration of the packet buffer device 5 according to the second embodiment of the present invention. The packet buffer device 5 according to the second embodiment shown in FIG. 11 is obtained by adding an error detection code generation unit 511 and an error detection unit 512 to the packet buffer device 5 according to the first embodiment shown in FIG. Other configurations are the same, and the same reference numerals are given and description thereof is omitted.

The error detection code generation unit 511 generates an error detection code for each packet storage information from the packet storage information generation unit 501. The error detection code generated by the error detection code generation unit 511 is output to the memory writing unit 504.
Note that the memory writing unit 504 stores the data from the error detection code generation unit 511 in addition to the data from the packet storage information generation unit 501 and the error correction code generation unit 502 when creating the packet management data.

The error detection unit 512 detects packet storage information with an error using an error detection code included in the packet management data stored in the error detection code generation unit 511.
The error correction unit 508 corrects the error only for the packet storage information in which the error is detected by the error detection unit 512.

In order to further increase the error resistance of individual packet storage information stored in the packet management data, it is possible to use an error correction code having a high error correction capability, but it takes a lot of time for error correction. In general, when a Hamming code capable of 1-bit error correction is used, and when the data length is 15 bits and the coding rate is 11/15, one clock is required for error correction, but a differential cyclic code capable of error correction of multiple bits. When the data length is 21 bits and the coding rate is 11/21, 32 clocks are required for error correction. On the other hand, the time required for error detection is one clock for both 1-bit error detection using a parity bit and 2-bit error detection using a Hamming code.
Therefore, not only an error correction code but also an error detection code is added to the packet storage information, and error detection is performed before error correction. If no error has occurred in the packet storage information, error correction is not performed, and error correction is performed only on the packet storage information in which an error has occurred. Thereby, since processing delay can be reduced, it is possible to use an error correction code having high error correction capability.

Of the operations until the received packet is written in the memory 505, the operations of the error detection code generation unit 511 and the memory writing unit 504 are different from those in the first embodiment.
That is, the error detection code generation unit 511 generates an error detection code for each packet storage information generated by the packet storage information generation unit 501 and outputs the error detection code to the memory writing unit 504. Then, the memory writing unit 504 generates the packet storage information generated by the packet storage information generation unit 501 and the error correction code generation unit 502 for all packets stored in the packet data in the creation of the packet management data. In addition to the error correction code, the error detection code generated by the error detection code generation unit 511 is also stored.

  FIG. 12 is a diagram illustrating an internal configuration example of the packet management data 12. As shown in FIG. 12, the packet management data 12 stores packet storage information 14, an error correction code 15 of the packet storage information, and an error detection code 17 of the packet storage information 14 for each received packet. ing.

Next, the operation until the data block 11 shown in FIG. 4 is read from the memory 505, reconstructed as a packet, and output is described below.
When the packet management data 12 is stored in the packet management data temporary storage unit 507, the error detection unit 512 performs error detection on the packet storage information 14 using the error detection code 17, and displays the presence / absence of an error in the processing state display. This is displayed on the part 16. Here, the error correction unit 508 monitors the processing state display unit 16 independently of the operation of the error detection unit 512, and the packet storage information 14 at the place where the processing state display unit 16 records that there is an error. Error correction is performed using the correction code 15, and error correction completion is recorded in the processing state display unit 16.

Independent of the operations of the error detection unit 512 and the error correction unit 508, the packet reconfiguration control unit 509 refers to the processing state display unit 16, and indicates that the processing state display unit 16 indicates no error or error correction completion. If there is, the packet restructuring unit 510 is instructed to reconstruct the packet. On the other hand, when the processing state display unit 16 detects a location indicating an error, the packet reconfiguration unit 510 is instructed to temporarily stop packet reconfiguration. An instruction to resume packet reconfiguration is issued when error correction completion is displayed on the processing status display unit 16.
The packet reconfiguration unit 510 then reconfigures the packet based on the packet storage information 14 and the packet data 13 from the memory reading unit 506 in accordance with an instruction from the packet reconfiguration control unit 509.

  As described above, according to the second embodiment, since the error detection code 17 is added to the individual packet storage information 14 included in the packet management data 12, error correction of the packet storage information 14 is performed. Before, error detection can be performed. As a result, error correction can be performed only on the packet storage information 14 in which an error has occurred in the packet storage information 14 in the packet management data, and an increase in processing delay can be suppressed. Therefore, the error tolerance of the packet storage information 14 can be increased by using an error correction code having a high error correction capability.

  In the first and second embodiments, the case where the packet buffer device 5 is used as the buffer device has been described. However, the present invention is not limited to this, and can be similarly applied to a frame buffer device that temporarily stores frames. It is.

  Further, within the scope of the present invention, the invention of the present application can be freely combined with each embodiment, modified with any component in each embodiment, or omitted with any component in each embodiment. .

  1 packet transfer device, 2 packet transmission source, 3 packet transmission destination, 4 control device, 5 packet buffer device (buffer device), 11 data block, 12 packet management data (management data), 13 packet data (integrated data), 14 Packet storage information (storage information), 15 error correction code, 16 processing status display unit, 17 error detection code, 501 packet storage information generation unit (storage information generation unit), 502 error correction code generation unit, 503 memory control unit, 504 Memory writing unit, 505 memory, 506 memory reading unit, 507 packet management data temporary storage unit (management data temporary storage unit), 508 error correction unit, 509 packet reconfiguration control unit (reconfiguration control unit), 510 packet reconfiguration unit (Reconstruction unit) 511 Error detection code generation unit 512 Error detection unit.

Claims (2)

In a buffer device using a memory that performs burst transfer,
For each received data, a storage information generation unit that generates storage information of the data in the memory;
An error correction code generation unit that generates an error correction code for each piece of storage information generated by the storage information generation unit;
Management data including integrated data in which the data is collected to a size suitable for access to the memory, storage information generated by the storage information generation unit, and error correction code generated by the error correction code generation unit A memory writing unit for writing a data block in association with the memory into the memory;
A memory reading unit for reading out data blocks stored in the memory;
A management data temporary storage unit for storing management data included in the data block read by the memory reading unit;
An error correction unit for correcting an error in stored information using an error correction code included in the management data stored in the management data temporary storage unit;
Reconfiguration for reconfiguring the data based on the integrated data included in the data block read by the memory reading unit and the storage information included in the management data stored in the management data temporary storage unit And
A buffer device comprising: a reconstruction control unit that instructs the reconstruction unit to reconstruct the data after error correction of stored information is completed by the error correction unit. An error detection code generation unit that generates an error detection code for each piece of storage information generated by the storage information generation unit;
Using an error detection code generated by the error detection code generation unit, and an error detection unit for detecting an error in storage information included in the management data stored in the management data temporary storage unit,
The buffer device according to claim 1, wherein the error correction unit corrects an error with respect to storage information in which an error is detected by the error detection unit.

Images