JP2000121700A - アクセスを制限した回路テストにおいて刺激位置を選択するための方法及び装置 - Google Patents

アクセスを制限した回路テストにおいて刺激位置を選択するための方法及び装置

Info

Publication number
JP2000121700A
JP2000121700A JP11290335A JP29033599A JP2000121700A JP 2000121700 A JP2000121700 A JP 2000121700A JP 11290335 A JP11290335 A JP 11290335A JP 29033599 A JP29033599 A JP 29033599A JP 2000121700 A JP2000121700 A JP 2000121700A
Authority
JP
Japan
Prior art keywords
node
branch
test
equation
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11290335A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000121700A5 (enExample
Inventor
John E Mcdermid
ジョン・イー・マクダーミッド
Cherif Ahrikencheikh
チェリフ・アーリケンチェイク
Rodney A Browen
ロドニー・エイ・ブローウェン
William P Darbie
ウィリアム・ピー・ダービー
Kay C Lannen
ケイ・シー・ラネン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2000121700A publication Critical patent/JP2000121700A/ja
Publication of JP2000121700A5 publication Critical patent/JP2000121700A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Telephone Function (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP11290335A 1998-10-09 1999-10-12 アクセスを制限した回路テストにおいて刺激位置を選択するための方法及び装置 Pending JP2000121700A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US169597 1998-10-09
US09/169,597 US6266787B1 (en) 1998-10-09 1998-10-09 Method and apparatus for selecting stimulus locations during limited access circuit test

Publications (2)

Publication Number Publication Date
JP2000121700A true JP2000121700A (ja) 2000-04-28
JP2000121700A5 JP2000121700A5 (enExample) 2006-11-24

Family

ID=22616365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11290335A Pending JP2000121700A (ja) 1998-10-09 1999-10-12 アクセスを制限した回路テストにおいて刺激位置を選択するための方法及び装置

Country Status (4)

Country Link
US (1) US6266787B1 (enExample)
EP (1) EP0992804B1 (enExample)
JP (1) JP2000121700A (enExample)
DE (1) DE69923045T2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6968285B1 (en) 2003-04-09 2005-11-22 Hamid Adnan A Method and apparatus for scenario search based random generation of functional test suites
US7111198B2 (en) * 2003-06-12 2006-09-19 Inventec Corporation Multithread auto test method
US7779374B1 (en) 2006-09-29 2010-08-17 Breker Verification Systems, Inc. Generating self-checking test cases from reduced case analysis graphs
WO2014121138A2 (en) * 2013-01-31 2014-08-07 The Regents Of The University Of California Method and apparatus for solving an optimization problem using an analog circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012625A (en) * 1975-09-05 1977-03-15 Honeywell Information Systems, Inc. Non-logic printed wiring board test system
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
US5012180A (en) * 1988-05-17 1991-04-30 Zilog, Inc. System for testing internal nodes
JPH07113898B2 (ja) * 1989-05-09 1995-12-06 株式会社日立製作所 障害検出方式
US5323108A (en) * 1992-01-23 1994-06-21 Hewlett-Packard Company Method for generating functional tests for printed circuit boards based on pattern matching of models
US5808919A (en) 1993-11-23 1998-09-15 Hewlett-Packard Company Diagnostic system
US5530372A (en) * 1994-04-15 1996-06-25 Schlumberger Technologies, Inc. Method of probing a net of an IC at an optimal probe-point
US5521513A (en) * 1994-10-25 1996-05-28 Teradyne Inc Manufacturing defect analyzer
US5732209A (en) * 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
EP0794495A3 (en) * 1996-03-08 1998-07-22 Hewlett-Packard Company Automated analysis of a model-based diagnostic system
US5734661A (en) * 1996-09-20 1998-03-31 Micron Technology, Inc. Method and apparatus for providing external access to internal integrated circuit test circuits

Also Published As

Publication number Publication date
EP0992804A3 (en) 2002-12-18
EP0992804B1 (en) 2005-01-05
DE69923045T2 (de) 2005-12-01
US6266787B1 (en) 2001-07-24
DE69923045D1 (de) 2005-02-10
EP0992804A2 (en) 2000-04-12

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