JP2000121692A - Test device for semiconductor element - Google Patents

Test device for semiconductor element

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Publication number
JP2000121692A
JP2000121692A JP10292454A JP29245498A JP2000121692A JP 2000121692 A JP2000121692 A JP 2000121692A JP 10292454 A JP10292454 A JP 10292454A JP 29245498 A JP29245498 A JP 29245498A JP 2000121692 A JP2000121692 A JP 2000121692A
Authority
JP
Japan
Prior art keywords
semiconductor device
voltage
test
current source
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10292454A
Other languages
Japanese (ja)
Inventor
Yukito Ikeda
幸仁 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP10292454A priority Critical patent/JP2000121692A/en
Publication of JP2000121692A publication Critical patent/JP2000121692A/en
Withdrawn legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect deterioration status of heat resistance without removing a semiconductor element to be tested from a test device. SOLUTION: A very small constant current source 2 for always applying such a very small d.c. constant current IM that heat eneration is ignored to a semiconductor element 4 to be tested is connected to the element 4. Variable resistors 5 are respectively connected in series to the semiconductor elements 4 to be tested. An input terminal of a sample hold circuit 6 for sample holding the voltage VM2 of the semiconductor element 4 to be tested in response to a timing signal immediately after the end of application of the current IT is connected to both ends of each semiconductor element 4 including the variable resistors 5. The output terminal of the sample hold circuit 6 is connected to the input terminal of a comparator 7, the comparator 7 outputs when the voltage VM2 of the semiconductor element 4 is lower than the reference voltage Vref to turn on a thyristor 9, thereby causing a light emitting diode 10 to emit light.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えばPN接合を
有する半導体の構造上の耐性を評価する熱疲労試験を複
数の半導体素子に対して同時に実施できる半導体素子の
試験装置及び試験方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus and a test method capable of simultaneously performing a thermal fatigue test for evaluating a structural resistance of a semiconductor having a PN junction on a plurality of semiconductor devices. is there.

【0002】[0002]

【従来の技術】従来、PN接合を有する半導体素子の熱
疲労試験を行う試験装置は、図3に示すように、電流I
Tを供給する定電流源1とリレー回路3と複数の被試験
用半導体素子4が直列に接続され、リレー回路3をタイ
ミングコントローラ11で制御して、直列に複数接続さ
れた素子4に図4に示す間欠的な通電電流IFを印加し
て発熱させるように構成されている。
2. Description of the Related Art Conventionally, a test apparatus for performing a thermal fatigue test on a semiconductor device having a PN junction has a current I as shown in FIG.
A constant current source 1 for supplying T, a relay circuit 3, and a plurality of semiconductor devices under test 4 are connected in series, and the relay circuit 3 is controlled by a timing controller 11 to connect a plurality of serially connected devices 4 to FIG. Is generated by applying an intermittent current IF shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
試験装置は、予め定めた通電回数となった時に装置から
被試験用半導体素子4を取り外し、当該素子の熱抵抗を
測定することにより劣化診断を行なっているため、以下
の欠点があった。即ち、被試験用半導体素子4の劣化診
断は、予め定められた通電回数でのみ行われるため、試
験途中で発生した劣化が判定できず、各素子の劣化時期
を正確に把握するのが難しい。
However, the conventional test apparatus removes the semiconductor device under test 4 from the device when a predetermined number of times of energization has been performed, and measures the thermal resistance of the device to perform a deterioration diagnosis. Therefore, there are the following disadvantages. That is, since the deterioration diagnosis of the semiconductor device under test 4 is performed only at a predetermined number of times of energization, deterioration occurring during the test cannot be determined, and it is difficult to accurately grasp the deterioration time of each device.

【0004】また、熱抵抗を測定する度に素子を取り外
さなければならず、手間がかかると共に、取り付け時や
取り外し時の誤接続や取り付け時のストレス等により不
具合を生じ易いという問題があり、特に複数の素子を同
時に試験する場合には著しく手間がかかり、取り扱いに
注意を要していた。
In addition, the element must be removed every time the thermal resistance is measured, which is troublesome, and causes problems such as erroneous connection at the time of attachment and detachment, stress at the time of attachment, and the like. When testing a plurality of devices at the same time, it takes a lot of trouble and requires careful handling.

【0005】本発明は、上記課題に鑑みてなされ、その
目的は、同時に試験を行なっている複数の被試験用半導
体素子を装置から取り外すことなく、試験途中で熱抵抗
の劣化を判定でき、素子の劣化を正確に診断できる半導
体素子の試験装置を提供することである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to determine deterioration of thermal resistance during a test without removing a plurality of semiconductor devices under test simultaneously from the device. It is an object of the present invention to provide a semiconductor device test device capable of accurately diagnosing deterioration of a semiconductor device.

【0006】[0006]

【課題を解決するための手段】上述の課題を解決し、目
的を達成するために、本発明の半導体素子の試験装置
は、直列に接続された被試験用半導体素子に予め設定さ
れた電流を間欠的に通電することにより該素子の耐性を
同時に試験する半導体の試験装置において、前記素子に
対して、該素子を発熱させるのに十分な直流電流を間欠
的に通電させるための間欠電流源と、前記素子に対し
て、該素子の発熱を無視でき得る充分に微少な直流電流
を常時通電するための定電流源と、前記素子ごとに直列
に接続された可変抵抗と、前記可変抵抗を含む前記素子
の両端電圧を基準電圧と比較する比較回路を備え、前記
比較回路は、前記間欠電流源による通電直後の前記両端
電圧の大小を判定する。
In order to solve the above-mentioned problems and achieve the object, a semiconductor device test apparatus according to the present invention provides a semiconductor device under test connected in series with a preset current. In a semiconductor test apparatus for simultaneously testing the resistance of the element by intermittently supplying current, an intermittent current source for intermittently supplying a DC current sufficient to cause the element to generate heat with the element. A constant current source for constantly supplying a sufficiently small DC current to the element that can neglect the heat generation of the element, a variable resistor connected in series for each element, and the variable resistor. A comparison circuit that compares a voltage between both ends of the element with a reference voltage, wherein the comparison circuit determines the magnitude of the voltage between both ends immediately after energization by the intermittent current source.

【0007】また、好ましくは、前記間欠電流源はPN
接合を有する半導体素子の順方向に通電する。
[0007] Preferably, the intermittent current source is PN.
Electric current is supplied in the forward direction of the semiconductor element having the junction.

【0008】また、好ましくは、前記間欠電流源による
電流印加直後の前記素子の両端電圧が前記基準電圧を下
回った場合に該素子が劣化していると判定する判定回路
を更に備える。
Preferably, the apparatus further includes a determination circuit for determining that the element has deteriorated when a voltage across the element immediately after the application of the current by the intermittent current source falls below the reference voltage.

【0009】[0009]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて添付図面を参照して詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

【0010】図1は、本発明に係る実施形態の半導体試
験装置の回路ブロック図である。
FIG. 1 is a circuit block diagram of a semiconductor test apparatus according to an embodiment of the present invention.

【0011】以下では、被試験用半導体素子としてPN
接合ダイオードを用いた例を説明する。
In the following, PN is used as a semiconductor device under test.
An example using a junction diode will be described.

【0012】PN接合を有する半導体素子の熱疲労試験
における劣化診断は、熱抵抗によって実施される。この
熱抵抗は予め被試験用半導体素子のPN接合の順方向に
微少の直流定電流IMを流しておき、被試験用半導体素
子自体の電力損失により発熱させるために充分な電流を
所定時間印加し、この電流の印加前の被試験用半導体素
子のPN接合電圧VM1と印加終了直後のPN接合電圧V
M2の電圧差ΔVF=VM1−VM2から算出される。
Diagnosis of deterioration of a semiconductor device having a PN junction in a thermal fatigue test is performed by thermal resistance. For this thermal resistance, a small DC constant current IM is applied in advance in the forward direction of the PN junction of the semiconductor device under test, and a sufficient current is applied for a predetermined time to generate heat due to power loss of the semiconductor device under test itself. The PN junction voltage VM1 of the semiconductor device under test before application of this current and the PN junction voltage V
It is calculated from the voltage difference ΔVF of M2 = VM1-VM2.

【0013】図1において、4は被試験用半導体素子で
あり、複数の素子4を同時に試験できるように直列に接
続されると共に、被試験用半導体素子4を発熱させるた
めの定電流源1がリレー回路3を介して接続されてい
る。
In FIG. 1, reference numeral 4 denotes a semiconductor device under test, which is connected in series so that a plurality of devices 4 can be tested at the same time, and has a constant current source 1 for heating the semiconductor device 4 under test. It is connected via a relay circuit 3.

【0014】また、被試験用半導体素子4には、当該素
子の発熱が無視できる程度の微少な直流定電流IMを常
時通電させるための微少定電流源2が接続されており、
リレー回路3をタイミングコントローラ11で制御する
ことにより、被試験用半導体素子4に図2に示す電流I
Fが流れるようになっている。
The semiconductor device under test 4 is connected to a minute constant current source 2 for constantly supplying a minute DC constant current IM such that the heat generation of the device can be ignored.
By controlling the relay circuit 3 by the timing controller 11, the current I shown in FIG.
F is flowing.

【0015】被試験用半導体素子4には各々直列に可変
抵抗5が接続されており、夫々の抵抗値は、試験前に直
流定電流IMを流すことにより可変抵抗5を含む被試験
用半導体素子4に印加される電圧VM1を全素子について
同一になるように調整されている。
Variable resistances 5 are connected in series to the semiconductor element 4 to be tested, and the respective resistance values are adjusted by passing a DC constant current IM before the test. The voltage VM1 applied to 4 is adjusted to be the same for all elements.

【0016】また、被試験用半導体素子4を発熱させる
ためにタイミングコントローラ11は可変抵抗5を含む
各被試験用半導体素子4に通電させる電流ITをコント
ロールし、可変抵抗5を含む各被試験用半導体素子4の
両端には電流ITの通電終了直後にタイミング信号を受
けて被試験用半導体素子4の電圧VM2をサンプルホール
ドするためのサンプルホールド回路6の入力端子が接続
されている。
In addition, in order to cause the semiconductor device under test 4 to generate heat, the timing controller 11 controls a current IT supplied to each semiconductor device under test 4 including the variable resistor 5, and controls a current IT including the variable resistor 5. An input terminal of a sample and hold circuit 6 for receiving a timing signal and sampling and holding the voltage VM2 of the semiconductor element under test 4 immediately after the end of the supply of the current IT is connected to both ends of the semiconductor element 4.

【0017】更に、サンプルホールド回路6の出力端子
はコンパレータ7の入力端子に接続され、コンパレータ
7はサンプルホールドされた電圧VM2を電圧源8によっ
て与えられる基準電圧Vrefと比較する。電圧VM2は、
先に定めたVM1から熱抵抗判定値ΔVFLを減算すること
により算出される(VM1−ΔVFL)。コンパレータ7
は、被試験用半導体素子4の電圧VM2がこの基準電圧V
refを下回った場合に出力が発生し、サイリスタ9をオ
ンすることによって発光ダイオード10を発光させる。
これにより、試験装置から被試験用半導体素子4を取り
外すことなく、試験実施中に熱抵抗の劣化状況を検出で
きる。
Further, the output terminal of the sample and hold circuit 6 is connected to the input terminal of a comparator 7, and the comparator 7 compares the sampled and held voltage VM2 with a reference voltage Vref provided by a voltage source 8. The voltage VM2 is
It is calculated by subtracting the thermal resistance determination value ΔVFL from the previously determined VM1 (VM1−ΔVFL). Comparator 7
Means that the voltage VM2 of the semiconductor element 4 under test is equal to the reference voltage V
An output is generated when the voltage falls below ref, and the thyristor 9 is turned on to cause the light emitting diode 10 to emit light.
This makes it possible to detect the deterioration of the thermal resistance during the test without removing the semiconductor device under test 4 from the test apparatus.

【0018】尚、本発明は、その趣旨を逸脱しない範囲
で実施形態を修正又は変形したものに適用可能である。
The present invention can be applied to a modified or modified embodiment without departing from the spirit of the invention.

【0019】[0019]

【発明の効果】以上のように、本発明によれば、試験装
置から被試験用半導体素子を取り外すことなく、試験実
施中に熱抵抗の劣化状況を判定できるため、同時に複数
の被試験素子を実施する場合に、熱抵抗測定のための取
り外しの手間が不要であり、試験工数の効率が図れると
共に、劣化時期の正確な把握ができ、適切な診断を行う
ことができる。
As described above, according to the present invention, it is possible to determine the deterioration state of the thermal resistance during the test without removing the semiconductor device under test from the test apparatus. In the case of carrying out, it is not necessary to remove it for the measurement of thermal resistance, the efficiency of the test man-hour can be improved, the timing of deterioration can be accurately grasped, and an appropriate diagnosis can be performed.

【0020】[0020]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る実施形態の半導体素子の試験装置
の回路ブロック図である。
FIG. 1 is a circuit block diagram of a semiconductor device test apparatus according to an embodiment of the present invention.

【図2】本実施形態において被試験用半導体素子に通電
させる電流を示す図である。
FIG. 2 is a diagram showing a current applied to a semiconductor device under test in the present embodiment.

【図3】従来の半導体試験装置の回路ブロック図であ
る。
FIG. 3 is a circuit block diagram of a conventional semiconductor test apparatus.

【図4】従来において被試験用半導体素子に通電させる
電流を示す図である。
FIG. 4 is a diagram showing a current applied to a semiconductor device under test in the related art.

【符号の説明】[Explanation of symbols]

1 定電流源 2 微少定電流源 3 リレー回路 4 被試験用半導体素子 5 可変抵抗 6 サンプルホールド回路 7 コンパレータ 8 電圧源 9 サイリスタ 10 発光ダイオード 11 タイミングコントローラ REFERENCE SIGNS LIST 1 constant current source 2 minute constant current source 3 relay circuit 4 semiconductor device under test 5 variable resistor 6 sample and hold circuit 7 comparator 8 voltage source 9 thyristor 10 light emitting diode 11 timing controller

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 直列に接続された被試験用半導体素子に
予め設定された電流を間欠的に通電することにより該素
子の耐性を同時に試験する半導体素子の試験装置におい
て、 前記素子に対して、該素子を発熱させるのに十分な直流
電流を間欠的に通電させるための間欠電流源と、 前記素子に対して、該素子の発熱を無視でき得る充分に
微少な直流電流を常時通電するための定電流源と、 前記素子ごとに直列に接続された可変抵抗と、 前記可変抵抗を含む前記素子の両端電圧を基準電圧と比
較する比較回路を備え、 前記比較回路は、前記間欠電流源による通電直後の前記
両端電圧の大小を判定することを特徴とする半導体素子
の試験装置。
1. A semiconductor device test apparatus for intermittently applying a preset current to a series-connected semiconductor device under test to test the durability of the device, wherein the device has An intermittent current source for intermittently applying a direct current sufficient to cause the element to generate heat; and an intermittent current source for constantly applying a sufficiently small direct current to the element so that the heat generation of the element can be ignored. A constant current source; a variable resistor connected in series for each element; and a comparison circuit for comparing a voltage across the element including the variable resistance with a reference voltage, wherein the comparison circuit is energized by the intermittent current source. A test apparatus for a semiconductor device, which determines the magnitude of the voltage between both ends immediately after the test.
【請求項2】 前記間欠電流源はPN接合を有する半導
体素子の順方向に通電することを特徴とする請求項1に
記載の半導体素子の試験装置。
2. The semiconductor device test apparatus according to claim 1, wherein the intermittent current source supplies current in a forward direction of the semiconductor device having a PN junction.
【請求項3】 前記間欠電流源による電流印加直後の前
記素子の両端電圧が前記基準電圧を下回った場合に該素
子が劣化していると判定する判定回路を更に備えること
を特徴とする請求項1に記載の半導体素子の試験装置。
3. The apparatus according to claim 2, further comprising a determination circuit for determining that the element has deteriorated when a voltage across the element immediately after the application of the current by the intermittent current source falls below the reference voltage. 2. The apparatus for testing a semiconductor device according to claim 1.
JP10292454A 1998-10-14 1998-10-14 Test device for semiconductor element Withdrawn JP2000121692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10292454A JP2000121692A (en) 1998-10-14 1998-10-14 Test device for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10292454A JP2000121692A (en) 1998-10-14 1998-10-14 Test device for semiconductor element

Publications (1)

Publication Number Publication Date
JP2000121692A true JP2000121692A (en) 2000-04-28

Family

ID=17782019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10292454A Withdrawn JP2000121692A (en) 1998-10-14 1998-10-14 Test device for semiconductor element

Country Status (1)

Country Link
JP (1) JP2000121692A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU188241U1 (en) * 2018-09-25 2019-04-04 ФЕДЕРАЛЬНОЕ ГОСУДАРСТВЕННОЕ БЮДЖЕТНОЕ ОБРАЗОВАТЕЛЬНОЕ УЧРЕЖДЕНИЕ ВЫСШЕГО ОБРАЗОВАНИЯ "Брянский государственный технический университет" Device for monitoring the resistance of diodes to the rate of rise of reverse voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU188241U1 (en) * 2018-09-25 2019-04-04 ФЕДЕРАЛЬНОЕ ГОСУДАРСТВЕННОЕ БЮДЖЕТНОЕ ОБРАЗОВАТЕЛЬНОЕ УЧРЕЖДЕНИЕ ВЫСШЕГО ОБРАЗОВАНИЯ "Брянский государственный технический университет" Device for monitoring the resistance of diodes to the rate of rise of reverse voltage

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