JP2000116136A - Rectifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rectifier circuit which requires no wiring work for a gate terminal for driving a FET(field effect transistor) for rectification and a FET for circulation and thereby reduces the size of an equipment. SOLUTION: A rectifier circuit 30 has N-channel MOS-FETs 31, 32. These FETs are packaged in a surface mounting MP-3 type package. A D1 terminal 33 is connected with the drain terminal of the N-channel MOS-FET 32 and the gate terminal of the N-channel MOS-PET 31. A D2 terminal 34 is connected with the drain terminal of the N-channel MOS-PET 31 and the gate terminal of the N-channel MOS-FET 32. The source terminals of the N-channel MOS- FETs 31, 32 are both connected to an S1 terminal 35. This rectifier circuit 30 has a FET for rectification and a FET for circulation packaged in one package and requires no wiring work for a gate terminal for driving the FETs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectifier circuit for performing DC-DC conversion, and more particularly to an insulated gate field effect transistor (Metal) for rectification and commutation.
Oxide Semiconductor-Field Effect Transistor: MO
The present invention relates to a rectifier circuit using a field effect transistor such as an S-FET.

[0002]

2. Description of the Related Art Conventionally, in a DC-DC conversion system for converting a certain DC voltage into another DC voltage, an output DC voltage exceeding an input DC voltage can be obtained by using an insulation type converter. This insulated converter is configured by a combination of an inverter and a rectifier circuit that insulate the power supply side and the load side in a DC manner and convert DC into AC. In the isolated converter having such a configuration, a direct current is converted into an alternating current by an inverter, and after raising or lowering the voltage to a predetermined voltage, another DC voltage can be obtained by rectification.

FIG. 7 shows an outline of the configuration of a DC-DC converter circuit conventionally proposed using such an insulated converter. This isolated converter is configured by a combination of a transformer and a diode rectifier circuit. The DC - DC converter circuit includes a positive electrode (+) side of the DC power source 10 of the voltage value V _in is connected to the positive electrode side of the primary winding of the transformer 11. The negative side of the primary winding of the transformer 11 is connected to the drain terminal of the N-channel MOS-FET 12, and the source terminal is connected to the negative side (−) of the DC power supply 10. N-channel MOS-FET
The gate terminal of 12, the DC power supply 10 the voltage value V _in is connected to a control circuit 13 which is supplied by, so the gate of the on and off states of the N-channel MOS-FET 12 is performed by the control circuit 13 ing. The positive side of the secondary winding of the transformer 11 is connected to the anode side of the diode 14, and the cathode side is connected to the smoothing circuit 15. The negative side of the secondary winding of the transformer 11 is connected to the anode side of the diode 16, and the cathode side is connected to the cathode side of the diode 14.
5 is connected. The smoothing circuit 15 is also connected to the negative side of the secondary winding of the transformer 11, and can output the SG 17 and the output voltage V _out 18 which serve as the ground reference of the signal to the outside.

An N-channel MOS-
When the FET 12 is conducting, an exciting current flows on the primary winding side of the transformer 11 to store magnetic energy. At this time, a current flows through the secondary winding side of the transformer 11 through the diode 14 and the smoothing circuit 15 due to the induced voltage, and V _out 18 is generated. When the N-channel MOS-FET 12 is turned off by the control circuit 13, the magnetic energy stored in the primary winding of the transformer 11 is released in the opposite direction to the secondary winding. the induced voltage is generated, thereby a current flows through the diode 16 and the smoothing circuit 15, V _out 1
8 occurs. In this way, the switching by the control circuit 13 intermittently controls the power from the DC power supply 10 to obtain a predetermined load power, eliminates a loss in the control circuit, and achieves high efficiency. In addition,
The high frequency component generated by this switching is blocked by the smoothing circuit 15, only the DC component is averaged, and V _out
18 are obtained.

[0005] Requirements for a power supply include miniaturization and high efficiency. If the DC-DC converter circuit as described above is incorporated in a power supply device, the device can be downsized because there are components incorporating two diode elements having a rectification function, which has been achieved. However, if attention is paid to increasing the efficiency of the power supply device, the efficiency cannot be increased due to the loss due to the voltage drop of the diode. Therefore, as one of means for increasing the efficiency of the power supply, instead of such a conventional diode rectification method using a diode rectification circuit, an FET rectification circuit using N-channel MOS-FETs for rectification and circulation is used. There is an FET rectification method.

FIG. 8 shows an outline of the configuration of a DC-DC converter circuit using such a FET rectification method. However, the same parts as those of the DC-DC converter circuit using the diode rectification method shown in FIG. 7 are denoted by the same reference numerals, and only the parts different from the DC-DC converter circuit using the diode rectification method of FIG. The positive side of the secondary winding of the transformer 11 is connected to the smoothing circuit 15 and to the drain terminal of the N-channel MOS-FET 19. The negative side of the secondary winding of the transformer 11 is connected to the drain terminal of the N-channel MOS-FET 20. The source terminal of the N-channel MOS-FET 19 and the source terminal of the N-channel MOS-FET 20 are both connected to the smoothing circuit 15. Further N channel M
The gate terminal of the OS-FET 19 is an N-channel MOS-
It is connected to the drain terminal of FET20. The gate terminal of the N-channel MOS-FET 20 is
It is connected to the drain terminal of S-FET20. Here, the N-channel MOS-FET 19 is a recirculation FET,
The N-channel MOS-FET 20 becomes a rectifying FET.

An N-channel MOS-
When the FET 12 is conducting, an exciting current flows on the primary winding side of the transformer 11 to store magnetic energy. At this time, on the secondary winding side of the transformer 11, the gate of the N-channel MOS-FET 20 is turned on by the induced voltage, a current flows from the source terminal to the drain terminal by the parasitic diode, and V _out 18 is generated. Then, the N-channel MOS-FET 1 is controlled by the control circuit 13.
2 becomes non-conductive, the release of magnetic energy stored on the primary winding side of the transformer 11 generates an induced voltage in the opposite direction to the secondary winding side, thereby causing N-channel The gate of the MOS-FET 19 is turned on, a current flows from the source terminal to the drain terminal by the parasitic diode, and V _out 18 is generated.

Further, various proposals have been made to improve the efficiency of the DC-DC converter circuit using such FET rectification method. For example, Japanese Patent Application Laid-Open No. 5-252737, entitled "MOSFET Rectifier Circuit of Forward Converter" A technique is disclosed in which the rising and falling of the voltage waveform between the gate and the source of the rectifying and commutating FETs are made sharp to substantially synchronize with the switching operation of the MOS-FET 12 and reduce the loss.

[0009]

As described above, the requirements for the power supply device include miniaturization and high efficiency. However, in the DC-DC converter circuit using the FET rectification method as described above, the number of components increases because the N-channel MOS-FETs used for the rectification circuit are independent components. Therefore, FE
It has been difficult to reduce the size of the DC-DC converter circuit based on the T rectification method to the same level as or more than that of the conventional DC-DC converter circuit based on the diode rectification method. Furthermore, in order to electrically connect to the other drain terminal to both the rectifying and freewheeling FET drive gate terminals, it is necessary to connect these three-dimensionally crossing each other. In order to take into account a decrease in reliability due to cross wiring and a difficulty in manufacturing due to the above, a circuit is complicated, which further impedes miniaturization of the device. As described above, in the case of the diode rectification method, there has conventionally been a component having two built-in diode elements, and their connection does not need to intersect, so that mere packaging is sufficient.
However, in the case of the FET rectification method, there are components incorporating a plurality of FET elements. However, these connections are complicated for application to a DC-DC converter circuit, so mere packaging is not enough to reduce the size of the device. It couldn't contribute.

SUMMARY OF THE INVENTION An object of the present invention is to provide a rectifying circuit which eliminates the need for wiring a gate terminal for driving a rectifying FET and a circulating FET.

[0011]

According to the first aspect of the present invention, (a) a first terminal electrically connected to a positive electrode side of a secondary winding of a transformer; and (b) a first terminal of the secondary winding. A second terminal electrically connected to the negative electrode side; and (c) a first terminal connected to the drain terminal and a gate terminal connected to the second terminal connected to both ends of the secondary winding. A first field-effect transistor for rectifying a current flowing through the first terminal in accordance with the generated induced voltage; and (d) a second terminal connected to the drain terminal and having a gate terminal connected to the first terminal. (E) a second field-effect transistor connected to rectify the current flowing in the direction of the second terminal according to the induced voltage;
A third terminal connected to the source terminal of each of the first and second field-effect transistors and electrically connected to the ground potential;
And a rectifier circuit.

That is, according to the first aspect of the present invention, the rectifier circuit has first to third terminals, and the first terminal has the first terminal.
Connecting the drain terminal of the field-effect transistor to the gate terminal of the second field-effect transistor, connecting the drain terminal of the second field-effect transistor and the gate terminal of the first field-effect transistor to the second terminal, The third terminal is connected to the source terminals of the first and second field-effect transistors. Then, the first field-effect transistor rectifies the current flowing in the first current according to the induced voltage generated at both ends of the secondary winding of the transformer, and the second field-effect transistor has the second terminal The current that flows through is rectified.

According to a second aspect of the present invention, in the rectifier circuit of the first aspect, the first and second field-effect transistors are integrated and formed so as to have a common source region. .

That is, according to the second aspect of the present invention, the first and second field-effect transistors are integrated on one chip, their source regions are shared, and each drain terminal and each gate terminal are provided insulated. I did it.

According to a third aspect of the present invention, in the rectifier circuit according to the first or second aspect, the first and second field-effect transistors are sealed with a molding resin to form the first to third field-effect transistors.
Are connected to the corresponding external terminals.

That is, according to the third aspect of the present invention, the first and second field-effect transistors have their drain terminals and gate terminals connected to each other, and are sealed with a mold resin. Each terminal is connected to the external terminal of the package.

According to a fourth aspect of the present invention, in the rectifier circuit according to the first or second aspect, the first to third terminals accommodated in a package having a plurality of terminals each having a number corresponding to the current capacity. It is characterized by being connected to a terminal.

That is, in the invention according to claim 4, the package is housed in a package having a plurality of terminals, and the first to third terminals are connected to external terminals of the number of packages corresponding to the current capacity. .

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of the configuration of a DC-DC converter circuit using a rectifier circuit according to an embodiment of the present invention. However, the same parts as those in the configuration of the conventional DC-DC converter circuit based on the FET rectification method shown in FIG. The DC - DC converter circuit includes a positive electrode (+) side of the DC power source 10 of the voltage value V _in is connected to the positive electrode side of the primary winding of the transformer 11. The negative side of the primary winding of the transformer 11 is an N-channel MOS-
The source terminal is connected to the drain terminal of the FET 12, and the source terminal is connected to the negative (−) side of the DC power supply 10. The gate terminal of the N-channel MOS-FET 12 is connected to the DC power supply 1
0 are connected to the control circuit 13 to which the voltage value V _in is supplied by, N-channel M by the control circuit 13
The gate of the OS-FET 12 is turned on and off. Hereinafter, this N-channel MOS-FET 1
2 is called a main switch.

The positive side of the secondary winding of the transformer 11 is connected to the smoothing circuit 15 and to the terminal D1 of the rectifier circuit 30. The negative side of the secondary winding of the transformer 11 is connected to the D2 terminal of the rectifier circuit 30. Rectifier circuit 3
The S1 terminal of 0 is connected to the smoothing circuit 15. The smoothing circuit 15 is also connected to the negative side of the secondary winding of the transformer 11, and externally provides a signal ground reference SG 17 and an output voltage V
_out 18 can be output.

FIG. 2 shows an outline of the configuration of the rectifier circuit 30 in the present embodiment. This rectifier circuit has N-channel MOS-FETs 31 and 32, and these FETs are packaged in a conventional MP-3 type package for surface mounting. The rectifier circuit 30 includes two connection terminals, a D1 terminal 33 and a D2 terminal 34, which are drain terminals, and an S1 terminal 35, which is one source terminal. D1 terminal 33 has
The drain terminal of the N-channel MOS-FET 32 and the gate terminal of the N-channel MOS-FET 31 are connected. The D2 terminal 34 has an N-channel MOS-FET 31
And the gate terminal of the N-channel MOS-FET 32 are connected. N-channel MOS-FE
The source terminals of T31 and T32 are connected to the S1 terminal 35, respectively. The N-channel MOS-FET 32 is a freewheeling FET, and the N-channel MOS-FET 31 is a rectifying FE.
T. As described above, the rectifying circuit 30 packages the rectifying FET and the recirculation FET into one, and performs the wiring as described above, thereby eliminating the need for the FET drive gate terminal wiring work.

The freewheeling FET and the rectifying FET are both connected so that current flows in the opposite direction, not in the direction from the drain to the source. This is because a parasitic diode exists between the drain and the source of these FETs, so that a current flows in the same direction as the diode. The N-channel MOS-FET 31 is connected to the negative side of the transformer 11 so that the rectifying FET conducts when the main switch 12 on the primary winding side of the transformer 11 conducts.

In the DC-DC converter circuit of this embodiment having such a rectifier circuit 30, when the control circuit 13 turns on the main switch 12, an exciting current flows through the primary winding of the transformer 11. , Stored magnetic energy. At this time, the induced voltage of the secondary winding of the transformer 11 causes the MOS-FE
The gate of T31 is turned on, a current flows from the source terminal to the drain terminal by the parasitic diode, and V _out 18 is generated. The main switch 1 is controlled by the control circuit 13.
When 2 becomes non-conductive, the release of magnetic energy stored on the primary winding side of the transformer 11 generates an induced voltage in the opposite direction to the secondary winding side. Thereby on the gate of N-channel MOS-FET 32 of the rectifier circuit 30, a current flows to the drain terminal from the source terminal by its parasitic diode, V _{ou t} 18 Te occurs.
By the switching by the control circuit 13, the power from the DC power supply 10 is intermittently controlled to obtain a predetermined load power, and the loss in the control circuit is eliminated to improve the efficiency. The high frequency component generated by this switching is blocked by the smoothing circuit 15, and only the DC component is averaged to obtain V _out 18.

As described above, in the FET rectifier circuit according to the present embodiment, the N-channel MOS-FET 32 in the circuit is a free-wheeling FET and the N-channel MOS-FET 31 is a rectifying FET.
It operates as a self-winding drive type synchronous rectification system.

FIG. 3 shows an image of a rectifier circuit in this embodiment packaged in an MP-3 type package. The MP-3 type package 40 is composed of two rectifying FETs and a circulating FE each formed into a chip.
T is wired as shown in FIG. 2 and is sealed in a substantially rectangular parallelepiped shape with a mold resin as an insulator. At the time of encapsulation, three metal terminals D1 terminal 33, D2 terminal 34, and S1 terminal 3 for transmitting and receiving the internal electric signal to and from the outside.
Part 5 is also sealed in the mold resin, and the remaining part protrudes outside from the side of the package in front of the drawing. Further, a part of the S terminal 41 electrically connected to the S1 terminal 35 in the package 40 is also sealed, and the remaining part protrudes from the side of the package at the back of the drawing. Such an MP-3 type package 40 includes:
D1 terminals 33 and D2 are surface-mounted on the printer board.
The terminal 34 and the S terminal 41 are electrically connected to the corresponding wiring on the substrate by solder or the like.

As shown in FIG. 2, the MP-3 type package 40 includes a rectifying FET 31 and a circulating FET 32 in the rectifying circuit 30, and each source terminal (S) is a metal terminal S1 terminal 35. Is electrically connected to The drain terminal of the rectifying FET 31 and the gate terminal of the circulating FET 32 are metal terminals D1
It is electrically connected to the terminal 33. Rectifier FET
The gate terminal 31 and the drain terminal of the reflux FET 32 are electrically connected to a D2 terminal 34 which is a metal terminal. In this way, the intersection between the drain terminal and the source terminal of each other required for connection of the rectifying FET and the freewheeling FET is performed inside the package.

As described above, the rectifier circuit according to the present embodiment employs the drains of the FETs required for connecting the rectifying FET and the free-wheeling FET required in the conventional FET rectifying method on the printed circuit board. Cross connection between the terminal and the source terminal can be made unnecessary, and simplification of wiring on a printed circuit board and improvement in mounting efficiency can be achieved.

First Modified Example

Although the rectifier circuit in this embodiment is packaged in an MP-3 type package, a conventional SOP is used.
It can also be packaged in a -8 type package.
In addition, depending on the application, it can be connected to a plurality of terminals depending on the current capacity flowing through each terminal.

FIG. 4 shows an image of a rectifier circuit packaged in an SOP-8 type package according to the first modification. SOP-8 type package 42
As shown in FIG. 2, two rectifying FETs and recirculating FETs, each of which is formed into a chip, are wired as shown in FIG. 2, and are sealed in a substantially rectangular parallelepiped shape with a mold resin which is an insulator. At the time of encapsulation, a part of the eight metal terminals for transmitting and receiving the internal electric signal to and from the outside is encapsulated in the mold resin, and the remaining part protrudes outside from the side of the package in front of and behind the drawing. ing. Here, in terms of current capacity, the four terminals on the package side on the rear side of the drawing are S1 terminals 43, and the two terminals on the package side on the front side of the drawing are D1 terminals 44 and D2 terminals 45, respectively. Such S
The OP-8 type package 42 is mounted on a printer board, and includes a D1 terminal 44, a D2 terminal 45, and an S terminal 43.
Are electrically connected to the corresponding wiring on the substrate by solder or the like. 4 terminals of S1 terminal 43, 4 terminals of D1 terminal
The four terminals D4 and the two terminals D2 45 are connected to wirings having the same potential.

The inside of the SOP-8 type package 42 is shown in FIG.
Rectifying FET 31 in the rectifying circuit 30 as shown in FIG.
And a reflux FET 32, and each source terminal (S) is electrically connected to four S1 terminals 43 which are metal terminals. The drain terminal of the rectifying FET 31 and the gate terminal of the circulating FET 32 are electrically connected to two D1 terminals 44 which are metal terminals. The gate terminal of the rectifying FET 31 and the circulating FET 3
2 are two D2 terminals 4 which are metal terminals.
5 is electrically connected. Thus, the rectifying FET
The intersection of the drain terminal and the source terminal of each other required for connection of the freewheeling FET is performed inside the package.

Second Modified Example

In the rectifier circuit of the present embodiment, the FET elements each formed into a chip are packaged in an MP-3 type package. It can also be packaged in an MP-3 type package.

FIG. 5 shows an image of a rectifier circuit according to the present embodiment, which is packaged in an MP-3 type package according to a second modification. However, the same parts as those of the MP-3 type package in the present embodiment shown in FIG. The MP-3 type package 40 includes a rectifying FET 31 and a circulating FE.
The FET chip 46 in which T32 is integrated into one chip is wired as shown in FIG. 2, and is sealed in a substantially rectangular parallelepiped shape with a mold resin as an insulator.

The inside of the MP-3 type package 40 includes an FET.
A chip 46 is provided, the source region is shared, and the drain and gate regions are insulated from each other by an insulating region 47. FET chip 4
The source region No. 6 is electrically connected to the S1 terminal 35 which is a metal terminal. The drain region 48 of the rectifying FET 31 and the gate region 49 of the freewheeling FET 32 are electrically connected to a D1 terminal 33 which is a metal terminal.
Further, the gate region 50 of the rectifying FET 31 and the F
The drain region 51 of the ET 32 is electrically connected to the D2 terminal 34 which is a metal terminal. Thus, the rectifying F
The intersection of the drain terminal and the source terminal of each other required for connection of the ET and the freewheeling FET is performed inside the package.

Third Modified Example

The rectifier circuit according to the second modification has an MP-
Although it was packaged in a 3 type package, the conventional S
It can also be packaged in an OP-8 type package. In addition, depending on the application, it can be connected to a plurality of terminals depending on the current capacity flowing through each terminal.

FIG. 6 shows an image of a rectifier circuit packaged in an SOP-8 type package according to the third modification. However, the same parts as those of the SOP-8 type package in the first modified example shown in FIG. The SOP-8 type package 42 includes a rectifying FET 31 and a circulating FET 32.
2 is wired as shown in FIG. 2 and sealed in a substantially rectangular parallelepiped shape with a mold resin as an insulator.

The inside of the SOP-8 type package 42 is FE
A T chip 46 is provided. The source region is shared, and the drain and gate regions are insulated from each other by an insulating region 47. The source region of the FETI chip 46 is electrically connected to four S1 terminals 43 which are metal terminals. Rectifying FET 31
Drain region 48 and the gate region 49 of the reflux FET 32 are electrically connected to two D1 terminals 44 which are metal terminals. The gate region 50 of the rectifying FET 31 and the drain region 51 of the freewheeling FET 32 are electrically connected to two D2 terminals 45 which are metal terminals. In this way, the intersection between the drain terminal and the source terminal of each other required for connection of the rectifying FET and the freewheeling FET is performed inside the package.

In the present embodiment and the first to third modifications, the description has been made assuming that the device is packaged in an MP-3 type package or an SOP-8 type package. However, the present invention is not limited to this. In order to eliminate the need for cross-connecting work, it is sufficient that the package is packaged together with the rectifying FET and the recirculating FET, and when packaged in a package having a plurality of terminals, the package is determined according to the current capacity of the drain and source terminals. Can be connected to a plurality of terminals.

[0043]

As described above, according to the present invention, the first to third terminals of the rectifier circuit formed by cross-connecting the drain terminal and the gate terminal of the rectifying FET and the recirculating FET are connected. Since it can be directly connected to a transformer, the cross connection between the drain terminal and the source terminal of each FET, which was required in the past, is not required, and the wiring on the printed circuit board can be simplified and the mounting efficiency can be improved. become able to. Further, since noise generated in the signal line can be avoided, reliability is improved.

Further, according to the second aspect of the present invention, each F
By integrating ET and sharing the source area,
It is possible to reduce the size and simplify the wiring.

According to the third aspect of the present invention,
Like the MP-3 type package, it can be applied to a conventional package for surface mounting and having a large current capacity, and can contribute to simplification of wiring on a printed circuit board and improvement of mounting efficiency.

Further, according to the present invention, since the current capacity varies depending on the application field of the rectifier circuit, the current capacity is accommodated in a package having four or more terminals, and the number of wires corresponding to the current capacity is reduced. By connecting to the terminal, the possibility of application to various power supply devices can be expanded.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram illustrating an outline of a configuration of a DC-DC converter circuit using a rectifier circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram illustrating a configuration of a rectifier circuit in the present embodiment.

FIG. 3 is an image diagram schematically illustrating a configuration of a rectifier circuit according to the present embodiment packaged in an MP-3 type package.

FIG. 4 is an image diagram schematically illustrating a configuration of a rectifier circuit according to the present embodiment packaged in an SOP-8 type package according to a first modification;

FIG. 5 is an image diagram schematically illustrating a configuration of a rectifier circuit packaged in an MP-3 type package according to a second modified example.

FIG. 6 is an image diagram schematically showing a configuration of a rectifier circuit packaged in an SOP-8 type package in a third modified example.

FIG. 7 is a circuit configuration diagram showing an outline of a configuration of a DC-DC converter circuit using a diode rectification method conventionally proposed.

FIG. 8 is a circuit diagram showing an outline of a configuration of a DC-DC converter circuit based on the FET rectification method conventionally proposed.

[Description of Signs] 10 DC power supply (V _in ) 11 Transformer 12 N-channel MOS-FET (main switch) 13 Control circuit 15 Smoothing circuit 17 SG 18 Output voltage (V _out ) 30 Rectifier circuit 31 N-channel MOS-FET (Rectifier) 32) N-channel MOS-FET (recirculation FET) 33 D1 terminal 34 D2 terminal 35 S1 terminal

Claims (4)

[Claims] A first terminal electrically connected to a positive electrode side of a secondary winding of the transformer; a second terminal electrically connected to a negative electrode side of the secondary winding; The first terminal is connected to its drain terminal and its gate terminal is connected to this second terminal to rectify the current flowing through the first terminal according to the induced voltage generated at both ends of the secondary winding. A first field-effect transistor, wherein the second terminal and the drain terminal thereof are connected and the gate terminal thereof is connected to the first terminal, and the current flowing in the direction of the second terminal according to the induced voltage is supplied to the first field-effect transistor. A second field-effect transistor for rectification; and a third terminal connected to a source terminal of each of the first and second field-effect transistors and electrically connected to a ground potential. Rectifier circuit. 2. The rectifier circuit according to claim 1, wherein said first and second field-effect transistors are integrated and formed so as to have a common source region. 3. The device according to claim 1, wherein the first and second field effect transistors are sealed with a molding resin, and the first to third terminals are connected to corresponding external terminals, respectively. Item 2. A rectifier circuit according to Item 2. 4. The device according to claim 1, wherein said first to third terminals are housed in a package having a plurality of terminals, and each of said first to third terminals is connected to a number of terminals corresponding to a current capacity. Rectifier circuit as described.