JP2000114531A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which prevents electrostatic breakdown, with no significant change in a manufacturing process. SOLUTION: A substrate comprising a slice line 150 and wirings 100 and 120 provided in two, upper and lower, layers on the substrate are provided, and a process where the substrate is sliced to a specified size according to the slice line 150 is provided. Here, in an area which is outside of the slice line 150 and not going to be a semiconductor device, a common wiring 190 which electrically connects the wirings 100 and 120 is provided, and by removing the common wiring 190 in a slice process, the electrical connection of the wirings 100 and 120 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for forming a panel of a reading section or a display section in an apparatus for processing an image such as an X-ray sensor, an optical sensor, a liquid crystal display, and a plasma display. About.

[0002]

2. Description of the Related Art In recent years, in medical equipment, a diagnosis result is digitally output in accordance with a demand for improvement of diagnosis speed, accuracy of diagnosis, and the like. I.
Are being digitized from an early stage.

[0003] In radiography, a technique has been established in which a film image taken by a film scanner is read by a film scanner and digitally processed. In recent years, area sensors that directly read X-rays and perform digital processing have been remarkably developed and commercialized with the aim of further speeding up.

FIG. 6 shows a plan view of a detector portion of an X-ray area sensor before being cut out from a substrate by slicing. In the figure, 601 is a gate wiring made of Cr or the like,
Reference numeral 602 denotes a bias line made of Al or the like, and 603 denotes a signal line made of Al. The signal line 603 also serves as a lead portion for connecting to the outside.

Further, 604 is a lead portion made of Al or the like for connecting the gate line 601 to the outside, 605 is a lead portion made of Al for connecting the bias line 602 to the outside, and 660 to 663 are made of Cr or the like. Lower wiring and A
1 and the like, an N-type μc-Si layer, an a-Si: H layer,
An SiN layer is provided.

Reference numeral 680 denotes a sensor unit including a photodiode for detecting light or a capacitor sandwiching a semiconductor, and 670 denotes a TFT unit. The sensor unit 680 held under a constant bias by the bias line 602 can generate a charge corresponding to the amount of incident light and accumulate it in a capacitor (not shown) provided therein.

The switching of the TFT 670 is performed by switching the potential of the gate line 601, and the signal line 60 is switched.
The electric charge is stored in the storage device 3, and the potential generated by the storage is read by an external IC or the like, whereby the image is read as an analog signal, and is converted into a digital signal by digitization.

FIG. 7 is a diagram for explaining a pattern forming process of the sensor 680, and is represented by a portion corresponding to the upper right portion of FIG. FIG. 7A shows a patterning step of patterning a gate wiring made of Cr or the like,
(B) is a patterning step of patterning a contact hole after forming an a-Si: H film, (c) is a patterning step of patterning a bias line made of Al or the like, and (d) is a patterning step of a signal line made of Al or the like. A patterning step, (e) shows isolation for separating each element and wiring, a patterning step performed after SiN film formation, and (f) shows a slicing step for sizing the panel to a predetermined size.

First, a film of Cr or the like serving as a lower electrode layer is deposited on a transparent glass substrate by a sputtering method or the like so as to have a constant thickness, and then subjected to resist coating, exposure, development, and etching steps, as shown in FIG. To form a simple pattern. In the figure, 700 is a gate wiring, 701 and 702 are bias routing lines, 703 is a lower electrode of the sensor, and 750 is a slice line. All the patterns are electrically insulated from each other.

[0010] Next, SiN, a
After forming three layers of -Si: H and N-type μc-Si, a contact hole as shown in FIG. 7B is formed through resist coating, exposure, development, and etching steps. In the figure, 710 is a portion where three layers are left, and 711 to 71
6 is a portion from which three layers have been removed by the etching process.
712 to 716 are portions called contact holes.

Subsequently, after a low-resistance metal thin film made of Al or the like is formed thereon by a sputtering method or the like,
Similarly, through the resist coating-etching process, FIG.
An Al wiring portion as shown in FIG. In the figure, 720
Is a bias line, 721 is a part for a gate line lead-out part, 722 is a part for a signal line, and 723 and 724 are parts for a bias line lead-out part.

The upper Al electrode and the lower Cr electrode are connected through the contact holes 712 to 716, and further, the gate line portions (700 and 721) and the bias line portions (720 and 701 and 723, 702 and 724). , The signal lines and the sensor lower electrode portions (722 and 703) are also electrically connected to each other via N-type μc-Si.

Next, through the same resist coating-etching steps, the other than the bias lines as shown in FIG.
l wiring portion, and using the same resist image
The c-Si layer is removed by etching. In the drawing, 731 is a gate line lead-out portion, 732 is a signal line and a signal line lead-out portion, 7
Reference numerals 33 and 734 denote bias line drawing portions, and reference numeral 735 denotes a drain electrode of the TFT. The signal line 732 also serves as a source electrode of the TFT.

At this time, since the upper electrode 736 of the sensor is covered with the resist, all three layers remain, and the other part 710 has only two layers of SiN and a-Si: H. The bias line 720 and the sensor upper electrode 736 are electrically connected. N-type μc-
When the Si layer is removed by etching, the gate line portion (70
0 and 731), bias line portions (736, 720 and 701)
And 733, 702 and 734), the signal line portion (732), and the sensor lower electrode portion (703 and 735) are electrically insulated from each other.

Subsequently, the elements are separated from each other through the same resist coating and etching steps, and a film of SiN for passivation is formed on the entire surface by a step such as a CVD step. A window for electrical connection is opened to form a pattern as shown in FIG. In the figure, 736 is as described in the previous step,
This is the portion where three layers remain. Reference numerals 741 to 744 denote three layers remaining under the Al electrode, and a part protruding from the wiring is a part left only by two layers.

Reference numerals 751 to 754 denote windows of passivation SiN. At this time, the gate line portions (700 and 731), the bias line portions (736, 720, 701 and 733, 702 and 734), and the signal line portion (73
2) The electrical insulation relationship between the sensor lower electrode portions (703 and 735) does not change.

Finally, slicing is performed along the slice line 750 (the slice line 750 is not actually formed into a pattern but is virtually set based on an alignment mark), and FIG. f)
Finish to the required size as shown.

[0018]

However, in the method of manufacturing a semiconductor device shown in the above prior art, FIG.
In the steps after the N-type .mu.c-Si etching step shown in FIG. This is because a potential difference is generated between the gate line portion, the bias line portion, and the signal line portion due to the charging of the substrate in the air knife in the wet etching process or the dry etching process, and the potential difference exceeds a certain allowable value. This is because a discharge occurs between the upper and lower wirings of the cross portion when the electric discharge occurs.

If a discharge occurs between the upper and lower wirings of the cross portion as described above, the yield of the semiconductor device may be reduced. Therefore, a manufacturing process for preventing the discharge is required.

(Object of the Invention) It is an object of the present invention to provide a method for preventing electrostatic breakdown during the manufacture of a semiconductor device without largely changing the manufacturing process of the semiconductor device.

[0021]

According to the present invention, a lower wiring pattern and an upper wiring pattern and a semiconductor element which are vertically arranged on a substrate via an insulating layer are formed, and the substrate is cut into a predetermined size by slicing. In a method of manufacturing a semiconductor device including a lower layer wiring and an upper layer wiring arranged above and below via the insulating layer and the semiconductor element, the lower layer wiring is formed in a region of the substrate separated from the semiconductor device by the slice. Alternatively, a common wiring connecting the leading wiring and the upper wiring or the leading wiring from here is formed in advance, and the lower wiring or the leading wiring and the upper wiring or the leading wiring is separated by separating the common wiring by the slice. It is characterized in that the electrical connection with the lead-out line from now on is eliminated.

A plurality of pairs of a photoelectric conversion element and a thin film transistor connected to the photoelectric conversion element are arranged, a gate wiring connected to the thin film transistor, a bias wiring for driving the photoelectric conversion element, and A semiconductor device including a signal wiring connected to the thin film transistor for outputting a signal from a photoelectric conversion element; a first step of forming the gate wiring on a substrate; and forming an insulating layer after the first step. A second step of forming a contact hole in the insulating layer, a third step of forming the bias wiring after the second step, and a fourth step of forming the signal wiring after the third step. In the method of manufacturing a semiconductor device formed by the fifth step of separating the element and the wiring and the sixth step of slicing the substrate to a predetermined size, the fifth step is completed. The gate wiring, the bias wiring, and the signal wiring are electrically connected to each other, and the electrical connection between the gate wiring, the bias wiring, and the signal wiring is eliminated in the sixth step. It is characterized by.

(Operation) When selecting a semiconductor device such as an area sensor having two upper and lower wiring layers, the upper and lower wiring lines are electrically connected in an area outside the slice line until the substrate is sliced to a prescribed size. In this case, the upper and lower wirings are separated by slicing.

[0024]

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 shows a preferred embodiment of the present invention, and shows a plan view before slicing a substrate in manufacturing a sensor panel. FIG. 2 is a diagram showing a process of forming the panel pattern shown in FIG. In the figure, reference numeral 180 denotes an upper electrode of a sensor unit including a photodiode or a capacitor for detecting light, and 170 denotes a TFT unit serving as a switching element connected to the sensor unit.

Reference numeral 100 denotes a lower layer gate wiring made of Cr or the like, and a common wiring 190 is provided through a lead portion 131, a contact hole portion 112, and a contact portion 191.
Is electrically connected to Note that the common wiring 190 is
The same material as the lower gate wiring is used.

Reference numeral 120 denotes an upper bias line made of Al or the like, which is connected to the bias routing line 101 via the contact hole 115. The bias routing lines 101 and 102 are
3, 114, the lead portions 133, 134, and the contact portions 193, 194 are connected to the common wiring 190.

Further, reference numeral 132 denotes a signal line made of Al in the upper layer and also serves as a lead portion for connecting to the outside. The signal line 132 is also electrically connected to the lower common wiring 190 via the contact portion 192. 131 is a lead portion made of Al or the like in the upper layer for connecting the gate wiring 100 to the outside, 133 is a lead portion made of Al in the upper layer for connecting the bias line 120 to the outside, 10
Reference numerals 1 and 102 denote bias routing lines made of lower Cr or the like.

That is, the gate wiring 100, the bias line 120, the signal line 132, the bias routing lines 101,
02, contact hole portions 112 to 115,
Leader 131, 133, 134, contact 19
The common wiring 190 is connected through 1 to 194.
The lead portions 131, 133, and 134 and the contact portions 191 to 194 are made of upper Al.

Reference numeral 150 denotes a slice line for slicing, and reference numerals 160 to 163 denote cross portions between the lower wiring and the upper wiring. In these cross portions, an N-type μc-line is provided between the upper wiring and the lower wiring. Si layer, a-Si: H
Layer and a SiN layer.

As described above, all the driving wirings (gate lines, bias lines, signal lines, and bias lines) shown in FIG. 1 are maintained at substantially the same potential until this process.
Therefore, the potential difference between the upper and lower wirings particularly at the cross portions 160 to 163 is maintained at almost 0V. Therefore, by connecting the driving external lines of all the sensors to the common wiring 190 on the substrate before slicing, the potential differences at all the cross portions in the panel can be maintained at almost 0V.

Next, a process of forming the panel pattern will be described with reference to FIG. The symbols in the figure are:
The portion corresponding to the sensor in the upper right portion of FIG. 1 is represented.

FIG. 2A is a step of patterning a gate wiring made of Cr or the like, and FIG. 2B is a step of patterning SiN, a-Si: H,
Patterning a contact hole after forming an N-type film μc-Si; (c) a patterning step of a bias line made of Al or the like; (d) a patterning step of a signal line made of Al or the like; An isolation step for separating the wirings, and (f) shows a slicing step for making the panel a predetermined size.

In the process of forming a panel pattern, first, a film of Cr or the like serving as a lower electrode layer is deposited on a transparent glass substrate or the like to a constant thickness by a sputtering method or the like, followed by resist coating, exposure, development, and etching steps. FIG.
A pattern as shown in FIG. In the figure, 200
Is a gate wiring, 201 and 202 are bias routing lines,
203 is a lower electrode of the sensor, 290 is a common wiring in the present invention, and 250 is a slice line. At this stage, all patterns are electrically isolated from each other.

Next, SiN, a-
After forming three layers of Si: H, N-type μc-Si,
Through a resist coating, exposure, development, and etching steps, a contact hole as shown in FIG. 2B is formed. In the figure, 210 is a portion where three layers of SiN, a-Si: H and N-type μc-Si are left, 211 to 216 are portions where the three layers are removed by an etching process, and 212 to 216 are contact holes. It is the part called.

Next, after a low-resistance metal thin film made of Al or the like is formed by a sputtering method or the like, an Al wiring portion as shown in FIG. 2C is formed through the same resist coating and etching steps. 220 is a bias line, 22
Reference numeral 1 denotes a portion where a gate line lead-out portion is largely left in an island shape; 222 denotes a portion where a signal line is largely left in an island shape;
Reference numerals 23 and 224 denote portions where the bias line lead portions are largely left in the form of islands, and reference numerals 292 to 295 denote contact portions between the lower common wiring and the respective upper lead lines.

The upper Al electrode and the lower Cr electrode are connected to each other through the contact holes 212 to 216. Further, the gate line portions (200 and 221), the bias line portions (220 and 201 and 223, 202 and 224), The signal line portion (222) is also electrically connected to each other via the N-type μc-Si and the common wiring.

Next, through the same steps of resist application and etching, A and B other than the bias line as shown in FIG.
l wiring portion, and using the same resist image
The c-Si layer is removed by etching. 231 is a gate line lead-out part, 232 is a signal line and a signal line lead-out part, 233
Reference numeral 234 denotes a bias line drawing portion, and 235 denotes a drain electrode of the TFT. The signal line 232 also serves as a source electrode of the TFT.

At the time of etching the N-type μc-Si layer, since the upper electrode 236 of the sensor is covered with a resist, all three layers of SiN, a-Si: H, and N-type μc-Si remain. Other parts 210 are SiN and a-S
Only two layers of i: H remain. Bias line 220 and N
It is electrically connected to the sensor upper electrode 236 made of the type μc-Si.

When the N-type μc-Si layer is removed by etching, the gate line portions (200 and 231), the bias line portions (236, 220, 201 and 233, 202 and 23)
4), the electrical connection relationship between the signal line portions (232) via the N-type μc-Si layer is canceled, but, unlike the related art, the electrical connection is maintained by the common wiring 290. However, in the case of this panel, the sensor lower electrode portion (2
03 and 235) are not connected to the common wiring 190, so that the electrical connection relationship via the common wiring is eliminated.

Next, the elements are separated from each other through the same resist coating-etching process, SiN for passivation is formed on the entire surface by a method such as CVD, and the lead wire portion is again subjected to the resist coating-etching process. A connection window is opened to form a pattern as shown in FIG.

In the figure, reference numerals 241 to 244 denote three layers of SiN, a-Si: H, and N-type μc-Si remaining under the Al electrode, and a part protruding from the wiring is a part where only two layers remain. is there. Reference numerals 251 to 254 denote passivation SiN windows. At this time, the gate line portions (200 and 23)
1), bias line portions (236, 220, 201, and 23)
3, 202 and 234) and the signal line portion (232) do not change their electrical connection relationship.

Finally, slicing is performed along the slice line 250 (the slice line 250 is not actually formed in a pattern, but is virtually set based on an alignment mark), and FIG. Finish to the design size as in). At this point, the gate line portions (200 and 231) and the bias line portions (236, 220, 201 and 233, 202 and 2)
34), the electrical connection relationship of the signal line portion (232) is eliminated.

As described above, according to the pattern forming process described in this embodiment, since the common wiring is formed in the same conductive layer as the lower wiring, one mask used for patterning the lower wiring is changed. Only the other processes can be performed using the same pattern as the conventional process.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 shows a preferred embodiment of the present invention, and shows a plan view before slicing. In the drawing, reference numeral 301 denotes a lower gate wiring made of Cr or the like, 302 denotes a bias line made of Al or the like in an upper layer, and
Reference numeral 03 denotes a signal line made of Al in the upper layer. The basic configuration is the same as that of the first embodiment, and a description thereof will be omitted.

Reference numeral 390 denotes a common wiring made of the same material as the lower gate wiring, reference numerals 391 and 392 denote contact portions between the common wiring and driving wirings (bias lines and signal lines) made of Al or the like, and reference numeral 350 denotes a slice line. It is. 360-3
63 is a cross portion between the lower layer wiring and the upper layer wiring.

The process of forming a panel pattern according to the present embodiment is different from that of the first embodiment only in the mask used for patterning, and the semiconductor manufacturing process itself is the same as that described in the first embodiment. That is, the bias line 302 is electrically connected to the common line 390 via the contact portion 392, the signal line 303 is electrically connected to the common line 390 via the contact portion 391,
The gate line 301 is formed in the same lower layer pattern as the common wiring, and is electrically connected to the common wiring 390.

Therefore, also in the panel shown in this embodiment, all the wirings are
The cross portions 360 to 363 are maintained at substantially the same potential.
Is hardly damaged by static electricity. Further, as described above, in the present embodiment also, the first embodiment is changed only by changing one mask used for patterning the underlying wiring.
The same effect as described above can be obtained.

(Embodiment 3) Next, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 shows a preferred embodiment of the present invention, and shows a plan view before slicing. In the figure, 400 is a lower gate wiring, 420 is an upper bias line, 401 and 402 are sparsely biased lead lines, 403 is a lower sensor lower electrode, and 431 and 43.
Reference numerals 3 and 434 denote lead portions of respective wirings made of Al or the like in the upper layer, and reference numeral 432 denotes a signal line made of Al, which also serves as a lead portion for connection to the outside. 436 is an electrode on the sensor,
435 is a drain electrode of the TFT.

Reference numeral 490 denotes a common wiring made of the same material as the upper wiring provided in the present invention.
33, 434 and the signal line 432 are formed from the same upper layer pattern. 450 is a slice line. The other configuration is the same as that of the first embodiment, and the description is omitted.

The manufacturing process according to the present embodiment is a modified pattern of the process shown in the first embodiment, and uses an upper layer wiring material for a common wiring. Also in the present embodiment, the mask is changed only by one mask at the time of forming the upper layer pattern, and the same effect as the manufacturing process described in the first embodiment can be realized.

(Embodiment 4) Next, Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5 shows a preferred embodiment of the present invention, and shows a plan view before slicing. In the figure, reference numeral 501 denotes a lower gate wiring made of Cr or the like, and 502 denotes a bias line made of an upper Al or the like.
Numeral 03 denotes a signal line made of Al in the upper layer, and its basic configuration is the same as that of the first embodiment, so that the description is omitted.

Reference numeral 590 denotes a common wiring made of the same material as the upper wiring provided in the present invention, 591 denotes a contact portion between the common wiring 590 and the lower gate line, and 550 denotes a slice line. The manufacturing process in the present embodiment is a modified pattern of the process shown in the second embodiment, and uses an upper layer wiring material for a common wiring.

In the present embodiment, as in the third embodiment, the mask is changed by changing only one mask at the time of forming the upper layer pattern, and the same effect as the manufacturing process described in the first embodiment can be realized.

[0054]

As described above, according to the present invention,
The substrate can be prevented from being charged during the process by changing only one mask at the time of pattern formation without changing the manufacturing process itself of the semiconductor device. Therefore, it is possible to prevent a discharge between the upper layer wiring and the lower layer wiring at a cross portion thereof, thereby preventing electrostatic breakdown in a semiconductor device manufacturing process.

Also, by preventing electrostatic destruction,
The yield of semiconductor devices can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a panel according to a first embodiment before slicing.

FIG. 2 is a plan view illustrating a process of forming a panel pattern according to the first embodiment.

FIG. 3 is a plan view of a panel according to a second embodiment before slicing.

FIG. 4 is a plan view of a panel according to a third embodiment before slicing.

FIG. 5 is a plan view of a panel according to a fourth embodiment before slicing.

FIG. 6 is a plan view of a prior art panel before slicing.

FIG. 7 is a plan view showing a process of forming a panel pattern according to the related art.

[Explanation of symbols]

100, 200, 301, 501, 601, 700 C
r, lower layer gate wiring 101, 102, 201, 202, 701, 702 lower layer bias lead line 112-115, 212-216, 712-716 contact hole section 120, 220, 302, 502, 602 , 720 Upper layer bias lines 131, 231, 604, 731 Gate line lead-out parts 132, 232, 603 Signal line lead-out parts 133, 233, 234, 605, 733, 734 Bias line lead-out parts 150, 250, 350 , 450, 550, 750 Slice line 170, 670 TFT section 180, 680 Sensor section 190, 290, 390 for detecting light 190, 290, 390 Common wiring made of the same material as the lower layer gate wiring 191-194, 292 295,391,392,5
91 Contact portions between common wiring and upper driving wires (each lead portion) made of Al or the like 160 to 163, 360 to 363, 660 to 663 Cross portions between lower and upper wirings 203, 703 Lower electrodes 210, 710 of sensor The portion where the three layers are left 211, 711 to 716 The portion where the three layers are removed by the etching process 221 and 721 The portion where the lead portion of the gate line is largely left in an island shape 222, 722 The signal line is largely left in an island shape Parts 223, 224, 723, 724 parts where the bias line lead-out part is largely left in an island form 235, 735 TFT drain electrode 236, 736 upper part of sensor 241 to 244, 741 to 744 3 remaining under the upper layer wiring Layer portions, portions protruding from wiring are portions where only two layers remain 251 to 254, 751 to 754 Sshibeshon S
Upper layer signal lines 431, 433, 434 of iN window layers 303, 503 Al, etc. Leader portions of respective upper wiring lines 432, etc. Leader portions 432 Leader portions for connection to the outside by upper signal lines of Al, etc. 490, 590 Common wiring made of the same material as the wiring in the upper layer 732 Signal line and signal line lead-out portion

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/146 F-term (Reference) 2H092 JA24 JB23 JB32 JB79 KA05 KA18 KB04 MA05 MA07 MA17 NA14 PA07 RA10 4M118 AA08 AB10 BA30 CA32 CB05 CB06 CB14 FB09 FB13 FB16 GA10 5F038 BH01 BH13 CA13 CD18 DF20 EZ20 5F064 AA01 BB21 CC09 CC23 DD41 EE33 EE51 FF50

Claims (5)

[Claims] 1. A semiconductor device comprising a lower wiring pattern, an upper wiring pattern, and a semiconductor element which are vertically arranged on a substrate with an insulating layer interposed therebetween, and the substrate is cut into a predetermined size by slicing to form a semiconductor element through the insulating layer. In a method of manufacturing a semiconductor device including lower and upper wirings arranged vertically and the semiconductor element, in a region of the substrate separated from the semiconductor device by the slice, the lower wiring or a leading wire from the lower wiring and the upper layer A common line is formed to connect the wiring or the lead line from here, and the common line is separated by the slice to electrically connect the lower layer line or the lead line from the upper layer line or the lead line from the same. A method for manufacturing a semiconductor device, comprising: canceling connection. 2. The method according to claim 1, wherein the common wiring is formed as a part of at least one of the lower wiring pattern and the upper wiring pattern. 3. The method according to claim 1, wherein the lower wiring and the upper wiring have at least one portion that intersects with each other. 4. The semiconductor device according to claim 1, wherein a plurality of pairs of a photoelectric conversion element and a thin film transistor connected to the photoelectric conversion element are arranged, a gate wiring connected to the thin film transistor, and a gate wiring for driving the photoelectric conversion element. And a signal line connected to the thin film transistor for outputting a signal from the photoelectric conversion element. At least one of these lines is the lower layer line, and at least one of the other lines is a lower layer line. 4. The method of manufacturing a semiconductor device according to claim 1, wherein 5. A plurality of pairs of a photoelectric conversion element and a thin film transistor connected to the photoelectric conversion element are arranged, a gate wiring connected to the thin film transistor, a bias wiring for driving the photoelectric conversion element, and A semiconductor device including a signal wiring connected to the thin film transistor for outputting a signal from a photoelectric conversion element; a first step of forming the gate wiring on a substrate; and forming an insulating layer after the first step. A second step of forming a contact hole in the insulating layer, a third step of forming the bias wiring after the second step, and a fourth step of forming the signal wiring after the third step. In the method for manufacturing a semiconductor device formed by the fifth step of separating the element and the wiring and the sixth step of slicing the substrate to a predetermined size, until the fifth step is completed. The gate wiring, the bias wiring, and the signal wiring are electrically connected to each other, and the electrical connection between the gate wiring, the bias wiring, and the signal wiring is canceled in the sixth step. A method for manufacturing a semiconductor device.