JP2000106521A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of the oscillation circuit. SOLUTION: A polarity of a voltage in an input node N20 is sequentially being inverted by inverters 11-15 consisting of each stage, and an output voltage of an output node 15 is fed back to the input node N20 via a feedback capacitor 18 and a feedback resistor 20 that decide an oscillated frequency. A PMOS 11c or an NMOS 11d is nonconductive in the inverter 11 of a 1st stage for periods other than a period when an output of the inverter 11 is switched so as to prevent occurrence of a through current. Thus, the power consumption of the entire oscillation circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit such as a CR oscillation circuit which consumes less power.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional CR oscillation circuit. This CR oscillation circuit has five stages of amplifier circuit inverters 1 to 5 cascaded between an input node N10 and an output node N5. An output terminal N7 is connected to the output node N5 via output buffer inverters 6 and 7. The output side of the fourth-stage inverter 4 is feedback-connected to an input node N10 via a feedback capacitor 8 for determining an oscillation frequency and a limiting resistor 9. Further, the output node N5 is feedback-connected to the input node N10 via a feedback resistor 10 for determining the oscillation frequency. Each of the inverters 1 to 7 includes a P-channel metal gate type field effect transistor (hereinafter referred to as “PMOS”) and an N-channel transistor which are connected in series between a power supply potential VCC (for example, 5 V) and ground (= 0 V). Metal gate type field effect transistor (hereinafter referred to as "NMOS")
It is composed of The characteristic value of each line element is set, for example, as follows.

A PMOS constituting the first-stage inverter 1
And NMOS dimensions (ie, gate width W /
The gate length L) is 10.0 / 3.0. Similarly, two steps
Of the PMOS and NMOS constituting the second inverter 2
Dimension is 3.0 / 5.0, 3rd stage inverter
3 and the respective dimensions of the NMOS constituting NMOS 3
Is 3.0 / 1.2, P constituting the fourth inverter 4
MOS dimension is 15.0 / 1.2, NMOS
Dimensions are 10.0 / 1.2, 5th stage invar
The dimension of the PMOS constituting the data 5 is 10.0
/1.2 and the dimensions of the NMOS are 5.0 /
1.2. Construct inverter 6 for output buffer
Each dimension of PMOS and NMOS is 3.0 /
1.2, Dimension of PMOS constituting inverter 7
15.0 / 1.2 and NMOS dimensions
The ratio is 8.0 / 1.2. Threshold value of each inverter 1-7
Voltage V _tIs around 2.5V. The feedback capacitor 8
5 pF, the limiting resistor 9 is 500Ω. In addition, the oscillation
The feedback resistor 10 is set to 900 so that the wave number becomes 100 kHz.
It is set to KΩ.

Next, the operation of the CR oscillation circuit shown in FIG. 2 will be described. For example, it is assumed that the input voltage of the first-stage inverter 1 is at the “L” level in the initial state. Then, the “L” level is sequentially inverted by each of the first to fourth inverters 1 to 4, and the output voltage of the fourth inverter 4 is at the “L” level, which is output by the fifth inverter 5. The output voltage is inverted to “H” level. The “H” level of the output voltage of the fifth-stage inverter 5 is a time constant CR (where C is the capacitance value of the feedback capacitor 8, and R is the feedback resistor 10).
, And is fed back to the input node N10, so that the input voltage of the first-stage inverter 1 increases. When the input voltage of the inverter 1 of the first stage exceeds the threshold voltage V _t of the inverter 1, the output voltage of the inverter 1 is inverted to "L" level, this "L" level 2
Since the inverters are sequentially inverted by the inverters 2 to 5 at the fifth to fifth stages, the output voltage of the fifth inverter 5 falls to the “L” level. Since this "L" level is delayed by the time constant CR and fed back to the input node N10, the input voltage of the first-stage inverter 1 also falls to the "L" level. By repeating such operations, the CR oscillation circuit of FIG. 2 oscillates, and an output signal having an oscillation frequency of 100 KHz is output from the output terminal N7 via the output buffer inverters 6 and 7.

[0005]

However, the conventional CR oscillation circuit has the following problems. 3 is an input waveform diagram of the inverter 1 in FIG. 2, FIG. 4 is an output waveform diagram of the inverter 1 in FIG. 2, FIG. 5 is an output waveform diagram of the inverter 5 in FIG. 2, and FIG. FIG. 9 is an output waveform diagram of the inverter 7. FIG. 7 is a current consumption waveform diagram of the inverter 1 in FIG. 2 at an oscillation frequency of 100 KHz, and FIG. 8 is an average current consumption waveform diagram of FIG. 2 at an oscillation frequency of 100 KHz. In a conventional CR oscillation circuit, as shown in FIG. 3, for example, it is assumed that the input voltage of the first-stage inverter 1 is at the “L” level as an initial state. Then, the output voltage of the fourth-stage inverter 4 becomes “L” level, and the output voltage of the fifth-stage inverter 5 becomes “H” level. The input voltage of the first-stage inverter 1 increases in response to the “H” level of the fifth-stage inverter 5, but increases slowly because the capacitor 8 is charged (A in FIG. 3). part).

[0006] When the first stage of the input voltage of the inverter 1 has exceeded the threshold voltage V _t of the inverter 1 (2.5V before and after), the output voltage of the inverter 1 is inverted to "L" level. As a result, the output voltage of the fourth inverter 4 becomes “H” level, and the output voltage of the fifth inverter 5 becomes “L” level. When the output voltage of the fourth-stage inverter 4 becomes “H” level, one electrode side of the capacitor 8 connected to the inverter 4 is changed from 0V to the power supply potential VC.
It jumps to C (for example, 5V). Therefore, the other electrode side of the capacitor 8 also jumps from 2.5 V to 7.5 V (portion B in FIG. 3). In response to the output voltage of the fifth-stage inverter 5 being at the “L” level, the capacitor 8 is gradually discharged (portion C in FIG. 3). When the input voltage of the first-stage inverter 1 gradually decreases and reaches the threshold voltage V _t (around 2.5 V) of the inverter 1, the output voltage of the inverter 1 is inverted to “H”. Level. As a result, the output voltage of the fourth inverter 4 becomes “L” level, and the output voltage of the fifth inverter 5 becomes “H” level. When the output voltage of the fourth-stage inverter 4 becomes “L” level, one electrode side of the capacitor 8 connected to the inverter 4 drops from 5V to 0V. Therefore, the other electrode side of the capacitor 8 is also 2.5 V
To -2.5 V (part D in FIG. 3).

NMOS constituting first-stage inverter 1
And PMOS are of the V _t(≒ 2.5V) ~
It is turned on in the range of 5 V, and the PMOS is in the range of 0 V to (5 V
-V _t) (≒ 2.5 V). this
Therefore V_t~ (5V-V_t), That is, around 2.5V
In the figure, both the NMOS and the PMOS are turned on.
As shown in FIG. 7, the power supply potential V in the first-stage inverter 1
A large through current flows from CC to ground. This result
As a result, as shown in FIG.
The average current consumption of the CR oscillation circuit is
A large value of 27.78 μA. This
In the conventional CR oscillation circuit, as shown in FIG.
A large through current flows in the resistor 1 and the entire CR oscillation circuit is turned off.
There was a problem that power consumption was large. The present invention
The first-stage inverter solves the problems of existing technologies
An oscillation circuit that suppresses the through current of the
The purpose is to provide.

[0008]

Means for Solving the Problems To solve the above problems, a first aspect of the present invention is an oscillation circuit, comprising:
An n-stage (where n is an odd number) inverter cascaded between an input node and an output node, and an inverter connected between the output side of the (n-1) -th inverter and the input node An oscillation frequency determination feedback capacitor and an oscillation frequency determination feedback resistor connected between the output node and the input node are provided, and the first-stage inverter is configured as follows. That is, the first-stage inverter has a first electrode, a second electrode connected to the input side of the second-stage inverter, and the first electrode connected to the input node and having a potential on the input node. A first electrode of a first conductivity type having a control electrode for controlling conduction between the first electrode and the second electrode;
Transistor, a first electrode and a second electrode connected to the input side of the second-stage inverter, and a potential between the first and second electrodes connected to the input node by a potential on the input node. A second transistor of a second conductivity type having a polarity opposite to that of the first conductivity type, and a first electrode connected to a first power supply potential node; A second electrode connected to the first electrode of the first transistor, and a control electrode connected to the output node and controlling a conduction state between the first and second electrodes by a potential on the output node. A third transistor of the first conductivity type, a first electrode connected to a second electrode of the second transistor, and a second power supply potential node different from the first power supply potential node. Second electrode, and the output node And a connection to the fourth transistor of the second conductivity type having a control electrode for controlling the conduction state between said first and second electrodes by the potential on the output node.

By adopting such a configuration, for example, assuming that the voltage of the input node is "L" level in the initial state, the output voltage of the (n-1) -th stage inverter is "L" level, and n The output voltage of the inverter at the stage becomes “H” level. Receiving this "H" level, the voltage on the input node side rises via the feedback resistor, but rises slowly because the feedback capacitor is charged. Depending on the “H” level of the output voltage of the n-th inverter, for example, the third transistor is turned off and the fourth transistor is turned on. When the voltage on the input node side exceeds, for example, the threshold voltage of the second transistor,
Since the second and fourth transistors are both turned on, the output voltage of the first-stage inverter goes to "L" level. When the output voltage of the (n-1) -th inverter becomes "H" level, the voltage on the input node side rises, for example, to the threshold voltage of the second transistor or more via the feedback capacitor. At this time, for example, the third transistor receiving the output voltage of the n-th inverter is turned on, the fourth transistor is turned off, the first transistor receiving the voltage of the input node is turned off, and the second transistor is turned off. The transistor is turned on. Thereafter, when the feedback capacitor is discharged and the voltage of the input node falls to become equal to or lower than the threshold voltage of the second transistor, the first transistor is turned on, and both the first and third transistors are turned on. In response to this condition, the output voltage of the first inverter attains the "H" level. By repeating such an operation, an output signal having a predetermined oscillation frequency is output from the output node. In the first aspect, switching of the output voltage of the first-stage inverter depends not on the threshold voltage of the inverter itself, but on the threshold voltage of the transistor constituting the inverter. Except at the moment when the output voltage of the first-stage inverter is switched, the third or fourth transistor is reliably turned off, and the through current is cut off.

According to a second aspect, in the oscillation circuit according to the first aspect, a first capacitor is connected between a first electrode of the first transistor and the second power supply potential node, A second capacitor is connected between a second electrode of the second transistor and the second power supply potential node. As a result, the second stage inverter is driven by the electric charges charged in the first and second capacitors. Third
According to the invention, in the oscillation circuit according to the first or second invention,
A limiting resistor is connected in series with the feedback capacitor.
As a result, overcurrent passing through the feedback capacitor is suppressed, and the first and second transistors are protected. In a fourth aspect, in the oscillation circuit according to the first, second, or third aspect, an output buffer is connected to the output node. Thus, the oscillation signal output from the output node is supplied to the load via the output buffer. In a fifth aspect, in the oscillation circuit according to the first, second, third, or fourth aspect, the n-stage inverter is a field effect transistor (hereinafter, referred to as an n-stage inverter).
"FET"). Thus, the switching of the first-stage inverter depends not on the threshold voltage of the inverter itself but on the threshold voltage of the FET.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a CR oscillation circuit showing a first embodiment of the present invention. This CR oscillation circuit includes an input node N20
And n output stages N15 (for example, five stages) are connected in series between the output node N15 and the output node N15. The output node N15 is connected to the output terminal N17 via the output buffer inverters 16 and 17.
The output side of the fourth-stage inverter 14 is feedback-connected to the input node N20 via the feedback capacitor 18 for determining the oscillation frequency and the limiting resistor 19. Further, the output node N15 is connected back to the input node N20 via a feedback resistor 20 for determining the oscillation frequency. The first-stage inverter 11 includes a first transistor of first conductivity type (for example, PMOS) 11a, a second transistor of second conductivity type (for example, NMOS) 11b, and a third transistor of first conductivity type (for example, NMOS). For example, it has a PMOS 11c and a fourth transistor (for example, NMOS) 11d of the second conductivity type, and these PMOS 11c, 11a and NMOS 1
1b and 11d are the first power supply potential (for example, VCC = 5
V) node and a second power supply potential (eg, ground = 0)
V) It is connected in series with the node. PMOS11
a and the gate of the NMOS 11b are connected to the input node N20.
The connection point between the PMOS 11a and the NMOS 11b is connected to the input side of the second-stage inverter 12. The gates of the PMOS 11c and the NMOS 11d are connected to the output node N15.
5 is gate-controlled.
The other inverters 12 to 17 are each formed of a PMOS and an NMOS connected in series between the power supply potential VCC and the ground.

The characteristic value of each circuit element is determined by, for example, a feedback resistor 20 to facilitate comparison with a conventional CR oscillation circuit.
The resistance is set to the same value as the conventional one, except for the resistance value.
That is, the PMOS 11 constituting the first-stage inverter 11
Each dimension of a, 11c and NMOS 11b, 11d is 10.0 / 3.0 as in the conventional case. Further, similarly to the conventional case, the dimensions of the PMOS and NMOS constituting the second-stage inverter 12 are 3.0 /
5.0 The dimensions of the PMOS and NMOS constituting the third-stage inverter 13 are 3.0 / 1.2, and the dimensions of the PMOS constituting the fourth-stage inverter 14 are 15.0 / 1.2 and NMOS. Has a dimension of 1
0.0 / 1.2 P constituting the inverter 15 in the fifth stage
MOS dimensions are 10.0 / 1.2 and NM
The OS dimension is 5.0 / 1.2. Further, as in the conventional case, each dimension of the PMOS and NMOS constituting the output buffer inverter 16 is set to 3.
0 / 1.2, the dimension of the PMOS constituting the inverter 17 is 15.0 / 1.2, and the dimension of the NMOS is 8.0 / 1.2. Each inverter 11-
The threshold voltage Vt of _No. 17 is around 2.5V. As before, the feedback capacitor 18 is 5 pF and the limiting resistor 19 is 5 pF.
00Ω. The resistance value of the feedback resistor 20 is different from the conventional one, and is set to 2500 K so that the oscillation frequency becomes 100 KHz.
Ω is set.

FIG. 9 is a waveform diagram of the input node N20 in FIG. 1, FIG. 10 is a waveform diagram of the output node N15 in FIG.
1 is an output waveform diagram of the inverter 11 in FIG. 1, FIG. 12 is an output waveform diagram of the inverter 17 in FIG. 1, FIG. 13 is a current consumption waveform diagram of the inverter 11 in FIG. 1, and FIG. 5 is an average current consumption waveform diagram of FIG. Hereinafter, FIGS. 9 to 14
The operation of the CR oscillation circuit of FIG. 1 will be described with reference to FIG.
For example, it is assumed that the voltage of input node N20 is at the “L” level in the initial state. Then, the “L” level is sequentially inverted by each of the inverters 11 to 14 of the first to fourth stages, and the output voltage of the fourth inverter 14 is at the “L” level. The output voltage is inverted to “H” level. Fifth-stage inverter 1
5, the voltage of the input node N20 rises via the feedback resistor 20.
8 and slowly rises (FIG. 9).
Part A). At this time, the PMOS 11 c is turned off and the NMOS 11
d is on.

When the voltage at the input node N20 is the NMOS 11b
Above the threshold voltage V _tn of the NMOS 11b,
11d are both turned on.
Attains an "L" level. Since this "L" level is sequentially inverted by the second to fifth inverters 12 to 15, the output voltage of the fourth inverter 14 becomes "H".
Level, the output voltage of the inverter 15 at the fifth stage becomes “L” level. When the output voltage of the fourth-stage inverter 14 becomes “H” level, one of the electrodes of the capacitor 18 connected to the inverter 14 changes from 0V to the power supply potential V
Jumps up to CC (for example, 5V). Therefore, the other electrode side of the capacitor 18 also jumps from the threshold voltage V _{tn of the} NMOS 11b to (V _tn + 5V) (portion B in FIG. 9). At this time, the PMOS 11c receiving the “L” level of the output node N15 is in the ON state, and the NMOS 11d
Are turned off, the PMOS 11a receiving the voltage of the input node N20 is turned off, and the NMOS 11b is turned on. At this time, the output side of the first-stage inverter 11 does not enter a floating state, but maintains the previous “L” level due to the parasitic capacitance of the MOS transistor and the like.

The "L" level of the output voltage of the first-stage inverter 11 is changed to the second- to fifth-stage inverters 12-1.
5, the output voltage of the fifth inverter 15 becomes the "L" level. In response to this "L" level,
The capacitor 18 gradually discharges (portion C in FIG. 9). The voltage of the input node N20 gradually decreases, (5V-
When V _tp ) or less, the PMOS 11a is turned on. At this time, the PMOS 11c is also turned on by the “L” level of the output node N15. PMOS11
In response to the state in which both a and 11c are turned on, the output voltage of the first-stage inverter 11 goes high.
This “H” level is applied to the second to fifth inverters 12 to
15, the output voltage of the fourth inverter 14 becomes “L” level and the output voltage of the fifth inverter 15 becomes “H” level. In response, the PMOS 11c of the first-stage inverter 11 is turned off,
1d is on, PMOS 11a is on, and NM
The OS 11b is turned off, and the output voltage of the first-stage inverter 11 maintains the “H” level due to the parasitic capacitance of the MOS transistor and the like. By repeating such operations, the CR oscillation circuit in FIG. 1 oscillates, and an output signal having an oscillation frequency of 100 KHz is output from the output terminal N17 via the inverters 16 and 17 for output buffers.

As described above, the CR oscillation circuit according to the present embodiment has the following effects (i) to (iii). (I) In the first-stage inverter 11, the PMOS 11a and the NMOS 11b are changed according to the voltage of the input node N20.
Switching, since further performed switching of PMOS11c and NMOS11d by the output voltage of the output node N15, switching of the output of the first inverter 11 is not the threshold voltage V _t of the inverter itself as in the prior art, MOS
It depends on the threshold voltages V _tn and V _tp of the transistors. In addition, the waveform of the input node N20 in FIG. 9 and the waveform of the output node N15 in FIG.
1a is on, PMOS 11c is off, NM
When the OS 11b is on, the NMOS 11d is off. That is, except for the moment when the output of the first-stage inverter 11 is switched, the PMOS 11c or the NMOS 1
Since 1d is reliably turned off, a through current from the power supply potential VCC in the first-stage inverter 11 to the ground can be prevented. Therefore, as shown in FIG. 13, the current consumption of the inverter 11 is smaller than the current consumption of the conventional inverter shown in FIG. As a result, as shown in FIG.
At KHz, the average current consumption of the CR oscillation circuit is Hspice
Is a very small value of 2.60 μA. (Ii) The capacitance value of the feedback capacitor 18 and the feedback resistor 20
The oscillation frequency can be set arbitrarily by changing the resistance value of. (iii) limiting resistor 1 in series with feedback capacitor 18
9, the PMOS 11a and the NMOS 1
Overcurrent flowing to each gate of 1b can be prevented, whereby the PMOS 11a and NMOS 11b can be protected. Also, the input node N20 is
, And the output of the first-stage inverter 11 can be accurately switched.

Second Embodiment FIG. 15 is a circuit diagram of a CR oscillation circuit showing a second embodiment of the present invention, and is common to elements in FIG. 1 showing the first embodiment and common elements. Are given. In this CR oscillation circuit, instead of the first-stage inverter 11 in FIG.
An inverter 11A having a different configuration is provided, and a feedback resistor 20A having a different resistance value is used instead of the feedback resistor 20 of FIG.
Is provided. The first-stage inverter 11A includes PMOS 11c, 11a and NMOS 11 connected in series between the power supply potential VCC and the ground, similarly to the first embodiment.
b and 11d, a first capacitor 11e is connected between the connection point of the PMOSs 11c and 11a and the ground, and a second capacitor 11f is connected between the connection point of the NMOSs 11b and 11d and the ground. Is connected. Each of the capacitors 11e and 11f has a capacitance value of, for example, 1 pF. The resistance value of the feedback resistor 20A is set to 2200 KΩ so that the oscillation frequency becomes 100 KHz. Other configurations and characteristic values of each circuit element are the same as those in FIG.

FIG. 16 is a waveform diagram of the input node N20 in FIG. 15, FIG. 17 is a waveform diagram of the output node N15 in FIG.
18 is an output waveform diagram of the inverter 11A in FIG. 15, FIG. 19 is an output waveform diagram of the inverter 17 in FIG.
15 is a current consumption waveform diagram of the inverter 11A in FIG. 15, and FIG. 21 is an average current consumption waveform diagram of the whole of FIG. Hereinafter, the operation of the capacitors 11e and 11f of the CR oscillation circuit of FIG. 15 will be described with reference to FIGS. FIG.
The first-stage inverter 11 includes a PMOS 11c and an NM
Since the through current is limited by the OS 11d, there is almost no current supply capability to the output side of the inverter 11, and the capability of driving the second-stage inverter 12 is small.
For this reason, capacitors 11e and 11f are provided, and as shown in FIG. 18, the second-stage inverter 12 is driven by using the charges temporarily stored in the capacitors 11e and 11f. As a result, the oscillation operation can be reliably performed.

Since the capacitance values of the capacitors 11e and 11f are very small, for example, 1 pF, there is almost no increase in current due to the provision of the capacitors 11e and 11f as shown in FIG. As shown in FIG. 21, the average consumption current of the CR oscillation circuit at an oscillation frequency of 100 KHz is 3.26 μA, which is a simulation value in Hspice.
Value. It can be seen that the overall average current consumption does not increase so much compared to the average current consumption of 2.60 μA in FIG. As described above, in the present embodiment, in addition to the effects of the first embodiment, since the capacitors 11e and 11f are provided, the oscillation operation can be reliably performed without increasing the power consumption so much.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) and (b). (A) In FIGS. 1 and 15, the five-stage inverter 11,
Although the CR oscillation circuits 11A to 15 have been described, the number of inverters 11 and 11A to 15 may be an arbitrary odd number. Even with such a configuration, substantially the same operation and effect as in the above embodiment can be obtained. Can be Further, the characteristic value of each circuit element such as the dimension of the MOS transistor can be arbitrarily changed according to conditions such as the power supply potential VCC and the oscillation frequency. (B) In the above embodiment, the oscillation circuit is configured by using the MOS transistors, but may be configured by using other transistors such as FETs.

[0021]

As described above in detail, according to the first aspect, the first-stage inverter is constituted by the first, second, third, and fourth transistors. Except at the moment when the output of the inverter is switched, the third or fourth transistor is reliably turned off, and a through current can be prevented. As a result, current consumption can be reduced. According to the second aspect, since the first and second capacitors are provided in the first-stage inverter, the second-stage inverter is driven by using the charges temporarily stored in these capacitors. be able to. Thereby, the oscillation operation can be reliably performed. According to the third aspect, since the limiting resistor is connected in series with the feedback capacitor, overcurrent flowing to the control electrodes of the first and second transistors in the first-stage inverter is prevented, and these transistors are protected. In addition, it is possible to prevent the voltage fluctuation of the control electrode and perform the stable switching operation of the first-stage inverter. According to the fourth aspect, since the output buffer is connected to the output node, the influence of the load connected to the output buffer can be reduced. According to the fifth aspect, since the n-stage inverters are each configured by an FET, a small and accurate oscillation circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CR oscillation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional CR oscillation circuit.

FIG. 3 is an input waveform diagram of the inverter 1 in FIG.

4 is an output waveform diagram of an inverter 1 in FIG.

5 is an output waveform diagram of the inverter 5 in FIG.

6 is an output waveform diagram of the inverter 7 in FIG.

7 is a current consumption waveform diagram of the inverter 1 in FIG.

8 is a waveform chart of the average current consumption of the whole of FIG. 2;

9 is a waveform diagram of an input node N20 in FIG.

FIG. 10 is a waveform chart of an output node N15 in FIG. 1;

FIG. 11 is an output waveform diagram of the inverter 11 in FIG.

12 is an output waveform diagram of the inverter 17 in FIG.

13 is a current consumption waveform diagram of the inverter 11 in FIG.

FIG. 14 is a waveform chart of average current consumption of the whole of FIG. 1;

FIG. 15 is a circuit diagram of a CR oscillation circuit according to a second embodiment of the present invention.

FIG. 16 is a waveform diagram of an input node N20 in FIG.

FIG. 17 is a waveform chart of an output node N15 in FIG.

18 is an output waveform diagram of the inverter 11A in FIG.

19 is an output waveform diagram of the inverter 17 in FIG.

20 is a current consumption waveform diagram of inverter 11A in FIG.

21 is a waveform chart of the average current consumption of the whole of FIG. 15;

[Explanation of symbols]

 11, 11A to 17 Inverter 11a, 11c PMOS 11b, 11d NMOS 18 Feedback capacitor 19 Limiting resistor 20, 20A Feedback resistor N15 Output node N17 Output terminal N20 Input node

Claims (5)

[Claims] 1. An n-stage (where n is an odd number) inverter connected in cascade between an input node and an output node; and an output terminal of the (n-1) -th inverter and the input node. An oscillation frequency determination feedback capacitor connected between the output node and the input node; and an oscillation frequency determination feedback resistor connected between the output node and the input node. An electrode, a second electrode connected to the input side of the second-stage inverter, and control for controlling a conduction state between the first and second electrodes by a potential on the input node connected to the input node. A first transistor of a first conductivity type having an electrode; a first electrode and a second electrode connected to the input side of the second-stage inverter; and a potential on the input node connected to the input node. The first and second power A second transistor of a second conductivity type having a polarity opposite to that of the first conductivity type, the first electrode being connected to a first power supply potential node; A second electrode connected to a first electrode of the first transistor; and a control electrode connected to the output node and controlling a conduction state between the first and second electrodes by a potential on the output node. A third transistor of the first conductivity type, comprising: a first transistor connected to a second electrode of the second transistor;
, A second electrode connected to a second power supply potential node different from the first power supply potential node, and the first and second electrodes connected to the output node by a potential on the output node. An oscillation circuit comprising: a fourth transistor of the second conductivity type having a control electrode for controlling conduction between the fourth transistor and the second transistor. 2. The oscillation circuit according to claim 1, wherein a first capacitor is connected between a first electrode of said first transistor and said second power supply potential node, and said second transistor is connected to said first power supply node. An oscillation circuit comprising a second capacitor connected between a second electrode and the second power supply potential node. 3. The oscillation circuit according to claim 1, wherein a limiting resistor is connected in series with said feedback capacitor. 4. The oscillation circuit according to claim 1, wherein an output buffer is connected to said output node. 5. The oscillation circuit according to claim 1, wherein each of said n-stage inverters is constituted by a field effect transistor.