JP2000103696A - Silicon epitaxial wafer and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize the in-plane distribution of the surface roughness of a silicon epitaxial wafer layer by optimizing the in-plane distribution of susceptor temperature of a vapor-phase thin film growing apparatus. SOLUTION: A susceptor 5 is supported only at the circumferential part of the back face by using vertical pins 7b at the tip ends of spokes 7 radially branched from a rotary shaft 6 in place of supporting the susceptor at the center of the back face. The susceptor 5 is constructed in such a manner as to keep the difference between the maximum temperature and the minimum temperature on the surface of the silicon wafer within 7 deg.C. The in-plane distribution of the surface roughness of the silicon epitaxial wafer can be suppressed to <=0.02 ppm by this method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a silicon epitaxial wafer and a method for manufacturing the same, and more particularly, to high-precision management of the surface roughness of a silicon epitaxial layer through uniformization of the in-plane temperature of the silicon wafer.

[0002]

2. Description of the Related Art The design rules for semiconductor devices are:
It has already reached the sub-quarter micron level at a practical level. As the amount of electric charge handled by semiconductor devices decreases due to miniaturization, even a small defect near the surface of a silicon single crystal substrate has a greater risk of having a fatal effect on device characteristics than ever before, and in particular, the performance of bipolar circuits and CMOS circuits Deterioration becomes a problem. So in the future,
Instead of a silicon single crystal substrate manufactured by slicing and mirror polishing a silicon single crystal ingot pulled from the melt, the use of silicon epitaxial wafers obtained by vapor-growing a silicon epitaxial layer on the surface is increasing. Expected. Hereinafter, the silicon single crystal substrate and the silicon epitaxial wafer are collectively referred to as a silicon wafer.

[0003] A silicon epitaxial wafer requires a high degree of thickness uniformity. Since the original silicon single crystal substrate is highly flat, the thickness uniformity may be referred to as the flatness of a silicon epitaxial layer vapor-phase grown on the silicon single crystal substrate. High flatness is required because the wavelength of exposure light used in recent photolithography has been shortened to the far ultraviolet wavelength region, and the depth of focus has been significantly reduced. Because there is. Moreover, this requirement is that the silicon wafer diameter is
As they expand from m to 300 mm and even higher, they become increasingly severe.

FIG. 8 shows an example of the configuration of a single-wafer type vapor phase thin film growing apparatus 20. In this apparatus, a silicon wafer W placed one by one in a reaction vessel 21 made of transparent quartz is radiatively heated from above and below using infrared lamps 29a and 29b, and a vapor phase growth of a thin film is performed. . The infrared lamps 29a and 29b are arranged in double concentric circles, with the infrared lamp 29a constituting an outer pair and the infrared lamp 29b constituting an inner pair. The above reaction vessel 2
1 is divided into an upper space 21a and a lower space 21b by a susceptor 25 for mounting the silicon wafer W thereon. In the upper space 21a, gas supply holes 22
The raw material gas introduced together with the H ₂ gas as a carrier gas flows in the direction of arrow A in the figure while forming a substantially laminar flow on the surface of the silicon wafer W, and is discharged from the exhaust hole 24 on the opposite side. The lower space 21b is supplied with H ₂ gas which is a purge gas at a higher pressure than the source gas. The reason why the pressure of the purge gas is increased is that the reaction vessel 21 and the susceptor 2
This is to prevent the raw material gas from entering the lower space 21b from the gap between the source gas 5 and the lower space 21b.

In the lower space 21b, the susceptor 2
Support means made of quartz for supporting the back surface of the silicon wafer W from behind and lift pins for attaching and detaching the silicon wafer W on the susceptor 25 are built in. The support means includes a rotating shaft 26 and a plurality of spokes 27 radially branched from the rotating shaft 26. Vertical pins 27b and 27c are provided at the end of the spoke 27 and the tip of the rotating shaft 26, respectively.
The tips of b and 27c are fitted into recesses 25c and 25d provided on the back surface of the susceptor 25, respectively, to support them. The rotation shaft 26 is
It is rotatable in the direction of arrow C in the figure by driving means (not shown).

The head of the lift pin 28 has an enlarged diameter, and the head has a through hole 25b formed in the bottom surface of the counterbore 25a of the susceptor 25 for mounting the silicon wafer W thereon.
Are suspended from the tapered side wall portion. The shaft portion of the lift pin 28 is a through hole 27 a formed in the middle of the spoke 27.
, So that the lift pins 28 are stably suspended.

The mounting and dismounting of the silicon wafer W on the susceptor 25 is performed by raising and lowering the support means. For example, when removing the silicon wafer W from the susceptor 25, the support means is lowered as shown in FIG. 9, and the tail of the lift pin 28 is brought into contact with the inner wall of the lower space 21b of the reaction vessel 21. The lift pins 28 urged by this abut against the back surface of the silicon wafer W at the head thereof, and float the silicon wafer W above the counterbore 25a. After that, a handler (not shown) is inserted into the space between the susceptor 25 and the silicon wafer W, and the silicon wafer W is transferred and transported.

As a constituent material of the susceptor 25, a graphite base material coated with a SiC (silicon carbide) film is usually used. The fact that graphite is selected as the base material is related to the fact that the mainstream of the heating method of the vapor phase thin film growth equipment at the beginning of development was high-frequency induction heating, but it is also easy to obtain high-purity products This is because there are merits such as easy processing, excellent thermal conductivity, and difficulty in breaking. However, because graphite is a porous material, there is a possibility that occluded gas may be released during the process. In the process of vapor phase thin film growth, graphite reacts with the source gas to change the surface of the susceptor to SiC. Therefore, there has been a problem that the surface is covered with a SiC film from the beginning. SiC coatings are usually CVD
(Chemical vapor deposition). Like the susceptor 25, the constituent material of the lift pin 28 is a graphite-based SiC coating.

[0009]

The demand for the flatness of a silicon epitaxial wafer has been increasing year by year. It has been found that the thickness of the epitaxial layer varies depending on the in-plane position of the silicon epitaxial wafer. In particular, when the thickness of the silicon epitaxial layer exceeds approximately 8 μm, the difference in the in-plane thickness of the silicon epitaxial layer tends to be emphasized to a level that is not practically preferable.

FIG. 10 shows that the diameter is 200 mm, the plane orientation of the main surface is (100), and the resistivity is 0.01 Ω · cm to 0.02 Ω ·
cm on a p ⁺ type silicon single crystal substrate with a target thickness of 15μ
m and p-type silicon epitaxial layer (resistivity = 10Ω)
* Cm) shows the film thickness distribution of the silicon epitaxial layer observed by the present inventors when vapor-phase growth is performed. (A) shows the measurement direction of the film thickness distribution, the direction toward the notch N (notch) indicating the crystal orientation is the vertical direction,
The direction orthogonal to this is the horizontal direction. (B) shows the film thickness distribution with respect to the horizontal distance from the center of the silicon epitaxial wafer EW, and (c) shows the film thickness distribution with respect to the vertical distance from the center of the silicon epitaxial wafer EW.

As is apparent from these figures, the thickness of the silicon epitaxial layer tends to decrease at the center of the silicon epitaxial wafer EW. Due to this thickness drop, flatness is reduced by SEMI (Semicondu
0.3 μm in SFQD (SEMI M1-96) as defined by ctor Equipment and Materials International)
Due to the extremely large extent, the flatness defect rate may exceed 4% in the production of a silicon epitaxial wafer. Here, SF defined by SEMI
With QD, the whole wafer is divided into 20 mm square cells,
This is the absolute value of the maximum value of the elevation difference between the reference plane obtained by the best fit method and the projections or depressions generated in each cell.

The present inventors newly show that the same tendency is observed in FIG. 11 showing the result of measuring the in-plane distribution of the surface roughness of a silicon epitaxial layer using a laser scattered light detection device. Was found. The laser scattered light detection device is a device that detects the size of fine particles and surface roughness by measuring the intensity of scattered light obtained by scanning the silicon wafer surface with laser light. The intensity of the scattered light is expressed in units of ppm. For example, 0.5
The ppm means that scattered light having an intensity of 0.5 / million with respect to the intensity of the incident light was measured. Also, since the intensity of the scattered light is proportional to the magnitude of the surface roughness, it can be seen that, for example, when the intensity of the scattered light is high, the irregularities are relatively large. Although the laser scattered light detection device can measure the entire main surface of the silicon wafer, non-negligible levels of irregularly reflected light from the chamfered portion are simultaneously measured at the periphery of the silicon wafer surface. The measurement values obtained in the range of several mm in width at the peripheral portion of the wafer surface are excluded.

Referring to FIG. 11, the surface of a silicon epitaxial wafer EW has an A depending on the surface roughness.
To D can be roughly classified. The intensity of the scattered light is as large as 0.345 ppm to 0.365 ppm in a region A occupying an arc shape as if dividing the peripheral portion of the wafer into approximately three equal parts, and in a region B forming an island shape centering on the inside of a break of the region A. Therefore, it can be seen that relatively large surface roughness is generated. On the other hand, the intensity of the scattered light is 0.330 ppm to 0.335 p in the region C which is generated in a circular shape at the center of the wafer and in the region D which is generated in the form of a dot near the break of the region A.
pm and the surface roughness is relatively small.
From the difference between the maximum value (0.365 ppm) and the minimum value (0.330 ppm) of the intensity of the scattered light, the surface roughness of the silicon epitaxial wafer EW has a variation of 0.035 ppm in terms of the intensity of the scattered light. It turns out that there is.

Thus, FIG. 11 showing the distribution of the surface roughness of the silicon epitaxial wafer EW is also shown in FIG.
Surface roughness tends to be small at the center of W. However, the amount of change in film thickness cannot be directly estimated from the surface roughness. This is because the surface roughness mainly depends on the in-plane temperature distribution of the silicon wafer, whereas the change in film thickness depends not only on the in-plane temperature distribution of the silicon wafer but also on the in-plane distribution of the supply amount of the source gas. This is because they will be affected.

However, in any case, the thickness distribution as described above is not practically acceptable, assuming application to a future semiconductor process in which the design rule is reduced to 0.13 μm or less. Therefore, an object of the present invention is to provide a silicon epitaxial wafer in which the uniformity of the surface roughness of the silicon epitaxial layer is further improved, and the flatness and the in-plane distribution of the film thickness are improved, and a method for manufacturing the same.

[0016]

The silicon epitaxial wafer of the present invention has a surface roughness measured by a laser scattered light detection method in which the cumulative frequency is 0.3% or less from the upper end and the lower end, respectively. It has a silicon epitaxial layer in which the in-plane distribution of the surface roughness calculated excluding the value is suppressed to 0.02 ppm or less. Excluding from the upper and lower ends the measured values included within the cumulative frequency of 0.3% means that the measured values outside the range of x ± 3σ (σ is the standard deviation) centered on the average value x of all the measured values. Is almost equivalent to excluding.

In order to manufacture such a silicon epitaxial wafer, the present inventors have improved the shape of the support means made of quartz, and
And a good result can be obtained by shifting the contact position of the end portion (corresponding to the above-described vertical pin 27b) of the support member (corresponding to the above-described spoke 27) to the back surface of the susceptor to the outer peripheral side as compared with the related art. It has been found that the present invention can be performed, and the present invention has been proposed. At this time, the distance from the outer peripheral edge of the susceptor to the contact portion at the end of the support member is set to a value that can suppress the temperature drop of the silicon wafer edge with respect to the in-plane maximum temperature of the silicon wafer within 7 ° C. You.

The susceptor is rotated around a predetermined rotation axis. However, when the heating means is a plurality of infrared lamps arranged around a predetermined center axis,
By making this center axis eccentric with respect to the rotation axis of the susceptor, the radiant heat of the heating means can reach the conventional shielding part by the support means from obliquely downward. Therefore, a local decrease in temperature in the susceptor surface can be mitigated, and a decrease in the thickness of the thin film at the corresponding portion of the silicon wafer on the susceptor can be prevented. Furthermore, the influence of the support member can be reduced by increasing the distance between the back surface of the susceptor and the support member as compared with the related art. The distance is set to a value that can keep the difference between the highest temperature and the lowest temperature within the silicon wafer surface within 7 ° C.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is based on the assumption that the in-plane distribution of the surface roughness of a silicon epitaxial layer measured by using a laser scattered light detecting device is the film thickness distribution of the silicon epitaxial layer due to non-uniform temperature. It is proposed by focusing on the fact that it has a similar tendency. The surface roughness is correlated with the growth temperature, and as shown in FIG. 1, the surface roughness decreases when the growth temperature is low, but tends to increase as the growth temperature increases. The fact that the surface roughness changes by 0.02 ppm near 1130 ° C., which is a general silicon epitaxial growth temperature, means that a growth temperature difference of 7 ° C. exists locally. In a supply rate-limiting temperature range of 1050 ° C. or higher where normal silicon epitaxial growth is performed, if the growth temperature difference is set to 7 ° C. or lower, the growth temperature does not substantially change, and a uniform growth rate is achieved even when viewed locally. be able to.

Referring again to FIG. 11 with the above in mind, it can be seen that the central region C and the three peripheral regions D of the silicon epitaxial wafer EW are regions where the temperature is relatively low. These regions C and D correspond to contact portions of the vertical pin 27c and the lift pin 28, respectively. The region C is a portion where the vertical pin 27c comes into contact with the rear surface, but it is considered that the heat of the infrared lamp 29b does not easily reach due to the spatial shielding by the rotating shaft 26, and thus the temperature is lowered. Can be The region D is a portion where the lift pins 28 come into contact from the back surface. However, since the thermal conductivity of the graphite base material, which is a constituent material of the lift pins 28, is extremely high, heat is generated using the lift pins 28 as a heat conduction path, It is considered that the temperature was lowered for this reason. The island-shaped region B is a region having a slightly higher temperature than the surroundings, and corresponds to a portion where the spokes 27 extending in three directions from the central axis 26 are provided. Quartz, which is a constituent material of the spokes 27, exerts a large heat storage effect due to the low thermal conductivity, so it is considered that once heated, the temperature in the vicinity thereof increases.

The present invention seeks to make the in-plane temperature distribution uniform by devising the shape of the support means that may affect the temperature distribution in the silicon wafer plane. As one of the measures, the distance from the outer peripheral edge of the susceptor to the contact portion at the end of the support member is made shorter than before, that is, the contact portion is made farther from the peripheral portion of the silicon wafer. The optimum value of the above distance varies depending on the specifications of the vapor phase thin film growth apparatus, such as the thickness, thermal conductivity, output of the heating means, shape and dimensions of the end of the support member, and cannot be specified unconditionally by the dimensions. . In the present invention, "a value capable of suppressing the temperature drop of the wafer edge portion with respect to the maximum in-plane temperature of the silicon wafer placed on the susceptor within 7 ° C."
The reason why the temperature is specified is to make the rule universal.

Embodiment 1 Here, a silicon epitaxial wafer of the present invention will be described with reference to FIG. The display pitch of the surface roughness in FIG. 2 is smaller than that in the case of FIG. 11 described above, and the meaning of the surface roughness is different even with the same hatching. This silicon epitaxial wafer EW is a p-type silicon epitaxial layer (resistivity = 15 μm) having a target thickness of 15 μm on a p ⁺ -type silicon single-crystal silicon wafer having a diameter of 200 mm and a plane orientation (100) of the main surface.
10 Ω · cm).

In FIG. 2 showing the present invention, regions A to C similar to those shown in FIG. 11 showing a conventional example are seen, but the appearance thereof is considerably different. First, the regions A of the surface roughness increase regions appearing at three locations in the peripheral portion of the silicon epitaxial wafer EW in FIG. 2 are considerably smaller than those in FIG. 11 showing the conventional example. The region B, which is the surface roughness increasing region that appears in an island shape in FIG. 11, is not isolated in FIG. 2 showing the present invention, and is more evenly distributed in the silicon wafer surface. In addition, the central region C is not a clear circular surface roughness reduction region as shown in FIG. 11, but rather a vague surface roughness increase region. The dotted area D seen in FIG. 11 does not appear in FIG.

According to the present invention, the in-plane surface roughness is excluded from all the measured values of the surface roughness by the laser scattered light detection method, except for the measured values included within the cumulative frequency of 0.3% from the upper end and the lower end, respectively. Find the distribution. In the case of the silicon epitaxial wafer EW shown in FIG. 1, the measurement value included within the cumulative frequency of 0.3% refers to a region having a surface roughness of 0.334 ppm or less (frequency: 0.08%) and a surface roughness of 0.34 ppm. 352pp
m or more (frequency 0.15%). Therefore,
The maximum value of the in-plane roughness of this silicon epitaxial wafer is 0.352 ppm, the minimum value is 0.334 ppm, and the in-plane distribution of the surface roughness is 0.352−0.334 =
It becomes 0.018 ppm. This value was in the range of 0.02 ppm specified in the present invention, and it was confirmed that the silicon epitaxial wafer had an extremely uniform in-plane roughness distribution.

FIG. 3 shows a film thickness distribution of the silicon epitaxial wafer EW of the present invention. Here, (a) shows the measurement direction of the film thickness distribution and the notch N indicating the crystal orientation.
The direction toward (notch) is defined as a vertical direction, and the direction perpendicular to the direction is defined as a horizontal direction. (B) is a film thickness distribution with respect to a lateral distance from the center of the silicon epitaxial wafer EW, and (c) is a silicon epitaxial wafer EW.
6 shows a film thickness distribution with respect to a vertical distance from the center of W. As is clear from these figures, a decrease in the thickness of the silicon epitaxial layer at the center of the wafer hardly appears. SFQD according to the definition of SEMI is 0.01 μm at the center of the wafer,
The maximum value is 0.17 μm in the whole wafer,
It has been greatly improved compared to the past.

In the manufacture of a silicon epitaxial wafer, the in-plane distribution of the surface roughness of the silicon epitaxial layer is suppressed to 0.02 ppm or less as defined in the present invention, so that the defect rate of the flatness based on SFQD is reduced by 0.7%. %. That is, a silicon epitaxial wafer whose surface roughness is suppressed to 0.02 ppm or less specified in the present invention does not cause a local change in film thickness or flatness caused by a local temperature change. It becomes.

Embodiment 2 Here, a configuration example of a single-wafer-type vapor-phase thin film growing apparatus 10 used for manufacturing the silicon epitaxial wafer shown in Embodiment 1 will be described with reference to FIGS. . FIG. 4 is a schematic sectional view showing a configuration example of a vapor phase thin film growth apparatus, FIG. 5 is a schematic sectional view showing a part of the apparatus enlarged, and FIG. 6 is a plan view of the susceptor as viewed from the back. In this apparatus, vapor-phase epitaxial growth is performed while heating silicon wafers W set one by one in a reaction chamber 1 made of transparent quartz from above and below using infrared lamps 9. The inside of the reaction vessel 1 is divided into an upper space 1a and a lower space 1b by a susceptor 5 for mounting the wafer W thereon.

The susceptor 5 is made of a graphite substrate made of C
Diameter 25 made of material coated with VD coating
It is a disk having a thickness of 0 mm and a thickness of 4 mm, and a counterbore portion 5a is formed on the upper surface thereof as a mounting portion of the silicon wafer W. The size of the counterbore portion 5a is, for example, 205 mm in diameter when an 8-inch wafer (200 mm in diameter) is placed.
mm and a depth of 1 mm. In addition, as shown in FIG. 6, at the periphery of the back surface of the susceptor 5, the end of the support member,
That is, a recess 4c having a diameter of 4 mm and a depth of 2 mm and a recess 5d having a diameter of 10 mm and a depth of 2 mm are formed in a portion where the head of a vertical pin 7b provided at the end of the spoke 7 described below abuts. Here, since there are three spokes 7, the recesses 5c and 5d are arranged at equal intervals with a central angle of 120 °. Here, the center of the concave portion 5b is considered to be equal to the center of the vertical pin 7b, and the distance from the outer peripheral edge of the susceptor 5 to the center of the concave portions 5c and 5d is defined as the outer peripheral edge-vertical pin distance d1. Here, as an example, d
1 = 5 mm. This is a position closer to the outside by 6 mm than in the related art.

By the way, in the conventional device as shown in FIG.
c is provided, and the susceptor 2 is formed by using a concave portion 25d on the rear surface of the susceptor central portion for receiving the vertical pin 27c.
5 and the support member were aligned. However, in the present invention in which the vertical pin at the center is omitted, such alignment cannot be performed, and one of the concave portions at the periphery is used for alignment instead. That is why the concave portion 5c is reduced in diameter as compared with the other two concave portions 5d. That is, the concave portion 5c having a diameter capable of accommodating the vertical pin 7b at the end portion of the spoke 7 with almost no gap is used for alignment, and the other two concave portions 5d have some allowance.

In the upper space 1 a in the reaction vessel 1, the source gas introduced together with the H ₂ gas as the carrier gas from the gas supply hole 2 forms a substantially laminar flow over the surface of the silicon wafer W in the direction of arrow A in the figure. And is discharged from the exhaust hole 4 on the opposite side. The lower space 1b is supplied with H ₂ gas which is a purge gas at a higher pressure than the source gas.
The reason why the pressure of the purge gas is set to be high is that the reaction vessel 1 and the susceptor 5
This is to prevent the raw material gas from entering the lower space 1b from the gap between them. In the lower space 1b, support means made of quartz for supporting the susceptor 5 from the back surface and lift pins 8 for attaching and detaching the silicon wafer W on the susceptor 5 are incorporated.

The support means includes a rotating shaft 6 and, for example, three spokes 7 radially branched from the rotating shaft 6.
It is composed of A vertical pin 7b is provided at the end of the spoke 7, and its tip is fitted into a concave portion 5c provided on the back surface of the susceptor 5 to support it. As in the conventional device, a member corresponding to a vertical pin abutting on the center rear surface of the susceptor on the extension of the rotation axis does not exist in the device of the present invention. The distance between the back surface of the susceptor 5 and the spoke 7 is defined as a susceptor-spoke distance d2. Here, as an example, d2 = 15 mm. The rotating shaft 6 is rotatable in a direction indicated by an arrow C in the figure by a driving unit (not shown).

The lift pin 8 has a head whose diameter is enlarged, and the head has a susceptor 5 for mounting a silicon wafer W thereon.
Is suspended on the tapered side wall of a through hole 5b provided on the bottom surface of the counterbore 5a. The shaft portion of the lift pin 8 is inserted into a through hole 7a formed in the middle of the spoke 7, so that the lift pin 8 is stably hung down.
In the present embodiment, as a constituent material of the lift pins 8, Si is used.
A C base coated with a SiC coating was used. The SiC substrate has a lower thermal conductivity than a conventional graphite substrate. The attachment / detachment of the silicon wafer W on the susceptor 5 is performed by raising / lowering the support means. For example, when removing the silicon wafer W from the susceptor 5, the support means is lowered, and the tail of the lift pin 8 is brought into contact with the inner wall of the lower space 1b of the reaction vessel 1. The lift pins 8 urged by this abut against the back surface of the silicon wafer W at the head thereof, and float the silicon wafer W above the counterbore 5a. After that, a handler (not shown) is inserted into the space between the susceptor 5 and the silicon wafer W, and the silicon wafer W is transferred and transported.

The infrared lamps 9a and 9b have a plurality of lamps arranged in a double concentric circle. The infrared lamp 9a constitutes one set on the outside, and the infrared lamp 9b constitutes one set on the inside. The spatial center axis of each set coincides with the rotation axis 6 of the susceptor 5. These two
The amount of electricity supplied to the pair of infrared lamps 9a and 9b can be controlled independently, so that the amount of heating by these two sets can be adjusted independently.

Here, the silicon epitaxial layer was actually vapor-phase grown using the above-described vapor-phase thin-film growth apparatus.
The silicon single crystal substrate used was a p ⁺ -type silicon single crystal substrate having a diameter of 200 mm and a plane orientation of the main surface (100), and a p-type silicon epitaxial layer having a target thickness of 15 μm (resistivity = 10 Ω · cm). The epitaxial growth conditions were as follows as an example. H ₂ annealing conditions: 1130 ° C., 45 seconds Epitaxial growth temperature: 1130 ° C. H ₂ flow rate: 40 l / min Source gas (diluted SiHCl ₃ with H ₂ ) flow rate: 12 l / min Dopant (B ₂ H ₆ with H ₂ ) Dilution) flow rate: 100ml
In growing the silicon epitaxial layer, the temperature distribution of the silicon single crystal substrate was first optimized so that the in-plane distribution of the surface roughness of the silicon epitaxial layer was suppressed to 0.02 ppm or less as described above. Next, the supply amount of the source gas was adjusted to adjust the film thickness distribution in the wafer.

The silicon epitaxial wafer described above in the first embodiment is obtained in this manner. The surface roughness distribution of this silicon epitaxial wafer EW is 0.018 ppm, and the above-described method for suppressing the difference between the maximum in-plane temperature and the minimum temperature in the plane of the silicon wafer W to 7 ° C. or less from the size of the surface roughness distribution. It can be seen that the device configuration is reflected. First, the lowering of the surface roughness of the region C in the central portion of the wafer, that is, the lowering of the temperature was suppressed because the vertical pins abutting on the back surface of the central portion of the susceptor were omitted, and the output of the inner infrared lamp 9b was changed to the outer side. This is a result that is larger than the output of the infrared lamp 9a. The reason that the region A is relatively reduced is that the contact position of the vertical pin 7b at the end of the spoke 7 is closer to the outer peripheral side than before. Further, the reason that the region B became unclear was
This is because the distance d2 between the susceptor and the spoke has been increased as compared with the related art. Further, the region D has disappeared because the SiC base material having a lower thermal conductivity than the conventional graphite base material is used as a constituent material of the lift pins 8.

In the above-described apparatus, it is also effective to increase the distance d2 between the susceptor and the spokes and to decenter the spatial center axis of the infrared lamp assembly with respect to the rotation axis 6 of the susceptor. FIG. 7 shows a configuration example of such a vapor phase thin film growth apparatus. The basic configuration of the vapor phase thin film growth apparatus 11 shown in this figure is almost the same as that of the vapor phase thin film growth apparatus 10 shown in FIG. 4, but the susceptor-spoke distance d2 is larger than d1. Further, the axis X1 of the rotating shaft 6 does not coincide with the center axis X2 of the assembly of the infrared lamps 9a and 9b. With this configuration, it is possible to further uniform the surface roughness distribution of the silicon epitaxial wafer.

According to the manufacturing method of the present invention, since the vapor phase growth can be performed within the range of the temperature difference that can ensure a substantially uniform growth rate even when viewed locally, it is caused by a local temperature change. It is possible to manufacture a silicon epitaxial wafer having no local change in film thickness or flatness. In other words, the variation in the film thickness in the wafer caused by the manufacturing method of the present invention is substantially caused only by the in-plane distribution of the supply amount of the source gas, and therefore, the in-plane variation of the surface roughness of the silicon epitaxial layer is caused. After optimizing the temperature distribution of the silicon wafer so that the distribution is suppressed to 0.02 ppm or less, a silicon epitaxial wafer having a more uniform film thickness can be manufactured by appropriately adjusting the supply amount of the source gas. . For example, the aforementioned FIG. 10 showing a conventional silicon epitaxial wafer EW
In FIG. 3, the film thickness distribution, which was about 0.4 μm in the wafer plane, was improved to half, about 0.2 μm, by the manufacturing method of the present invention, as shown in FIG.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.
For example, the shape of the support means and the lift means, the number of spokes branched from the tip of the rotating shaft, the diameter of the silicon wafer to be used, the conditions of silicon epitaxial growth, and the details of the configuration of the vapor phase thin film growth apparatus are appropriately changed and selected. , Combinations are possible.

[0039]

As is apparent from the above description, in the vapor phase thin film growth apparatus of the present invention, the support means is improved in shape and size, and the relative position with respect to the heating means is changed as necessary. As a result, the temperature distribution of the susceptor due to radiant heat from the heating means is optimized, thereby improving the surface roughness uniformity of the silicon epitaxial layer on the silicon wafer placed on the susceptor,
The flatness and the in-plane distribution of the film thickness are improved. The present invention is a technology for improving the practical performance of a single-wafer-type vapor-phase thin film growth apparatus, which is expected to become mainstream with an increase in the diameter of a silicon wafer, and is particularly effective for producing a high-quality silicon epitaxial wafer. Therefore, the industrial value in the semiconductor manufacturing field is extremely high.

[Brief description of the drawings]

FIG. 1 is a graph showing a relationship between a surface roughness of a silicon epitaxial layer and a vapor phase growth temperature.

FIG. 2 is a chart showing an in-plane distribution of surface roughness of a silicon epitaxial layer of the silicon epitaxial wafer of the present invention.

3A and 3B are diagrams showing a film thickness distribution of a silicon epitaxial layer of a silicon epitaxial wafer of the present invention, and FIG. 3A is a plan view of a wafer for explaining a measurement direction;
(B) Figure shows film thickness distribution along the lateral diameter of the wafer,
(C) shows the film thickness distribution along the vertical diameter of the wafer.

FIG. 4 is a schematic sectional view showing a configuration example of a vapor phase thin film growth apparatus usable in the present invention.

FIG. 5 is a schematic sectional view showing a part of the vapor phase thin film growth apparatus of FIG. 4 in an enlarged manner.

6 is a plan view of the susceptor of the vapor phase thin film growth apparatus of FIG. 4 as viewed from the back.

FIG. 7 is a schematic sectional view showing an example in which the distance between a susceptor and a spoke of the vapor phase thin film growth apparatus of FIG. 4 is increased.

FIG. 8 is a schematic cross-sectional view showing a state of use during vapor phase growth in a typical configuration example of a conventional vapor phase thin film growth apparatus.

FIG. 9 is a schematic sectional view showing a state in which a silicon wafer is lifted from a susceptor using lift pins in a typical configuration example of a conventional vapor phase thin film growth apparatus.

FIG. 10 is a diagram showing a film thickness distribution of a silicon epitaxial layer of a conventional silicon epitaxial wafer;
(A) Figure is a plan view of the wafer for explaining the measurement direction,
(B) Figure shows film thickness distribution along the lateral diameter of the wafer,
(C) shows the film thickness distribution along the vertical diameter of the wafer.

FIG. 11 is a chart showing an in-plane distribution of surface roughness of a silicon epitaxial layer of a conventional silicon epitaxial wafer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reaction container 1a Upper space (of reaction container) 1b Lower space (of reaction container) 5 Susceptor 5a Counterbore 5c, 5d Concave portion (on the back of susceptor) 7 Spoke 7b Vertical pin 8 Lift pin 9 Infrared lamp 10, 11 Gas-phase thin film Growth device W Silicon wafer EW Silicon epitaxial wafer d1 Peripheral edge-vertical pin distance d2 Susceptor-spoke distance X1 Axis line (of rotary shaft 6) X2 (Spatial axis of infrared lamp assembly)

Claims (10)

[Claims] 1. An in-plane surface roughness calculated by excluding measured values within 0.3% of a cumulative frequency from the upper end and the lower end, respectively, of all the surface roughness measured by a laser scattered light detection method. A silicon epitaxial wafer having a silicon epitaxial layer whose distribution is suppressed to 0.02 ppm or less. 2. The silicon epitaxial wafer according to claim 1, wherein said surface roughness has a substantially concentric in-plane distribution. 3. The silicon epitaxial wafer according to claim 1, wherein the thickness variation of the silicon epitaxial layer is substantially caused only by the in-plane distribution of the supply amount of the source gas. 4. A silicon epitaxial wafer in which a silicon wafer is mounted on a rotary susceptor horizontally supported in a reaction vessel, and a silicon epitaxial layer is vapor-grown on the silicon wafer while heating the silicon wafer. In the method for producing a silicon epitaxial layer, the measured values of the surface roughness measured by a laser scattered light detection method, excluding the measured values included within a cumulative frequency of 0.3% from the upper end side and the lower end side, respectively. A method for manufacturing a silicon epitaxial wafer, wherein the temperature distribution of the silicon wafer is optimized so that the calculated in-plane distribution of the surface roughness is suppressed to 0.02 ppm or less. 5. The susceptor is supported by bringing the ends of a plurality of support members radially branched from the tip of a vertical rotation shaft into contact with the back surface of a peripheral portion surrounding a mounting portion of the silicon wafer. The distance from the outer peripheral edge of the susceptor to the contact portion at the end of the support member,
5. The method for manufacturing a silicon epitaxial wafer according to claim 4, wherein the temperature drop at the wafer edge with respect to the maximum in-plane temperature of the silicon wafer mounted on the susceptor is set to a value that can be suppressed within 7 [deg.] C. 6. The distance between the back surface of the susceptor and the support member is set to a value corresponding to the temperature drop of the wafer edge with respect to the maximum in-plane temperature of the silicon wafer placed on the susceptor.
5. The method for producing a silicon epitaxial wafer according to claim 4, wherein the value is set to a value that can be suppressed to within ° C. 7. The method according to claim 5, wherein the heating of the silicon wafer is performed using a plurality of radiant heating lamps arranged symmetrically about a central axis eccentric from the rotation axis of the susceptor. A method for manufacturing a silicon epitaxial wafer according to claim 6. 8. The method for manufacturing a silicon epitaxial wafer according to claim 4, wherein after optimizing the in-plane temperature distribution of the silicon wafer, the in-plane thickness distribution of the silicon epitaxial layer is adjusted. 9. The susceptor according to claim 4, wherein at the time of supporting the susceptor, one of a plurality of abutting portions between a peripheral edge of a back surface of the susceptor and the support member is used for positioning the susceptor. A method for manufacturing a silicon epitaxial wafer. 10. The method for manufacturing a silicon epitaxial wafer according to claim 4, wherein the vapor phase growth of the silicon epitaxial layer on the silicon wafer is performed in a single wafer mode.