JP2000101204A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2000101204A
JP2000101204A JP26635398A JP26635398A JP2000101204A JP 2000101204 A JP2000101204 A JP 2000101204A JP 26635398 A JP26635398 A JP 26635398A JP 26635398 A JP26635398 A JP 26635398A JP 2000101204 A JP2000101204 A JP 2000101204A
Authority
JP
Japan
Prior art keywords
conductive layer
frequency
signal line
wiring board
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26635398A
Other languages
Japanese (ja)
Other versions
JP3626354B2 (en
Inventor
Ayako Takagi
亜矢子 高木
Takeshi Miyagi
武史 宮城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP26635398A priority Critical patent/JP3626354B2/en
Publication of JP2000101204A publication Critical patent/JP2000101204A/en
Application granted granted Critical
Publication of JP3626354B2 publication Critical patent/JP3626354B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce EMI on a floating surface conductive layer. SOLUTION: As a shield layer, a conductive layer 4 of a thick resistor on a surface is arranged and the conductive layer 4 is not connected to any pattern inside a wiring board, so that the distribution of electric fields inside the board can be made smooth and high frequency noises can be reduced. Besides, the frequency of propagation signals on a high-speed signal line is transmitted but the EMI electromagnetic wave of its higher harmonic component can be shielded. A floating surface conductive layer 3 is formed through a dielectric film on high-speed signal wiring 1 and when the thickness of the conductive layer 3 is defined as (t), resistivity is defined as ρ, transmissivity is defined as μ and the frequency of a clock signal is defined as (f), these values are selected so as to satisfy an expression.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、EMI対策を施し
た配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board provided with EMI measures.

【0002】[0002]

【従来の技術】近年、パソコンが扱うデータが高精細画
像など大容量になり、処理能力の向上が望まれている。
そこで、CPUのクロック周波数が高速化が進み、周辺
のICへのバス配線やクロック線、データ線などが高速
かつ高密度になり、EMIが問題となってきている。
2. Description of the Related Art In recent years, the data handled by personal computers has become large, such as high-definition images, and it has been desired to improve the processing capability.
Therefore, the clock frequency of the CPU has been increased, and bus wiring, clock lines, data lines, and the like to peripheral ICs have been increased in speed and density, and EMI has become a problem.

【0003】EMI低減の手段として、回路基板表面に
金属や磁性体などの膜を施すことにより、電磁波シール
ドを行う方法が公知であるが、その構造について次に示
す。
As a means for reducing EMI, a method of shielding electromagnetic waves by applying a film such as a metal or a magnetic material on the surface of a circuit board is known, and the structure thereof will be described below.

【0004】図19に示されるのように、プリント基板
上に感光性ソルダレジスト膜を形成した後、所定の場所
にシールド導電膜を形成する構造がある(特開平2―9
8192)。また、図20に示されるのように、プリン
ト基板完成後に電源電位に落とした銅箔等の導電体を貼
りあわせたことを特徴とするプリント配線基板がある
(特開平2―249290)。これは、図20は、図1
9のようにシールド膜と回路基板が一体となって形成さ
れるのではなく、導電体を後で貼りあわせることによ
り、布線の配設、修正等が容易にできる利点がある。図
19、図20とも導電体を表面に配置することにより、
低周波から高周波まですべての周波数帯の電界シールド
が実現される。
As shown in FIG. 19, there is a structure in which after forming a photosensitive solder resist film on a printed circuit board, a shield conductive film is formed at a predetermined place (Japanese Patent Laid-Open No. 2-9).
8192). Further, as shown in FIG. 20, there is a printed wiring board in which a conductor such as a copper foil dropped to a power supply potential after the printed board is completed is bonded (Japanese Patent Laid-Open No. 2-249290). This is shown in FIG.
Rather than forming the shield film and the circuit board integrally as in 9, there is an advantage that the wiring can be easily arranged and corrected by bonding the conductor later. By arranging the conductor on the surface in both FIGS. 19 and 20,
Electric field shielding in all frequency bands from low frequency to high frequency is realized.

【0005】また、図21に示されるのように、導体に
より回路形成された絶縁基板上にフェライト層を形成す
ることで電磁波ノイズの放射を抑える構造がある(特開
平3―255698号)。これは、図19、図20と異
なり、磁界を吸収する磁界シールドとなる。
Further, as shown in FIG. 21, there is a structure in which a ferrite layer is formed on an insulating substrate on which a circuit is formed by a conductor to suppress radiation of electromagnetic wave noise (Japanese Patent Laid-Open No. 3-256598). This is a magnetic field shield that absorbs a magnetic field, unlike FIGS.

【0006】さらに、図22に示されるのように、基板
周辺の側面部を導電性膜でお覆うことにより、側面から
の電磁波放射を低減できる(特開平7―235776
号)。この構造は信号線からの電磁界ノイズだけでな
く、電源―グラウンドの層間の高周波ノイズの放射を抑
えるのに有効である。
Further, as shown in FIG. 22, by covering the side surface around the substrate with a conductive film, electromagnetic wave radiation from the side surface can be reduced (Japanese Patent Laid-Open No. Hei 7-235776).
issue). This structure is effective in suppressing not only the electromagnetic field noise from the signal line but also the emission of high-frequency noise between the power supply and ground layers.

【0007】図19、図20のような導体シールド層は
信号線層と近接しているので、高速信号線はシールド膜
を考慮したストリップラインのような構造で特性インピ
ーダンスを設計しなければならない。ストリップライン
は外部に電磁波を出さないが、低インピーダンス配線と
なり、誘電体内に電界が集中することにより、電界強度
分布が急峻になり高周波ノイズが発生しやすい。
Since the conductor shield layer as shown in FIGS. 19 and 20 is close to the signal line layer, the characteristic impedance of the high-speed signal line must be designed in a strip line-like structure in consideration of the shield film. Although the strip line does not emit electromagnetic waves to the outside, it becomes a low impedance wiring, and the electric field concentrates in the dielectric, so that the electric field intensity distribution becomes steep and high frequency noise is likely to occur.

【0008】さらに、図21に示されるのように、導体
により回路形成された絶縁基板上にフェライト層を形成
することで電磁波ノイズの放射を抑える構造がある(特
開平3―255698号)。本構造は導電体のシールド
ではなく、磁性体のシールドであり電磁波を吸収する
が、ストリップラインのように低インピーダンス配線で
はないので上記問題は生じない。しかし、フェライトは
高価であり、信号線の直近にあると高速信号線の波形の
劣化を起こす可能性がある。
Further, as shown in FIG. 21, there is a structure that suppresses the emission of electromagnetic wave noise by forming a ferrite layer on an insulating substrate on which a circuit is formed by conductors (Japanese Patent Application Laid-Open No. 3-256598). Although this structure is not a shield of a conductor but a shield of a magnetic material and absorbs electromagnetic waves, the above problem does not occur because it is not a low impedance wiring like a strip line. However, ferrite is expensive, and there is a possibility that the waveform of the high-speed signal line will be deteriorated if the ferrite is in the immediate vicinity of the signal line.

【0009】さらに、図22に示されるのように、基板
周辺の側面部を導電性膜でお覆うことにより、側面から
の電磁波放射を低減できる(特開平7―235776
号)。この構造は信号線だけでなく、電源グラウンド間
のスイッチングノイズなどの高周波ノイズの放射を抑え
るのに有効である。しかし、上記のように電磁波を金属
筐体内に閉じ込めることにより、プリント基板内での電
磁波の乱反射が起こり、その影響がケーブルを介して外
部に放射する可能性がある。
Further, as shown in FIG. 22, by covering the side surface around the substrate with a conductive film, the electromagnetic wave radiation from the side surface can be reduced (Japanese Patent Laid-Open No. 7-235776).
issue). This structure is effective for suppressing radiation of high-frequency noise such as switching noise between power supply grounds as well as signal lines. However, by confining the electromagnetic waves in the metal housing as described above, irregular reflection of the electromagnetic waves in the printed circuit board occurs, and the effect may be radiated to the outside via a cable.

【0010】[0010]

【発明が解決しようとする課題】従来、電磁波シールド
としてはなるべく導電率、透磁率の高い材料が効率がよ
いとされてきた。しかし、銅、アルミニウム、銀などの
導電率の高い材料を用いると配線基板内の信号線より発
生した電界はほぼ回路基板内に反射するので、基板内の
電界分布が急峻になり、高周波ノイズが大きくなる可能
性がある。そこで、シールド層として、EMIとしては
問題が小さいが、伝播信号としては重要な高速信号線の
周波数fの電磁波はある程度外部に透過するようにし
て、基板内部の電界分布をゆるやかにすることは、基板
内の高周波ノイズを低減するにの有効である。EMIの
周波数帯は、実際に基板内を走っている信号線の周波数
の高調波成分が問題になる場合がよくある。
Heretofore, it has been considered that a material having high conductivity and high magnetic permeability is effective as an electromagnetic wave shield. However, if a material with high conductivity such as copper, aluminum, or silver is used, the electric field generated from the signal lines in the wiring board is almost reflected into the circuit board, so that the electric field distribution in the board becomes sharp and high frequency noise is reduced. Can be large. Therefore, as a shield layer, although the problem is small as EMI, but as a propagation signal, an electromagnetic wave having a frequency f of a high-speed signal line is transmitted to the outside to some extent so that the electric field distribution inside the substrate is moderated. This is effective in reducing high-frequency noise in the substrate. In the EMI frequency band, a problem often arises of a harmonic component of the frequency of the signal line actually running in the substrate.

【0011】一般に導電層のシールド効果として、表皮
の厚さより膜厚が薄い場合は電磁波が通過するが、表皮
の厚さより膜厚が厚い場合は電磁波が通過しないといわ
れている。
Generally, as a shielding effect of the conductive layer, it is said that when the film thickness is thinner than the skin, the electromagnetic wave passes, but when the film thickness is thicker than the skin, the electromagnetic wave does not pass.

【0012】表皮の厚さは次のように表される。The thickness of the skin is expressed as follows.

【0013】[0013]

【数2】 表皮の厚さは、(1)式より、抵抗率が小さければ小さ
いほど、また、周波数が高ければ高いほど、薄くなる。
そこで、ある抵抗である厚さの導電層を表面に配置すれ
ば、ある周波数以上の電磁波は透過するが、その周波数
以下の電磁波は通過しないという現象が起きる。そこ
で、所望の周波数の信号線に関して、その信号線の周波
数の電磁波は表面導電層より外部にある程度透過する
が、その高調波である不要電磁波(EMI)は透過せず
に吸収する導電層の抵抗率と厚みを選択すれば、EMI
低減には有効である。
(Equation 2) According to equation (1), the thickness of the skin becomes smaller as the resistivity becomes smaller and as the frequency becomes higher.
Therefore, if a conductive layer having a certain resistance and a thickness is disposed on the surface, a phenomenon occurs in which electromagnetic waves of a certain frequency or more are transmitted, but electromagnetic waves of a certain frequency or less are not transmitted. Therefore, with respect to a signal line of a desired frequency, the electromagnetic wave of the frequency of the signal line is transmitted to the outside to some extent from the surface conductive layer, but the unnecessary electromagnetic wave (EMI), which is its harmonic, is absorbed without being transmitted. If you select the rate and thickness, EMI
It is effective for reduction.

【0014】従来、EMI対策として高周波信号線のデ
ジタル波に関して、抵抗を直列に通して波形の立ち上が
りをなまらせ、高周波ノイズを低減する方法がとられて
いる。これに関しても、マイクロストリップ線路の上部
にある抵抗をもった導電層を形成することにより、波形
をなまらせ、高周波ノイズを低減するという効果もあ
る。
Conventionally, as a countermeasure against EMI, a method of reducing the high frequency noise by passing a resistor in series with a digital wave of a high frequency signal line to smooth the rising of the waveform has been adopted. Also in this regard, by forming a conductive layer having a resistance above the microstrip line, there is an effect that the waveform is smoothed and high-frequency noise is reduced.

【0015】[0015]

【課題を解決するための手段】請求項1に記載の本発明
の配線基板は、高速信号配線上に誘電体膜を介して、フ
ローティングにした表面導電層を形成し、該表面導電層
の抵抗率ρ、厚さtを制御することにより、電磁波を選
択的にシールドすることを特徴とする。
According to a first aspect of the present invention, there is provided a wiring board according to the present invention, wherein a floating surface conductive layer is formed on a high-speed signal wiring via a dielectric film, and the resistance of the surface conductive layer is reduced. By controlling the ratio ρ and the thickness t, electromagnetic waves are selectively shielded.

【0016】請求項2に記載の本発明の配線基板は、高
速信号配線上に誘電体膜を介して、フローティングにし
た表面導電層を形成し、かつ、該導電層の厚さtは抵抗
率をρ、透磁率をμ、クロック周波数をfとすると
According to the second aspect of the present invention, a floating surface conductive layer is formed on a high-speed signal wiring via a dielectric film, and the thickness t of the conductive layer is a resistivity. Is ρ, permeability is μ, and clock frequency is f.

【数3】 とすることにより、クロック周波数fより高周波側の電
磁波がシールドされることを特徴とする。
(Equation 3) Thus, the electromagnetic wave on the higher frequency side than the clock frequency f is shielded.

【0017】請求項3に記載の本発明の配線基板は、前
記表面導電層が高速信号線の直上から前記信号線の幅の
2倍以上離した位置に配することを特徴とする。
According to a third aspect of the present invention, in the wiring substrate, the surface conductive layer is disposed at a position at least twice the width of the signal line from immediately above the high-speed signal line.

【0018】請求項4に記載の本発明の配線基板は、前
記導電層を配線基板の周端部に形成することを特徴とす
る。
According to a fourth aspect of the present invention, in the wiring substrate, the conductive layer is formed at a peripheral end of the wiring substrate.

【0019】[0019]

【発明の実施の形態】以下に本発明の実施の形態を実施
例により詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

【0020】まず図1に、本発明の実施例である配線基
板の断面図を用いて、従来の配線基板と比較することに
より説明する。次の3種類の場合を比較した電界分布の
シミュレーションを行った。
First, FIG. 1 will be described by using a cross-sectional view of a wiring board according to an embodiment of the present invention in comparison with a conventional wiring board. A simulation of the electric field distribution was performed by comparing the following three cases.

【0021】A.図1において、信号線1の上部の誘電
体膜上に導電層がない場合、 B.図1において、信号線1の上部の誘電体上に銅など
の低抵抗の導電層が存在し、グラウンド電位に落ちてい
る場合、 C.図1において、信号線1の上部の誘電体上にある抵
抗をもった導電層が存在し、電位がどこにもつながって
いない場合。
A. 1. In FIG. 1, when there is no conductive layer on the dielectric film above signal line 1, B. In FIG. 1, when a low-resistance conductive layer such as copper exists on the dielectric above the signal line 1 and drops to the ground potential, In FIG. 1, a case where a conductive layer having resistance is present on a dielectric above the signal line 1 and the potential is not connected anywhere.

【0022】Aの場合、図2に信号線の端部を層に垂直
方向に切ったα―α' の電界分布と図3にグラウンドの
端部を層に垂直方向に切ったβ―β' の電界分布を示
す。同様に、Bの場合、図4に信号線の端部を層に垂直
方向に切ったα―α' の電界分布と図5にグラウンドの
端部を層に垂直方向に切ったβ―β' の電界分布を示
す。最後にCの場合、図6に信号線の端部を層に垂直方
向に切ったα―α' の電界分布と図7にグラウンドの端
部を層に垂直方向に切ったβ―β' の電界分布を示す。
In the case of A, FIG. 2 shows the electric field distribution of α-α ′ in which the end of the signal line is cut perpendicular to the layer, and FIG. 3 shows the β-β ′ in which the end of ground is cut perpendicular to the layer. 5 shows the electric field distribution of FIG. Similarly, in the case of B, FIG. 4 shows the electric field distribution of α-α ′ with the end of the signal line cut perpendicular to the layer, and FIG. 5 shows the β-β ′ with the end of ground cut perpendicular to the layer. 5 shows the electric field distribution of FIG. Finally, in the case of C, FIG. 6 shows the electric field distribution of α-α ′ with the end of the signal line cut perpendicular to the layer, and FIG. 7 shows the β-β ′ with the end of ground cut perpendicular to the layer. 4 shows an electric field distribution.

【0023】これらより図2、図3において、信号線層
1の部分で電界分布が急峻な変化を示していることがわ
かる。次に、図4において、表面にグラウンド電位に落
ちた導体層があることにより、誘電体3での電界強度が
10倍近くにも増大することがわかった。最後に、表面
にどの電位にも落ちていないある抵抗を持った導電層が
あることにより、図6、図7より、信号線部も、グラウ
ンド部もゆるやかな電界分布であることがわかった。電
界分布がゆるやかであることにより、信号線部やグラウ
ンド面にノイズが発生しても、周囲への影響が小さい。
2 and 3 that the electric field distribution shows a steep change in the signal line layer 1 portion. Next, in FIG. 4, it was found that the presence of the conductor layer having a ground potential on the surface increased the electric field intensity in the dielectric 3 by nearly 10 times. Finally, since the surface has a conductive layer having a certain resistance which has not dropped to any potential, it can be seen from FIGS. 6 and 7 that the signal line portion and the ground portion have a gentle electric field distribution. Since the electric field distribution is gentle, even if noise is generated in the signal line portion or the ground plane, the influence on the surroundings is small.

【0024】次に、図1の導電層3の抵抗率を変化させ
た時の本発明への適用条件を調べる。
Next, the conditions applied to the present invention when the resistivity of the conductive layer 3 in FIG. 1 is changed will be examined.

【0025】図8に銅、アルミニウム、黄銅、チタンの
場合の表皮の厚さの周波数依存性を計算した結果を示
す。図8から、抵抗率が低い銅やアルミニウムなどは、
厚みが20μm 程度あれば、20MHz以上のすべての
周波数帯をシールドすることが可能であることがわか
る。しかし、抵抗率がある程度高いチタンは、厚みが2
0μm では、20MHzの周波数の電磁波は通すが50
0MHz以上の高周波は通さないという選択ができるよ
うになる。
FIG. 8 shows the results of calculating the frequency dependence of the skin thickness in the case of copper, aluminum, brass, and titanium. From FIG. 8, copper or aluminum with low resistivity is
It can be seen that if the thickness is about 20 μm, it is possible to shield all the frequency bands above 20 MHz. However, titanium having a relatively high resistivity has a thickness of 2
At 0 μm, electromagnetic waves with a frequency of 20 MHz pass, but 50
It becomes possible to select not to pass a high frequency of 0 MHz or more.

【0026】実際に金属板のシールド効果を調べた実験
結果を図9に示す。アルミニウムのような低抵抗の金属
板では数10kHzから数10MHzまでシールド効果
は変化しないが、チタンのような抵抗を持った金属では
数100kHzからシールド効果が低減することがわか
る。これらの現象を配線基板の断面図で説明すると、低
周波側では図10のように信号線の電界が導電層を通過
するが、高周波側では図11のように信号線の電界が導
電層を通過せずにシールドされている。
FIG. 9 shows an experimental result of actually examining the shielding effect of the metal plate. It can be seen that the shielding effect does not change from tens of kHz to tens of MHz with a low-resistance metal plate such as aluminum, but the shielding effect decreases from several hundred kHz with a metal having resistance such as titanium. To explain these phenomena in a cross-sectional view of the wiring board, the electric field of the signal line passes through the conductive layer on the low frequency side as shown in FIG. 10, but the electric field of the signal line passes through the conductive layer on the high frequency side as shown in FIG. Shielded without passing.

【0027】図12にクロック周波数が矩形波である時
の、基本波の周波数fとその高調波の周波数3f、5f
の表面の電流密度Jを1とした時の導電層内での電流密
度の減衰の様子を表す。
In FIG. 12, when the clock frequency is a rectangular wave, the frequency f of the fundamental wave and the frequencies 3f, 5f of its harmonics are shown.
2 shows how the current density in the conductive layer attenuates when the current density J on the surface is 1.

【0028】表面からの深さを、(1)式の表皮の厚さ
の式を用いて、
The depth from the surface is calculated by using the expression of the thickness of the skin in the expression (1),

【数4】 とした時に、基本波の電流密度は0.37<J<0.47 となる
が、高調波3fの電流密度は0.17<J<0.27 、高調波5f
の電流密度は0.11<J<0.19 となり、基本波の電磁波は4
0%前後表面導電層を透過して外部に漏洩するが、高調
波は電磁波の漏洩が25%以下に減衰していることがわ
かる。これらより、導電層の厚さtが表皮の厚さδの3
/4以上1以下になると、信号線の周波数fの電磁波は
ある程度透過し、それ以上の高周波に対してシールドを
行う導電層が実現できる。
(Equation 4) Then, the current density of the fundamental wave is 0.37 <J <0.47, but the current density of the harmonic 3f is 0.17 <J <0.27, and the harmonic 5f
Has a current density of 0.11 <J <0.19, and the fundamental electromagnetic wave is 4
It can be seen that the leakage of the electromagnetic waves is reduced to 25% or less for the higher harmonics, though the light passes through the surface conductive layer around 0% and leaks to the outside. From these, the thickness t of the conductive layer is 3 times the thickness δ of the skin.
When the value is equal to or more than / 4 and equal to or less than 1, the electromagnetic wave having the frequency f of the signal line is transmitted to some extent, and a conductive layer that shields a higher frequency than that can be realized.

【0029】実際にマイクロストリップ線路に矩形波信
号を入力して、Cu,Ti、SUSの金属をフローティ
ングにして配線上に置き、その近傍磁界を測定した。そ
の時、それぞれの金属板のシールド効果を、同一配線長
で、搭載されるプリント基板の大きさが異なるもの(基
板A、B、C;大きさA<B<C)について調べた結果
について図13に示す。
A rectangular wave signal was actually input to the microstrip line, Cu, Ti, and SUS metals were floated and placed on the wiring, and the magnetic field in the vicinity was measured. At this time, FIG. 13 shows a result of examining the shielding effect of each metal plate on the printed wiring boards having the same wiring length and different sizes (substrates A, B, and C; sizes A <B <C). Shown in

【0030】シールドが無い場合、基板が大きくなると
放射ノイズが大きくなることがわかる。これは、近傍磁
界が配線上だけでなく、プリント基板内の電源グラウン
ド層での共振によって生じているためである。また、図
13より、マイクロストリップ線路上にTiをおいた場
合、Cu,SUSよりシールド効果が高いことが実証で
きた。これは、図8よりTiはCu,Ti、SUSの中
で表皮厚さが最も厚く、板厚tに近いため、クロック信
号は透過するが、その高調波成分は透過せず、また、基
板内への反射がCuより小さいので配線基板内の電界分
布がゆるやかになり、放射ノイズが低減したためであ
る。
It can be seen that when there is no shield, radiation noise increases as the size of the substrate increases. This is because the near magnetic field is generated by resonance not only on the wiring but also on the power supply ground layer in the printed circuit board. Also, from FIG. 13, it was demonstrated that when Ti was placed on the microstrip line, the shielding effect was higher than that of Cu and SUS. This is because, as shown in FIG. 8, Ti has the largest skin thickness among Cu, Ti, and SUS and is close to the plate thickness t, so that the clock signal is transmitted, but its harmonic component is not transmitted, and This is because the electric field distribution in the wiring substrate becomes gentle because the reflection to Cu is smaller than Cu, and the radiation noise is reduced.

【0031】そこで、(2)式より、高周波成分をシー
ルドしたい信号線に関して、導電層の厚みtと抵抗率ρ
の関係を示す。例として、図14に、60MHz,20
0MHz、1GHzの時の信号線の周波数において、そ
の信号線の周波数以下の電磁波は透過するが、その信号
線の周波数以上の電磁波は透過しないシールド導電層を
実現するための抵抗率と抵抗体の厚みの関係を示す。
(2)式の範囲を図14の斜線部分で示す。図14よ
り、例えば信号線の周波数が60MHzの場合、抵抗率
が10×10-8の時は、厚みを15μm から20μm 程
度にすればよいことがわかる。
Therefore, according to the equation (2), the thickness t of the conductive layer and the resistivity ρ
Shows the relationship. As an example, FIG.
At the frequency of the signal line at 0 MHz and 1 GHz, the electromagnetic wave below the frequency of the signal line is transmitted, but the electromagnetic wave above the frequency of the signal line is not transmitted. The relationship of thickness is shown.
The range of expression (2) is shown by the hatched portion in FIG. From FIG. 14, it can be seen that, for example, when the frequency of the signal line is 60 MHz, and when the resistivity is 10 × 10 −8 , the thickness may be about 15 μm to about 20 μm.

【0032】次に、図1の回路基板の断面図において、
信号線と外部シールド膜との間の誘電体3の厚みuを変
化させた時、ケースA、B,Cの場合の最大電界強度の
シミュレーション結果について図15に示す。ケース
A、B,Cの場合とも、誘電体3の厚みが厚くなればな
るほど最大電界強度が小さくなり、基板内での高周波ノ
イズが小さくなることが予想される。しかし、誘電体3
の膜厚が内層誘電体9の厚みの1/2以上になると最大
電界強度の低減効果がわずかであることがわかる。
Next, in the sectional view of the circuit board of FIG.
FIG. 15 shows a simulation result of the maximum electric field intensity in cases A, B, and C when the thickness u of the dielectric 3 between the signal line and the external shield film is changed. In the cases A, B, and C, it is expected that the thicker the dielectric 3, the lower the maximum electric field intensity and the lower the high-frequency noise in the substrate. However, dielectric 3
It can be seen that the effect of reducing the maximum electric field intensity is small when the film thickness of is 1 / or more of the thickness of the inner dielectric material 9.

【0033】高周波のアナログ信号とデジタル信号が近
接して配置されていうような場合などで、高周波を波形
の劣化を小さく抑えたい場合は、図16のように表面導
電層を信号線の誘電体膜を介した直上部ではなく、直上
から信号線の幅の2倍以上離した位置に配することによ
り、信号線に発生する電界には影響なく、EMIだけを
ある程度シールドすることができる。
In a case where high-frequency analog signals and digital signals are arranged close to each other, for example, when it is desired to suppress the deterioration of high-frequency waveforms, as shown in FIG. By arranging the EMI at a position at least two times the width of the signal line from immediately above, rather than directly above, the EMI can be shielded to some extent without affecting the electric field generated in the signal line.

【0034】また、図14より、抵抗率ρと厚さtの関
係がわかったが、所望の抵抗率と所望の導電層の厚さt
を実現するために、図17、図18のように複数の金属
を層状に形成することにより、ある周波数f以上の電磁
波はシールドするが、その周波数以下の電磁波は透過す
るという導電層を形成する。
FIG. 14 shows the relationship between the resistivity ρ and the thickness t. The desired resistivity and the desired thickness t of the conductive layer are obtained.
17 and 18, by forming a plurality of metals in layers as shown in FIGS. 17 and 18, a conductive layer is formed that shields electromagnetic waves of a certain frequency f or higher but transmits electromagnetic waves of a certain frequency or lower. .

【0035】最後に、図19のように、配線基板におい
て層間のコモンモードノイズなどの高周波ノイズを低減
するために、上記表面導電層を配線基板の周端部に形成
することによりシールドをすることができる。
Lastly, as shown in FIG. 19, in order to reduce high-frequency noise such as common mode noise between layers in the wiring board, the surface conductive layer is formed at the peripheral end of the wiring board for shielding. Can be.

【0036】[0036]

【発明の効果】以上より、本発明によれば、配線基板内
部の電界強度が小さく、基板内に高周波ノイズが発生し
にくく、しかも、EMI低減ができる回路基板を提供す
ることができる
As described above, according to the present invention, it is possible to provide a circuit board in which the electric field strength inside the wiring board is small, high-frequency noise is hardly generated in the board, and EMI can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の一例を示す断面図である。FIG. 1 is a sectional view showing an example of a wiring board of the present invention.

【図2】図1において外部導体層がない場合の信号線端
部(α―α' )での電界分布図である。
FIG. 2 is an electric field distribution diagram at a signal line end (α-α ′) in the case where there is no external conductor layer in FIG.

【図3】図1において外部導体層がない場合のグラウン
ド端部(β―β' )での電界分布図である。
FIG. 3 is an electric field distribution diagram at a ground end (β-β ′) in the case where there is no external conductor layer in FIG. 1;

【図4】図1において外部導体層が低抵抗体でグラウン
ド電位につながっている場合の信号線端部(α―α' )
での電界分布図である。
FIG. 4 is a signal line end (α-α ′) in the case where the external conductor layer is a low resistance body and is connected to the ground potential in FIG.
FIG.

【図5】図1において外部導体層が低抵抗体でグラウン
ド電位につながっている場合のグラウンド端部(β―
β' )での電界分布図である。
FIG. 5 is a diagram illustrating a ground end portion (β−) when the external conductor layer is connected to the ground potential with a low resistance body in FIG.
FIG. 6 is an electric field distribution diagram at β ′).

【図6】図1において外部導体層がある低抵を持つ導体
でどの電位にもつながっていない場合の信号線端部(α
―α' )での電界分布図である。
FIG. 6 shows a signal line end (α) in the case where the external conductor layer is a conductor having a low resistance and is not connected to any potential in FIG.
-Α ').

【図7】図1において外部導体層がある低抵を持つ導体
でどの電位にもつながっていない場合のグラウンド端部
(β―β' )での電界分布図である。
FIG. 7 is an electric field distribution diagram at a ground end (β-β ′) in the case where the outer conductor layer in FIG. 1 is a conductor having a low resistance and not connected to any potential.

【図8】表皮の厚さの周波数依存性を示す図である。FIG. 8 is a diagram showing the frequency dependence of the thickness of the skin.

【図9】金属板によるシールド効果の周波数依存性を示
す図である。
FIG. 9 is a diagram illustrating frequency dependence of a shielding effect by a metal plate.

【図10】信号線の低周波成分の電界がある抵抗を持っ
た導電層を透過している状態を示す図である。
FIG. 10 is a diagram showing a state where an electric field of a low-frequency component of a signal line is transmitted through a conductive layer having a certain resistance.

【図11】信号線の高周波成分の電界がある抵抗を持っ
た導電層によってシールドされている状態を示す図であ
る。
FIG. 11 is a diagram showing a state where an electric field of a high frequency component of a signal line is shielded by a conductive layer having a certain resistance.

【図12】導電層内での電流密度の減少を示す図であ
る。
FIG. 12 is a diagram showing a decrease in current density in a conductive layer.

【図13】マイクロストリップ線路上の近傍界放射ノイ
ズ(実測値)を示す図である。
FIG. 13 is a diagram showing near-field radiation noise (actually measured values) on a microstrip line.

【図14】ある周波数f以上の電磁波に関してシールド
を行う時の表面の導電層の抵抗率と厚みの関係を示す図
である。
FIG. 14 is a diagram showing the relationship between the resistivity and the thickness of the conductive layer on the surface when shielding is performed for electromagnetic waves of a certain frequency f or more.

【図15】信号線と外部シールド膜との間の誘電体の厚
みと電界最大強度の関係を示す図である。
FIG. 15 is a diagram showing the relationship between the thickness of a dielectric between a signal line and an external shield film and the maximum electric field intensity.

【図16】本発明の配線基板の一例を示す断面図であ
る。
FIG. 16 is a cross-sectional view illustrating an example of a wiring board of the present invention.

【図17】本発明の配線基板の一例を示す断面図であ
る。
FIG. 17 is a cross-sectional view illustrating an example of the wiring board of the present invention.

【図18】本発明の配線基板の一例を示す断面図であ
る。
FIG. 18 is a cross-sectional view illustrating an example of the wiring board of the present invention.

【図19】本発明の配線基板の一例を示す断面図であ
る。
FIG. 19 is a cross-sectional view illustrating an example of the wiring board of the present invention.

【図20】従来の配線基板を示す断面図である。FIG. 20 is a sectional view showing a conventional wiring board.

【図21】従来の配線基板を示す断面図である。FIG. 21 is a sectional view showing a conventional wiring board.

【図22】従来の配線基板を示す断面図である。FIG. 22 is a cross-sectional view showing a conventional wiring board.

【図23】従来の配線基板を示す断面図である。FIG. 23 is a cross-sectional view showing a conventional wiring board.

【符号の説明】[Explanation of symbols]

1…信号配線、2…第1電源グラウンド層、3…表面誘
電体層、4…導電層、5…第2電源グラウンド層、6…
第3電源グラウンド層、7…第4電源グラウンド線(表
層)、8…空気、9…内層誘電体層、10…信号線、1
1…電気力線
REFERENCE SIGNS LIST 1 signal wiring 2 first power ground layer 3 surface dielectric layer 4 conductive layer 5 second power ground layer 6
Third power ground layer, 7: fourth power ground line (surface layer), 8: air, 9: inner dielectric layer, 10: signal line, 1
1. Electric lines of force

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 高速信号配線上に誘電体膜を介して、フ
ローティングにした表面導電層を形成し、該表面導電層
の抵抗率ρ、厚さtを制御することにより、電磁波を選
択的にシールドすることを特徴とする配線基板。
1. A floating surface conductive layer is formed on a high-speed signal wiring via a dielectric film, and by controlling the resistivity ρ and the thickness t of the surface conductive layer, electromagnetic waves can be selectively generated. A wiring board characterized by being shielded.
【請求項2】 請求項1記載の構造において、該表面導
電層の厚さtに関して、抵抗率をρ、透磁率をμ、クロ
ック周波数をfとすると 【数1】 の範囲とすることにより、クロック周波数fよりも高周
波側の電磁波がシールドされることを特徴とする配線基
板。
2. The structure according to claim 1, wherein, with respect to the thickness t of the surface conductive layer, the resistivity is ρ, the magnetic permeability is μ, and the clock frequency is f. Wherein the electromagnetic wave on the higher frequency side than the clock frequency f is shielded.
【請求項3】 該導電層は高速信号線の直上から信号線
の幅の2倍以上離した位置に配することを特徴とする請
求項1記載の配線基板。
3. The wiring board according to claim 1, wherein the conductive layer is disposed at a position separated from the position immediately above the high-speed signal line by at least twice the width of the signal line.
【請求項4】 該導電層を配線基板の周端部に形成する
ことを特徴とする請求項1記載の配線基板。
4. The wiring board according to claim 1, wherein said conductive layer is formed at a peripheral end of the wiring board.
JP26635398A 1998-09-21 1998-09-21 Wiring board Expired - Fee Related JP3626354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26635398A JP3626354B2 (en) 1998-09-21 1998-09-21 Wiring board

Publications (2)

Publication Number Publication Date
JP2000101204A true JP2000101204A (en) 2000-04-07
JP3626354B2 JP3626354B2 (en) 2005-03-09

Family

ID=17429772

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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