JP2000100832A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which has a wide output width, satisfactory linearity, and a large output. SOLUTION: 4 columns of FET units 19, 20, 21, and 22 are provided. Gate electrode 23, 26, 37, and 40 of the units are respectively connected from ends T1 and T2 of common gate feeding buses 29 and 43, via a common bus 50, to a gate pad 51. Similarly, source electrodes 24, 27, 38, and 41 are connected to source pads 31, 35, and 47, and drain electrodes 25, 28, 39, and 42 are connected to drain pads 33, 36, 45, and 49. Drain voltage can be selectively fed to the units, and the units have different gate widths langing from Lg1 to Lg4. Thus, due to the feeding of the drain voltage, outputs corresponding to gate widths of the units the selectively combined or synthesized, and the outputs are connected to the gate pad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for power amplification.

[0002]

2. Description of the Related Art In a conventional high-power semiconductor device, an electrode structure is generally used in which the number of unit gate electrodes is increased to increase the total gate width of the gate electrodes.

However, when increasing the number of unit gate electrodes, the length of the gate power supply bus connecting the unit gate electrodes in common must be increased. As a result, there is a problem that a propagation delay loss occurs due to an increase in resistance value and a phase shift.

[0004] For this reason, the applicant has proposed a semiconductor device in which this point is improved, that is, an FET 1 disclosed in Japanese Patent Application Laid-Open No. 5-251478. Next, referring to FIG.
The electrode structure of ET1 will be described.

The FET 1 has a plurality of FET units 2A,
2B, 2C, 2D, 2E, and 2F. In addition,
Each FET unit includes a plurality of unit cells 6 each including a unit gate electrode 3, a unit source electrode 4, and a unit drain electrode 5.

The adjacent FET units 2A, 2B and 2C
And 2D, 2E and 2F, the respective unit gate electrodes 3
They are connected to common gate power supply buses 7A, 7B and 7C, respectively. That is, a plurality of unit gate electrodes 3 of the FET unit 2A are formed at equal intervals on one side (for example, the left side in the drawing) of the common gate power supply bus 7A in the direction orthogonal to the direction of extension. You. Further, a plurality of unit gate electrodes 3 of the FET unit 2B are formed at equal intervals on the other side (for example, the right side in the drawing) of the common gate power supply bus 7A in the direction orthogonal to the direction of extension thereof. You. The gate width of the unit gate electrode 3 is all Lg.

The unit source electrode 4 and the unit drain electrode 5 of each FET unit are alternately formed so as to sandwich each unit gate electrode 3. The unit source electrode 4 and the unit drain electrode 5 of each unit cell 6 are set to substantially the same length as the gate width Lg of the unit gate electrode 3.

A plurality of common gate power supply buses 7A, 7B, 7
C are formed in parallel. Therefore, the FET units 2A, 2B, 2C, 2D, 2E, 2F are arranged in a horizontal row.

One end of each common gate power supply bus 7A, 7B, 7C is commonly connected to a common bus 8 for gate. Also,
A gate pad 9 for applying a gate voltage Vg to the unit gate electrode 3 is connected to the gate common bus 8.

In the FET unit, the inner adjacent F
The unit source electrodes 4 of the ET units 2B and 2C, 2D and 2E are commonly connected to the common source power supply buses 10A and 10B. Further, among the FET units, the unit source electrodes 4 of the outer FET units 2A and 2F are connected to the source power supply buses 11A and 11B. Common source power supply buses 10A and 10B and source power supply buses 11A and 11B
Are commonly connected to a source common bus 12. Source pads 13A and 13B as ground terminals are connected to one ends of the source power supply buses 11A and 11B, respectively.

Each unit drain electrode 5 is a drain feeder bus 14A, 14B, 14C, 14D, 14 which is an air-bridge wiring provided so as to straddle the unit source electrode 4.
E, 14F. Drain feed bus 14A, 1
One ends of 4B, 14C, 14D, 14E, and 14F are commonly connected to a common drain bus 15. A drain pad 16 is connected to the drain common bus 15.

In the FET 1, the current value of the drain current flowing from the unit source electrode 4 to the unit drain electrode 5 is equal to the gate current.
And is controlled by the voltage value of the trigger voltage Vg. Also, FET
The maximum output of 1 is determined by the voltage value of the drain voltage.

In the FET 1, the gain of each unit cell 6 of each FET unit is small. However, FET
The maximum output of 1 is proportional to the total gate width obtained by adding the gate widths of all the unit cells 6. Therefore, the maximum output of the FET 1 increases.

Further, even if the number of the unit gate electrodes 3 is increased, the length of the gate common bus 8 can be reduced. Therefore, since the distance does not greatly increase in the direction orthogonal to the signal propagation direction G, the phase difference generated between the unit gate electrodes can be minimized.

In the above, the semiconductor device has been described by taking the FET as an example. However, a microwave integrated circuit (M) having a circuit configuration including an active element and a passive element formed on a semiconductor substrate has been described.
MIC: Monolithic Microwave Integrated Circuit
Also has a similar electrode structure to the FET. Therefore, these are included in the semiconductor device. The material of the semiconductor device may be either gallium arsenide or silicon.

[0016]

However, in the conventional semiconductor device, the maximum output can be changed depending on the voltage value of the drain voltage Vd. However, as shown in FIG. 5, the horizontal axis represents the voltage value of the drain voltage Vd. There is a problem that the linearity of the characteristic curve 17 obtained when plotting and plotting the maximum output of the semiconductor device on the vertical axis is poor.
Therefore, when the maximum output of the semiconductor device is changed depending on the drain voltage Vd, a circuit for correcting linearity is required separately, and the circuit configuration is complicated.

In portable communication devices and the like, the capacity of a built-in power supply has been reduced year by year as the size of the device is reduced. For this reason, the rated voltage value of the power supply is reduced, and it is difficult to vary the voltage value of the drain voltage Vd in a wide range.
Therefore, there is a problem that the maximum output of the semiconductor device is fixed at a substantially constant level.

Further, when the maximum output of the semiconductor device is changed, it is necessary to newly design the shape or arrangement of the unit gate electrode, unit source electrode, unit drain electrode, etc., depending on the specifications. That is, there is a problem that the semiconductor device is custom-made, not only the cost is extremely high, but also it takes time to manufacture.

Therefore, an object of the present invention is to provide a semiconductor device for solving the above problem.

[0020]

The present invention is configured as follows to solve the above-mentioned problems. That is, a semiconductor device according to claim 1, comprising a unit gate electrode, and a unit drain electrode and a unit source electrode alternately formed so as to sandwich the unit gate electrode. A first common gate power supply bus having unit gate electrodes of adjacent field effect transistor units on both sides in a semiconductor device having four units arranged side by side;
A second common gate power supply bus having unit gate electrodes of adjacent field-effect transistor units on both sides; a second common gate power supply bus and the first common gate power supply bus; A gate pad to be connected and power supply means for supplying a drain voltage to each of the field effect transistor units are provided, and the total gate width of each of the field effect transistor units is set to a different length. In addition, a unit gate electrode having a shorter gate width than the outside is disposed inside the common gate power supply bus.

Each of the four field effect transistors
The total gate width of the unit is formed to different lengths. Therefore, the maximum output of each field effect transistor unit is different. Further, since a unit gate electrode having a smaller gate width than the outside is arranged in the region between the first and second common gate feeding buses, that is, inside, the first and second common gate feeding buses are arranged. The distance between the common gate power supply buses is the shortest. Therefore, the resistance value during this period becomes small. Furthermore, the power supply means can individually supply the drain voltage to each field effect transistor unit. Therefore, a field effect unit that supplies power and a field effect unit that does not supply power can coexist. As a result, the maximum output of the entire device can be changed by selecting the field effect unit to be fed.

In the semiconductor device according to the present invention, the ends of the first common gate power supply bus and the second common gate power supply bus are connected to the gate pads via the common bus. Things.

The gate voltage applied to the gate pad is supplied through a first common gate power supply bus or a second common gate power supply bus via a common bus.

In the semiconductor device according to the third aspect, the gate pad is provided at the center of the common bus.

By providing the gate pad at the center of the common bus, the distance from the gate pad to each common gate power supply bus becomes equal.

According to a fourth aspect of the present invention, the ends of the first common gate power supply bus and the second common gate power supply bus are directly connected to the gate pads.

The gate voltage applied to the gate pad is supplied directly from the gate pad via the first common gate power supply bus and the second common gate power supply bus. You.

[0028]

(Embodiment 1) A semiconductor device 18 according to the present invention will be described with reference to FIG.

The semiconductor device 18 includes four FET units 19, 20, 21, and 22.

The first FET unit 19 includes a plurality of unit cells each including a first unit gate electrode 23, a first unit source electrode 24, and a first unit drain electrode 25. The second FET unit 20 includes a unit cell including a second unit gate electrode 26, a second unit source electrode 27, and a second unit drain electrode 28, as described above. Have multiple.

The unit gate electrode 23 and the unit gate electrode 26
Are formed at equal intervals on both sides in the direction of extension of the first common gate power supply bus 29 extending linearly.
That is, the unit gate electrode 23 is formed in a comb shape on the left side in the drawing with respect to the common gate power supply bus 29. The unit gate electrode 26 is formed in a comb-like shape on the right side of the drawing with respect to the common gate power supply bus 29. The length of the gate width Lg1 of the unit gate electrode 23 is equal to that of the unit gate electrode 26.
Is longer than the length of the gate width Lg2 (Lg1).
> Lg2).

The unit source electrodes 24 and the unit drain electrodes 25 are alternately formed so as to sandwich the unit gate electrode 23. Therefore, in the adjacent unit cell in the first FET unit 19, a unit cell is formed by commonly using the unit source electrode 24 or the unit drain electrode 25. The unit source electrode 24 and the unit drain electrode 25 are set to have substantially the same length as the gate width Lg1 of the unit gate electrode 23.

The unit source electrode 24 is connected to the source electrode bus 3
0 is commonly connected. Further, the source electrode bus 30 is
It is connected to the source pad 31.

The unit drain electrode 25 is commonly connected to a drain power supply bus 32 having an air-bridge wiring portion formed so as to straddle the unit source electrode 24. This drain power supply bus 32 is connected to a drain pad 33.

The unit source electrodes 27 and the unit drain electrodes 28 are alternately formed so as to sandwich the unit gate electrode 26 in the same manner as described above. In this case, the unit source
The source electrode 27 and the unit drain electrode 28 are set to have substantially the same length as the gate width Lg2 of the unit gate electrode 26.

The unit source electrode 27 is commonly connected to a common source electrode bus 34. This common source electrode bus 34
Are connected to the source pad 35.

The unit drain electrode 28 is, as described above,
It is commonly connected to a drain power supply bus (not shown) having an air-bridge wiring portion formed so as to straddle the unit source electrode 27. The drain power supply bus is connected to the drain pad 36.

The third FET unit 21 is a second FET
Similarly to the electrode structure of the unit 20, the fourth FET
The unit 22 is formed similarly to the electrode structure of the first FET unit 19. Therefore, the description will be simplified.

The third FET unit 21 includes a plurality of unit cells each including a third unit gate electrode 37, a third unit source electrode 38, and a third unit drain electrode 39. Similarly, the fourth FET unit 22 includes a plurality of unit cells each including a fourth unit gate electrode 40, a fourth unit source electrode 41, and a fourth unit drain electrode 42.

The unit gate electrode 37 and the unit gate electrode 40
Are formed on both sides of the second common gate power supply bus 43 in the direction of extension. The length of the gate width Lg3 of the unit gate electrode 37 is equal to the gate width Lg of the unit gate electrode 40.
It is shorter than the length of g4 (Lg3 <Lg4).
However, as a whole semiconductor device, of the four FET units, the second FET unit 20 is the smallest and the first FET unit 19 is the largest (Lg2 <Lg3).
<Lg4 <Lg1).

The unit source electrodes 38 and the unit drain electrodes 39 are alternately formed so as to sandwich the unit gate electrode 37. The unit source electrode 38 and the unit drain electrode 39 are formed by the gate width Lg of the unit gate electrode 37.
The length is set to almost the same as 3.

The unit source electrode 38 is commonly connected to the common source electrode bus 34. Also, the unit drain electrode 39
Are commonly connected to a drain power supply bus 44. The drain power supply bus 44 is connected to the drain pad 45.

As described above, the unit source electrode 41 and the unit drain electrode 42 are arranged so that the unit gate electrode 40 is interposed therebetween.
They are arranged alternately. The unit source electrode 41 and the unit drain electrode 42 have a gate width L of the unit gate electrode 40.
The length is set to be substantially the same as g4.

The unit source electrode 41 is connected to the source electrode bus 4
6 are commonly connected. Further, the source electrode bus 46 is
Connected to source pad 47. The unit drain electrode 42 is commonly connected to a drain power supply bus 48.
The drain power supply bus 48 is connected to the drain pad 49.

FET units 19, 20, 21, 22
Are arranged such that the common gate power supply buses 29 and 43 are parallel to each other. As a result, as shown in FIG. 1, the FET units 19, 20, 21, and 22 are arranged in a horizontal row.

The end T1 of the common gate power supply bus 29 and the end T2 of the common gate power supply bus 43 are connected by a common bus 50. The common bus 50 has an end T1 and an end T
A gate pad 51 is connected to an intermediate point of the two. Therefore, the distance from the gate pad 51 to the end T1 or T2 becomes equal, and the phase difference in this portion disappears.

The common gate power supply bus 29 and the common gate
In the region between the power supply buses 43, the FET unit 19,
FET units 20 and 21 having a unit gate width shorter than the unit gate width of 22 are arranged. For this reason, the common bus 50 is formed to be the shortest, so that the resistance value is reduced and power loss such as heat generation is reduced.

In the semiconductor device 18 described above, the gate pad 51 is connected to an intermediate point between the end T1 and the end T2. However, since the common bus 50 is formed as short as possible, even when the distance from the gate pad 51 to the end T1 or T2 is different, the influence of the phase difference is so small as to be negligible. Therefore, the gate is located at an intermediate point between the end T1 and the end T2.
End T1 and end T
It may be connected to any place between the two.

Also, as a result of the above-described electrode structure,
The gate width Lg of each of the unit gate electrodes 23, 26, 37, 40 in the FET units 19, 20, 21, 22 is short, but the entire gate width Lg is small.
, The total gate width becomes longer, so that a large output can be obtained.

Further, the FET constituting the semiconductor device 18
The units 19, 20, 21, and 22 can be individually supplied with the drain voltage Vd. As a result, FE
The T units 19, 20, 21, 22 can be selectively operated.

Here, the FET units 19, 20, 2
For example, the gate widths of 1, 22, and 23 are set to a ratio of Lg2: Lg3: Lg4: Lg1 = 2: 3: 4: 8.

Then, assuming that the value of the maximum output power of the FET unit 20 is W, the value of the maximum output power of the third FET unit 21 is 1.5 × W,
Is 2 × W, the first FET unit 1
The maximum output value of 9 is 4 × W. Therefore, as shown in FIG. 2, the maximum output of the semiconductor device is W, 1.
5 × W, 2 × W, 2.5 × W, 3 × W,..., 7.5 ×
One of 16 combinations such as W, 8 × W, and 8.5 × W is set. That is, the drain voltage Vd
The maximum output of the semiconductor device can be changed in a wide range without changing the maximum output value.
It can be finely changed at intervals of × W.

In the semiconductor device 18 described above, the FE
Although the T unit 20 is adjacent to the FET unit 19,
The arrangement of the FET unit 20 and the FET unit 21 may be switched so that the FET unit 21 is adjacent to the FET unit 19.

(Embodiment 2) A semiconductor device 52 having another electrode structure will be described with reference to FIG. The only difference from the above-described semiconductor device 18 is the method of connecting the gate pads. Only this point will be described, and the same components are denoted by the same reference numerals.

In the semiconductor device 18 described above, the first common gate power supply bus 29 and the second common gate power supply bus 43
Are connected to a common bus 50, and the common bus 50 is connected to a gate pad 51. However, when designing the layout of the electrode structure of the FET 52, the gate pad 53 may be directly connected to the common gate power supply buses 29 and 43 if space is available.

In this case, unlike the semiconductor device 18 described above, the common bus 51 having a small sectional area, that is, a large resistance component is not provided. Therefore, the phase difference and the resistance component can be ignored as compared with the common bus 51.

[0057]

The semiconductor device of the present invention has the following effects. That is, in the semiconductor device of the first aspect, each F
The ET units can be operated individually with a separate supply of the drain voltage. Therefore, the FE to be operated
By selecting the T unit, the maximum output of the semiconductor device can be changed in a wide range. Therefore, even if the semiconductor device has conventionally had to be changed according to the specifications, the use of the semiconductor device of the present invention can be dealt with by one semiconductor device. Therefore, it is not necessary to replace the semiconductor device or to previously hold various semiconductor devices having different maximum outputs. As a result, the semiconductor device becomes extremely versatile.

In particular, in the development stage of a circuit design using a semiconductor device, the circuit design can be performed very efficiently, and the development cost can be reduced.

Further, in the mass production stage, by adjusting the maximum output of the semiconductor device, it is possible to reduce the output variation of the circuit using the semiconductor device. Therefore, the production yield of a circuit using a semiconductor device can be improved.

Furthermore, the distance between the ends of the first common gate power supply bus and the second common gate power supply bus is the shortest. For this reason, the phase difference between them becomes small, and the gain of the semiconductor device can be kept large, and the resistance value becomes small during this period, so that power loss is reduced.

In addition, an FET unit having a short gate width is arranged inside a semiconductor device from which heat cannot easily escape. Therefore, heat generated inside the semiconductor device is reduced.
Therefore, variation in amplification characteristics between the gate electrodes is reduced.

In the semiconductor device according to the second aspect, the ends of the first and second common gate power supply buses are connected via the common bus. For this reason, the layout of the electrode structure is complicated and
Even if there is no room in terms of space, the degree of freedom in the arrangement position of the gate pad can be increased.

In the semiconductor device according to the third aspect, the distance from the gate pad to the end of the first common gate power supply bus or the second common gate power supply bus is equal. The phase difference disappears. Therefore, the gain of the semiconductor device can be kept larger.

In the semiconductor device according to the fourth aspect, the ends of the first and second common gate power supply buses are directly connected to the gate pads without passing through the common buses. Therefore, the phase difference and the resistance value between the gate pad and the end of the first common gate power supply bus and the end of the second common gate power supply bus can be neglected. The gain can be kept larger, and the power loss can be further reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an electrode structure of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a change in maximum output when a constituent FET unit is selectively operated in a semiconductor device according to the present invention.

FIG. 3 is a diagram showing an electrode structure of another semiconductor device according to the present invention.

FIG. 4 is a diagram showing an electrode structure of a conventional semiconductor device.

FIG. 5 is a diagram showing a change in a maximum output when a drain voltage is changed in a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 18 semiconductor device 19 first field-effect transistor unit (first FET unit) 20 second field-effect transistor unit (second FET unit) 21 third field-effect transistor unit (third FET unit) 22) Fourth field effect transistor unit (fourth FET unit) 23 First unit gate electrode 24 First unit source electrode 25 First unit drain electrode 29 First common gate Electrode bus 30 Source bus 31 Source pad 32 Drain feeder bus 33 Drain pad 43 Second common gate electrode bus 50 Common bus 51 Gate pad

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H03F 3/16

Claims (4)

[Claims] 1. Four field effect transistor units each comprising a unit gate electrode, and unit drain electrodes and unit source electrodes alternately formed so as to sandwich the unit gate electrode. A first common gate power supply bus having unit gate electrodes of adjacent field effect transistor units on both sides, and a unit gate electrode of adjacent field effect transistor units on both sides. A second common gate power supply bus having the second common gate,
A gate pad to which the first common gate power supply bus and the first common gate power supply bus are connected; and power supply means for supplying a drain voltage to each of the field effect transistor units. The total gate width of the effect transistor unit is formed to have a different length, and a unit gate electrode having a shorter gate width than the outside is disposed inside the common gate power supply bus. A semiconductor device characterized by the above-mentioned. 2. An end of each of a first common gate power supply bus and a second common gate power supply bus is connected to a gate pad through a common bus. 3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the gate pad is provided at the center of the common bus. 4. The semiconductor according to claim 1, wherein ends of the first common gate power supply bus and the second common gate power supply bus are directly connected to a gate pad. apparatus.