JP2000098976A - Signal line driving circuit and liquid crystal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by providing a switch between adjacent signal lines and turning on/off these switches with the prescribed timing in plural signal lines successively driven. SOLUTION: A vertical scanning circuit 40 is constituted of a vertical shift register 42, a vertical selecting line driver 44 consisting of pMOS, nMOS transistors, and switching elements M2, M3,... Mk connecting between adjacent signal lines in vertical scanning lines VSL1, VSL2,... VSLk. The vertical selecting line VSL1 fs charged to driving voltage VSL2 at the first period of a horizontal synchronizing signal. The vertical selecting lines VSL1 and VSL2 both are set to a floating state at directly before finish of the first period, rearrangement of electric charges is performed by turning on the switching element M2 between vertical selecting lines, and the vertical selecting line VSL2 is charged to Vp/2. In the second period, the vertical selecting line VSL2 is charged to driving voltage Vp from Vp/2. After that, rearrangement of electric charges is performed in the same way in each vertical selecting line VSL1,... VSLk.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal line driving circuit,
In particular, the present invention relates to a liquid crystal drive circuit that is used for a liquid crystal display device and drives a vertical selection line, for example.

[0002]

2. Description of the Related Art A liquid crystal panel of a liquid crystal display device, for example, T
In an FT (Thin film transistor) liquid crystal panel, a plurality of vertical selection lines are sequentially driven by a vertical scanning circuit so that a liquid crystal display element (hereinafter, referred to as a liquid crystal cell) connected to these vertical selection lines functions. . By driving one vertical selection line, one row of pixels can be displayed by a plurality of liquid crystal cells connected to the vertical selection line. By sequentially driving the vertical selection lines, an image of one frame on the display panel is displayed.

FIG. 6 shows a configuration example of a vertical scanning circuit. Further, the operation timing of the vertical scanning circuit is shown in FIG.
The timing chart of FIG. As shown in FIG. 6, the vertical scanning circuit includes a vertical shift register 50 and a vertical selection line driver including a plurality of inverter circuits.

[0004] The vertical select line driver, as shown in FIG.
It comprises a plurality of cMOS inverters composed of MOS transistors and nMOS transistors. Control signals S _C1, S _C2, S _C3 from the vertical shift register 50 to the input terminal of each inverter, ..., S _CK are input, respectively the vertical selection line to an output terminal of each inverter VSL1, VS
, VSLk are connected. By each inverter, it sets the vertical selection line according to an input control signal to one of the drive voltage V _P or ground potential GND.

[0005] For example, in an inverter configured by the transistors P1 and N1, the source of the transistor P1 is connected to the driving voltage V _P, the source of the transistor N1 is grounded. The gates of the transistors P1 and N1 are connected to form the input terminal of the inverter, and the drains of the transistors P1 and N1 are connected to form the output terminal of the inverter. When a high-level control signal S _C1 is applied to the input terminal of the inverter, the transistor N1 is turned on, the transistor P1 is turned off, and the vertical selection line VSL1 is held at the ground potential GND. Conversely, when the input terminal of the inverter low level of the control signal S _C1 is applied, the transistor P1 is turned on, the transistor N1 is turned off, the vertical selection line VSL1 is charged to the driving voltage V _P.

The operation timing of the vertical scanning circuit shown in FIG.
This is shown by the timing chart of FIG. In FIG. 7, HD is, for example, a horizontal synchronous scanning signal.
, Φk are vertical selection lines VS, respectively.
L1, VSL2, VSL3,..., VSLk are shown. As shown, the vertical selection lines VSL1, VSL2, VSL3,..., VSLk are sequentially driven for each horizontal period (1H). That is, each vertical selection line is held to the driving voltage V _P respectively within one horizontal period.

[0007] The vertical scanning circuit shown in FIG. 6, each vertical selection line at the timing shown in FIG. 7 is held sequentially to the driving voltage V _P, the liquid crystal panel for each horizontal period is connected to each vertical selection line Each row of the image of one frame is sequentially displayed by the liquid crystal cell, and the image of each frame is displayed every one vertical cycle.

[0008]

Meanwhile [0006] In the conventional liquid crystal driving circuit described above, the vertical selection line for each horizontal period is driven from the ground potential GND to the drive voltage V _P. That is, since the charge of each vertical selection line to the drive voltage V _P from the ground potential GND, and power consumption due to this there is the disadvantage that large.

For example, if the number of vertical selection lines of a liquid crystal display panel is k, the capacitance per vertical scanning line is C _S , the driving voltage is V _P , and the frame frequency is f _V , the vertical selection line driving of the liquid crystal panel is performed. power P _C for is obtained by the following equation.

[0010]

[Number 1] _{P C = k · C S ·} V P 2 · f V ... (1)

[0011] larger panel of a liquid crystal display device, with high resolution, increases the capacity per one by increasing the length of the vertical selection line, since more is the number of vertical selection lines increases, increasing the power consumption P _C is I do. Furthermore, the power consumption P _C by increasing the frame frequency in the liquid crystal display device measures to increase the frame frequency in order to reduce flicker (flickering of the display screen) are taken to increase.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the power consumption by reusing the charges of adjacent vertical selection lines in a liquid crystal display device. It is an object of the present invention to provide a liquid crystal drive circuit capable of suppressing an increase in power consumption due to higher resolution, higher resolution, and higher frame frequency.

[0013]

In order to achieve the above object, a signal line driving circuit according to the present invention sequentially sets n (n is an integer of 2 or more) signal lines to a predetermined voltage, A signal line driver circuit for functioning a circuit element connected to a signal line, comprising: a plurality of switching elements connected between adjacent signal lines; and each of the first to n-th signal lines. After the voltage setting circuit for sequentially setting the predetermined voltage and the i-th (i = 1, 2,..., N-1) signal lines are held at the predetermined voltage, the next (i + 1) -th signal line
And a switch control circuit for turning on the switching element between the i-th signal line and the (i + 1) -th signal line for a predetermined period before the signal lines are driven.

In the liquid crystal drive circuit of the present invention, a plurality of liquid crystal cells are arranged in a matrix, a drive selection line is wired for each row of the liquid crystal cells, and a pixel signal line is wired for each column of the liquid crystal cells. Each liquid crystal cell is connected to the pixel signal line via a transistor whose gate is connected to the drive selection line, and is connected to the drive selection line when the drive selection line is driven to a predetermined voltage. One row of liquid crystal cells is a liquid crystal drive circuit that displays each pixel in accordance with the pixel signal on each pixel signal line, and in n (n is an integer of 2 or more) drive selection lines, Receiving a synchronization signal and a plurality of switching elements connected between
The drive selection line driver for sequentially setting each of the drive selection lines to the predetermined voltage for each cycle of the synchronization signal, and the i-th (i = 1, 2,..., N-1) drive selection lines are After being held at a predetermined voltage, the switching element between the (i + 1) th drive selection line and the (i + 1) th drive selection line before driving the next (i + 1) th drive selection line For a predetermined period.

Furthermore, in the present invention, preferably, the i-th
When the switching element between the drive signal lines and the (i + 1) th drive signal line is turned on, the i-th and (i + 1) th drive selection lines are set in a floating state. Thus, when the switching element is turned on, the electric charges of the i-th and (i + 1) th drive selection lines are redistributed, and these drive selection lines are reduced to a voltage approximately half of the predetermined drive voltage. Will be retained.

According to the present invention, in a plurality of signal lines driven at a predetermined drive voltage, switching elements are provided between adjacent signal lines, and the driving of the previous signal line is completed and the next signal line is completed. By turning on the switching elements between the signal lines before the signal lines start to be driven, the charges of the adjacent signal lines are redistributed, so that the level of the previous signal line is reduced to almost half of the drive voltage. Then, since the level of the next signal line rises to almost half of the drive voltage, when the next signal line is driven, it is driven from almost half the level of the drive voltage to the above drive voltage. Power consumption by driving is reduced. In this manner, the power consumption of the signal line whose driving period ends is reused in the adjacent signal line and the potential of the signal line to be driven next is raised, thereby reducing power consumption.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing an example of a configuration of a liquid crystal display device including a liquid crystal drive circuit according to the present invention. As shown in the figure, the liquid crystal display device of this embodiment includes a serial / parallel conversion circuit 10, a sample / hold circuit 20, and a liquid crystal panel 30. The liquid crystal panel 30 is, for example, a TFT liquid crystal panel, and has k vertical selection lines VSL1, VSL2,..., VSLk driven by the vertical scanning circuit 40, a plurality of TFTs driven by these vertical selection lines, and It is composed of a plurality of liquid crystal cells connected to these TFTs.

The serial / parallel conversion circuit 10 converts a serially input video signal _SV into a parallel video signal. For example, the serial / parallel conversion circuit 10
Converts the image signal S _V for one horizontal period is input to the serial (1H) into a parallel signal, and outputs the m-number of pixel signals corresponding to one line of an image in the liquid crystal panel in parallel.

The sample and hold circuit 20 includes a synchronization signal,
For example, it operates according to the horizontal synchronizing signal HD and the vertical synchronizing signal VD, samples m pixel signals output from the serial / parallel conversion circuit 10, and holds them.
I do. Then, the held m pixel signals S1, S2,
, Sm are connected to signal lines SL1, SL2, SL3,.
Output to SLm.

The liquid crystal panel 30 includes a plurality of liquid crystal cells L ₁₁ , L ₁₂ , L ₁₃ ,..., L _1m , L ₂₁ , arranged in a matrix.
_{L 22, L 23, ...,} L 2m, L k1, L k2, L k3, ..., it is constituted by L _miles. Each liquid crystal cell is made of a liquid crystal material, and when a predetermined driving voltage is applied to the liquid crystal cell, the optical characteristics of the liquid crystal cell change, so that one pixel can be displayed by one liquid crystal cell.

As shown, one electrode of each liquid crystal cell is connected to a common potential V _SS , and the other electrode is connected to a TFT. In the TFT, one of the impurity diffusion layers forming the source or the drain is connected to the signal line SL1,
, SLm, and connected to the other liquid crystal cell. The gate of the TFT is connected to one of the vertical selection lines VSL1, VSL2,..., VSLk. For example, is connected to the common potential V _SS of one of the liquid crystal cell L _11, the other TFT (T ₁₁₎
Are connected to one of the impurity diffusion layers. The other of the impurity diffusion layers of the T ₁₁ is connected to the signal lines SL1, SL2, SL3, the gate is connected to the vertical selection line SVL1.

As described above, in the liquid crystal panel 30, at the intersections of the m signal lines SL1, SL2, SL3,..., SLm and the k vertical selection lines VSL1, VSL2,. A liquid crystal cell is arranged. Each TFT in the same row is turned on / off in response to a vertical selection signal applied to a vertical selection line in the row,
Is turned on, the pixel signal applied to the signal line connected thereto is applied to the liquid crystal cell. For this reason,
Since each vertical selection line is sequentially driven by the vertical scanning circuit 40, the TFTs in each row are sequentially turned on, and accordingly, the pixel signals output by the sample and hold circuit 20 are sequentially displayed by the liquid crystal cells in each row. One frame image is displayed by the liquid crystal panel 30.

The k vertical selection lines wired to the liquid crystal panel 30 are driven by the vertical scanning circuit 40. FIG.
Is a liquid crystal driving circuit according to the present invention, that is, a vertical scanning circuit 40.
1 shows a configuration example. As shown, the vertical scanning circuit 40 includes a vertical shift register 42, a vertical selection line driver 44 including a plurality of pMOS transistors and nMOS transistors, and k vertical scanning lines VSL1 and VSL.
, VSLk, the switching elements M2, M3,..., Mk connected between adjacent signal lines. These switching elements are:
As shown in FIG.
The impurity diffusion layers forming the source and drain of these pMOS transistors are connected to adjacent vertical selection lines, respectively, and have control signals φ1c, φ2c, φ3c,..., Φ (k−1) from the vertical shift register 42 at the gates. )
c is applied.

The vertical shift register 42 comprises, for example, a plurality of shift registers. The vertical shift register 42 sends control signals φ1n, φ2n, φ3n,..., Φkn, φ1p, to the vertical selection line driver 44 according to the input horizontal synchronization signal HD and vertical synchronization signal VD.
.., φkp, and control signals φ1c, φ2c, φ3 for controlling on / off of the switching elements M2, M3,.
.., φ (k−1) c are output.

The vertical selection driver 44 receives k vertical selection lines V in response to a control signal from the vertical shift register 42.
, VSLk are driven. For example,
The pMOS transistor P1 and the nMOS transistor N1 are controlled by a control signal φ1p from the vertical shift register 42.
And in response to Fai1n, it sets the vertical selection line VSL1 to any one of the driving voltage V _P or ground potential GND. Specifically, the source of the pMOS transistor P1 is connected to the voltage V _P, the source of the nMOS transistor N1 is connected to the ground potential GND. The drains of the transistors P1 and N1 are connected to each other, and a vertical selection line VSL is connected to the connection point.
1 is connected. Control signals φ1p and φ1n are input to the gates of the transistors P1 and N1, respectively, and are turned on or off according to these control signals.

For example, when the control signal φ1p is at a high level,
When 1n is at low level, both transistors P1 and N1 are turned off. At this time, the vertical selection line VSL1 is in a floating state. On the other hand, when the control signals φ1p and φ1n are both at the high level, the transistor P1 is turned off,
1 turns on, and the vertical selection line VSL1 is held at the ground potential GND. Or, the control signal φ1p and when φ1n is low both transistor P1 is turned on, N1 is turned off, the vertical selection line VSL1 is held to the driving voltage V _P.
The control signal φ1p is low, when φ1n is high, the transistors P1 and N1 are both turned on, the driving voltage V _P is shorted, this condition is prohibited. The other vertical selection lines VSL2, VSL3,..., VSLk are driven by paired pMOS transistors and nMOS transistors, respectively, in substantially the same manner as the vertical selection line VSL1.

FIG. 3 is a timing chart showing the operation timing of the liquid crystal drive circuit shown in FIG. Hereinafter, FIG.
The operation of the liquid crystal drive circuit of the present invention will be described with reference to FIG.

As shown in FIG. 3, the horizontal synchronizing signal HD is a pulse signal having a fixed cycle. Although the vertical synchronization signal VD is omitted in FIG. 3, the vertical synchronization signal VD
Is a pulse having a fixed period. The frequency of the vertical synchronizing signal VD is, for example, equal to the frame frequency, or, for interlace scanning, for example, twice the frame frequency.

In the initial state, control signals φ1p, φ2
, φkp and control signals φ1n, φ2
, φkn are held at a high level, the vertical selection line driver 44
The OS transistors P1, P2, P3,..., Pk are turned off, and the respective nMOS transistors N1, N2, N3,.
k turns on. Therefore, the vertical selection lines VSL1, VSL
2,..., VSLk are all held at the ground potential GND. At this time, the control signals φ1c, φ2c, φ3
Since all of c,..., φ (k−1) c are held at the high level, all the switching elements M2, M3,.

Just before the first horizontal synchronizing signal HD is input, the control signal φ1n goes low, and thereafter the control signal φ1p also goes low. In the vertical selection line driver 44 in response to this, the transistor P1 is turned on, the transistor N1 is turned off, the vertical selection line VSL1 is charged to the driving voltage V _P. Vertical selection line VSL1
Are held at the drive voltage _VP level in the first horizontal cycle.

Immediately before the end of the first horizontal cycle, the control signal φ1p is switched from the low level to the high level, and the control signal φ1n is maintained at the low level. Therefore, both the transistors P1 and N1 are turned off. Also,
Since the control signal φ2n is also held at the low level, n
Since the MOS transistor N2 is also turned off, the vertical selection line V
SL1 and VSL2 are both in a floating state. Further, since the control signal φ1c is held at the low level during this time, the switching element M2 is turned on. As a result, the vertical selection line VSL2 is changed by the vertical selection line VSL2.
Is charged. That is, the vertical selection lines VSL1 and VSL
The charge is redistributed between the two. Before the charge redistribution, the vertical selection line VSL1 is in drive voltage V _P, the vertical selection line V
Since SL2 is at ground potential GND, the voltage on these vertical select lines will be approximately V _P / 2 as a result of charge redistribution.

Next, in the second cycle of the horizontal synchronizing signal HD (2H
The control signals φ1n and φ1c are switched from low level to high level. For this reason, nMO
The S transistor N1 turns on, the vertical selection line VSL1 is discharged, and is held at the ground potential GND. Further, the switching element M2 is turned off. On the other hand, since the control signal φ2p is switched from the high level to the low level, the pMOS transistor P2 is turned on and the vertical selection line V
SL2 is charged from V _P / 2 in the driving voltage V _P, is held to the driving voltage V _P during the second period of the horizontal synchronizing signal HD.

Thus, immediately before the end of the first cycle,
The electric charge is redistributed on the vertical selection lines VSL1 and VSL2, so that the vertical selection line VSL2 once becomes V _P /
Can be lifted to 2. And in the second cycle,
Vertical selection line VSL2 is charged from V _P / 2 to V _P. Before driving the vertical selection line VSL2, the electric charge of the previously driven vertical selection line VSL1 is reused, and the electric charge is redistributed between the vertical selection lines VSL1 and VSL2. lifted to approximately half the voltage level of V _P. Vertical selection line VS
When driving L2, only enough power is consumed to charge from V _P / 2 to the drive voltage V _P , so that the vertical select line VSL2 is charged from the ground potential GND to the drive voltage V _P as in the conventional liquid crystal drive circuit. Power consumption can be reduced to almost half compared with the case where

Each vertical selection line V after the vertical selection line VSL2
SL3,..., VSLk are connected to the above-described vertical selection line VLS2.
When much like, since it is charged to the driving voltage V _P is once charged to V _P / 2 level by the vertical selection line adjacent respectively, the power consumption when driving the respective vertical selection lines is reduced. As described above, except for the first vertical selection line VSL1, the other vertical selection lines VSL2, VSL
In SL3,..., VSLk, it is possible to realize reduction in power consumption when charging by redistribution of charges between adjacent vertical selection lines.

As described above, according to this embodiment, the switching elements M2 and VSLk are arranged between the vertical selection lines VSL1, VSL2,.
M3, ..., connected to Mk, was charged first vertical selection line VSL1 in one cycle of the horizontal synchronizing signal HD to the drive voltage V _P, the vertical selection line immediately before the first cycle is completed VLS1
And VLS2 are both set to a floating state, and the switching element M2 between these vertical selection lines is turned on to redistribute the charge, and the vertical selection line VSL2 is set to V _P.
/ 2. When the second cycle is started, to charge the vertical selection line VLS2 from V _P / 2 to the drive voltage V _P. Because once charged by raising the V _P / 2 to V _P by redistribution of similar charges in each vertical selection line since, can realize a reduction in power consumption for driving the vertical selection line.

Second Embodiment FIG. 4 is a circuit diagram showing a liquid crystal drive circuit according to a second embodiment of the present invention. The liquid crystal drive circuit according to the present embodiment includes a plurality of switches S1b, S2b, S3b,.
2a, S3a..., And k vertical selection lines VSL1, VSL
Drive SL2,..., VSLk.

As shown, the vertical shift register 42a
Receives the horizontal synchronizing signal HD and the vertical synchronizing signal VD, and controls a plurality of, for example, k buffers BUF1, BUF2, BUF3. Drive signals φ1a, φ2a, φ3a,... Are output from each buffer. Note that these drive signals, for example, a signal held in the driving voltage V _P of sequential vertical selection line for each cycle of the horizontal synchronizing signal HD.

The output terminal of the buffer BUF1 is a switch S
1b, and is connected to the vertical selection signal VSL1. Similarly, the output terminals of the other buffers are connected to other vertical selection lines via switches. The switches S2a, S3a, S4a,... Are connected between adjacent vertical selection lines. For example, vertical selection lines VSL1 and VSL
The switch S2a is connected to the switch SL2, and the switch S3a is connected between the vertical select lines VSL2 and VSL3.

The switches S1b, S2b, S3b... And S1a, S2a, S3a.
As in the embodiment, ON / OFF is controlled by a control signal signal from the vertical shift register 42a. In FIG. 4, control signals for controlling the switches are omitted.

FIG. 5 is a timing chart during the operation of the liquid crystal drive circuit shown in FIG. Hereinafter, the operation of the present embodiment will be described with reference to FIGS. 4 and 5. FIG.
, The signals S1 to Sm are pixel signals output to the signal lines SL1, SL2, SL3,..., SLm by the sample and hold circuit 20 in the liquid crystal display device shown in FIG.

As shown in the figure, each buffer BUF1, BUF2, BUF3... Is driven by a control signal from the vertical shift register 42a for each cycle of the horizontal synchronizing signal HD.
The output signal of each buffer is sequentially held at the drive voltage _VP level for each cycle of the horizontal synchronization signal HD.

For example, in the first cycle of the horizontal synchronizing signal HD, the output signal φ1a of the buffer BUF1 becomes the driving voltage V
Set to _P. At this time, since the switch S1b is turned on, the vertical selection line VSL1 is held to the driving voltage V _P. Since the switch S1b is turned off immediately before the end of the first cycle of the horizontal synchronizing signal HD, the vertical selection lines VSL1 and VSL
Both SL2 are held in a floating state.
Further, since the switch S2a is turned on, the vertical selection line V
Charge redistribution is performed between SL1 and VSL2. As a result of the charge redistribution, the vertical selection lines VSL1 and VSL2 are maintained at approximately V _P / 2.

In the second cycle of the horizontal synchronizing signal HD, the buffer BUF2 is driven, and its output terminal is driven by the driving voltage V.
_It is held in _P. At this time, since the switch S2b is turned on, the vertical selection line VSL2 is charged to the driving voltage V _P. That is, after the vertical selection line VSL2 is once charged to V _P / 2 by charge redistribution with the adjacent vertical selection line VLS1, the driving voltage V _{P is} applied by the buffer BUF2.
Is charged. For this reason, V _P from ground potential GND
The power consumption can be reduced to almost half of the case of charging up.

Each of the other vertical selection lines VSL3,... After the vertical selection line VSL2 is temporarily set to V by redistribution of charges between adjacent vertical selection lines, similarly to the vertical selection line VSL2.
After charged up to _P / 2 level, since it is charged to the driving voltage V _P, the power consumption for driving the vertical selection line can be reduced.

As described above, according to the present embodiment, the buffers BUF1, BUF are received by the vertical shift register 42a upon receiving the horizontal synchronizing signal HD and the vertical synchronizing signal VD.
UF2, BUF3 ... sequentially driven for each horizontal period, the switch S1b is turned on in the first period of the horizontal synchronizing signal HD, for holding the vertical selection line VSL1 the driving voltage V _P. 1
By turning off the switch S1b and turning on the switch S2a just before the end of the cycle, the vertical selection lines VSL1 and VS
L2 is redistributed, and the vertical selection line VSL2 is set to V _P /
Hold at 2. In the second cycle of the horizontal synchronization signal HD,
Turns on the switch S2b, to charge the vertical selection line VSL2 from V _P / 2 to V _P by the buffer BUF2. Therefore, power consumption for driving the vertical selection line can be reduced.

In the first and second embodiments described above, a configuration example of the present invention is shown by taking a liquid crystal driving circuit as an example. However, the present invention is not limited to a liquid crystal driving circuit.
The present invention can be applied to other signal line driving circuits that perform the same operation. For example, in an image scanner, since the image sensors arranged in a matrix are sequentially driven for each row or column, electric charges are transferred between adjacent signal lines in the driving signal lines of the image sensor as in the present invention. By reusing, the power consumption of the drive circuit can be reduced.

[0047]

As described above, according to the signal line driving circuit and the liquid crystal driving circuit using the same according to the present invention, a switch is provided between adjacent signal lines in a plurality of sequentially driven signal lines. By turning on / off these switches at a predetermined timing, there is an advantage that charges can be reused between adjacent signal lines and power consumption in driving the signal lines can be reduced. The use of a circuit is advantageous for increasing the size and resolution of a liquid crystal display device and improving the frame frequency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a liquid crystal display device according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of a liquid crystal drive circuit according to the present invention.

3 is an operation timing chart of the liquid crystal drive circuit shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the liquid crystal drive circuit according to the present invention.

5 is an operation timing chart of the liquid crystal drive circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of a general liquid crystal drive circuit.

7 is an operation timing chart of the liquid crystal drive circuit shown in FIG.

[Explanation of symbols]

10 serial / parallel conversion circuit, 20 sample-hold circuit, 30 liquid crystal panel, 40 vertical scanning circuit
42, 42a ... vertical shift register, 44 ... vertical selection line _{driver, T 11, T 12, ...} , T 1m, T 21, T 22, ...,
T _2m , T _k1 , T _k2 , ..., T _km ... TFT, L ₁₁ , L ₁₂ ,
_{..., L 1m, L 21,} L 22, ..., L 2m, L k1, L k2, ..., L
_miles ... liquid crystal cell, BUF1, BUF2, BUF3 ... buffer, V _P ... driving voltage, GND ... ground potential.

Continued on the front page F term (reference) 2H093 NA16 NA43 NA53 NB22 NC12 NC22 NC34 ND60 5C006 AA01 AC28 AC29 AF25 AF42 AF44 AF51 AF71 BB16 BC03 BC13 BC20 BF03 BF11 BF32 BF34 BF38 FA47 5C080 AA10 BB05 DD26 FF11 GG08 JJ02 FF11 JJ

Claims (4)

[Claims] 1. A signal line driving circuit for sequentially setting n (n is an integer of 2 or more) signal lines to a predetermined voltage and causing a circuit element connected to each signal line to function, A plurality of switching elements connected between adjacent signal lines; a voltage setting circuit for sequentially setting the first to n-th signal lines to the predetermined voltage; , 2,..., N-1) signal lines are held at the predetermined voltage, and before the next (i + 1) th signal line is driven, the i-th signal line and the A switch control circuit for turning on the switching element between the (i + 1) th signal lines for a predetermined period. 2. A plurality of liquid crystal cells are arranged in a matrix, a drive selection line is wired for each row of the liquid crystal cells, a pixel signal line is wired for each column of the liquid crystal cells, and a gate of each liquid crystal cell is driven by the drive. When the drive selection line is connected to the pixel signal line via a transistor connected to the selection line and the drive selection line is driven to a predetermined voltage, one row of liquid crystal cells connected to the drive selection line is A liquid crystal drive circuit for displaying each pixel according to a pixel signal on each pixel signal line, wherein the liquid crystal drive circuit is connected between adjacent drive selection lines in n (n is an integer of 2 or more) drive selection lines. A plurality of switching elements, a drive selection line driver that receives a synchronization signal, and sequentially sets each of the drive selection lines to the predetermined voltage for each cycle of the synchronization signal; and the i-th (i = 1, 2,...) , N-1) drive selection lines After the voltage is held at the predetermined voltage, the switching between the (i + 1) th drive selection line and the (i + 1) th drive selection line is performed before driving the next (i + 1) th drive selection line. A liquid crystal drive circuit having a switch control circuit for turning on the element for a predetermined period. 3. When the switching element between the i-th drive signal line and the (i + 1) -th drive signal line is turned on, the i-th and (i + 1) -th drive signal lines are in a floating state. 3. The liquid crystal driving circuit according to claim 2, wherein the setting is set. 4. The switching element includes a transistor to which a control signal from the switch control circuit is applied to a gate, and an impurity diffusion layer forming a source and a drain connected to the adjacent drive selection line. The liquid crystal drive circuit according to claim 2, wherein