JP2000092863A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress ground noise current while making a switching element to conduct high-speed switching the most suitable to the switching element. SOLUTION: In this inverter device, the output points of inverter legs 11, 12 constituted of two serial semiconductor switching elements for shortening DC voltage are connected through a coupling reactor 13. By shifting switching timing of the respective inverter legs 11, 12 a little, the voltage with low voltage changing factor is outputted by voltage drop at the coupling reactor 13 as output voltage despite of the respective semiconductor switching elements conducting high-speed switching. Thus, it is possible to restrain ground noise current while conducting high-speed switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an inverter device.

[0002]

2. Description of the Related Art Conventionally, an inverter device for generating a desired AC voltage from a DC voltage and outputting the AC voltage, as shown in FIG. 16, has inverter legs 101, 102, 1 constituting each phase.
03 upper side switching element (DC voltage positive side connection element)
And the lower switching element (DC voltage negative side connection element) are each configured by one semiconductor element, or are configured by a plurality of parallel / series connected semiconductor elements. The configuration is such that it operates by the same gate command signal and can be regarded as one switching element.

[0003]

However, IGB
As a semiconductor having a high switching speed such as T (Insulated Gate Bipolar Transistor) is applied to an inverter device, a high voltage change rate (d
v / dt), a ground noise current flows through a ground stray capacitance (capacitor component) of an electric motor or the like connected as a load of the inverter, which causes a malfunction of the earth leakage breaker and a source of noise to a communication signal system. There is. For this reason, measures have been considered to reduce the noise current by intentionally delaying the switching operation by devising the gate drive circuit that operates the switching element.However, delaying the switching operation increases the heat loss due to switching. Invite
There are other problems such as a decrease in the efficiency of the inverter and an increase in the volume of the cooler.

It is an object of the present invention to reduce the noise current to the ground while performing high-speed switching most suitable for the switching element.

[0005]

To achieve the above object, according to the present invention, two switching elements for short-circuiting a DC voltage are connected in series, and the two switching elements are connected in series. A pair of inverter legs that output an AC voltage from a connection point of the pair, a coupling reactor connected between the output of each AC voltage of the pair of inverter legs and the load, and one of the pair of inverter legs The gist of the present invention is to provide, for each phase, short-circuit timing adjusting means for shifting the short-circuit timing of the switching element forming the other inverter leg corresponding to the switching element with respect to the short-circuit timing of the switching element forming the inverter leg. .

The present invention according to claim 2 is based on claim 1.
In the described invention, the short-circuit timing adjusting means
The gist is a delay means for delaying the short-circuit timing of the switching element constituting the other inverter leg with respect to the short-circuit timing of the switching element constituting one inverter leg.

According to the first and second aspects of the present invention, the output points of the inverter legs composed of two series semiconductor switching elements for short-circuiting a DC voltage are connected by a coupling reactor, and then the switching of each inverter leg is performed. By slightly shifting the timing, despite the fact that each semiconductor switching element is performing high-speed switching, the output voltage is output at a low voltage change rate due to the voltage drop in the coupling reactor. The noise current is reduced.

According to a third aspect of the present invention, there is provided an inverter device for generating and outputting a desired AC voltage from a DC voltage, the first being composed of two series-connected semiconductor switching elements for short-circuiting the DC voltage. An inverter leg and a second inverter leg, a coupling reactor that connects intermediate points of the semiconductor switching elements connected in series of the first and second inverter legs, and supplies power to the load from the intermediate point; A gate signal generating means for outputting an on / off command signal to each of the two semiconductor switching elements constituting one inverter leg, and an on / off command signal output from the gate signal generating means being delayed by a predetermined time. Semiconductor of the second inverter leg corresponding to the semiconductor switching element of the first inverter leg And summarized in that and a delay means for outputting respective switching elements for each phase.

According to the third aspect of the invention, the output point of the inverter leg composed of two series semiconductor switching elements for short-circuiting a DC voltage is connected by a coupling reactor, and then the output from the gate signal generating means is turned on. -By shifting the switching timing of each inverter leg based on the OFF command signal by a delay, the output voltage has a low voltage change rate due to the voltage drop in the coupling reactor even though each semiconductor switching element performs high-speed switching. Voltage is output, and high-speed switching is performed to reduce ground noise current.

According to a fourth aspect of the present invention, there are provided a DC positive potential side switching element and a DC negative potential side switching element for short-circuiting a DC voltage connected in series between DC power supplies. A plurality of inverter legs connected in parallel to the DC power supply that outputs an AC voltage from a connection point of the series connection of the switching elements, and a coupling reactor connected between each AC voltage output of the inverter leg and the load; A gate signal generating means for outputting an on / off command signal to each of two switching elements constituting one of the inverter legs; and an on / off command signal output from the gate signal generating means, respectively. It is essential that each phase have delay means for supplying the corresponding switching elements of the inverter leg while sequentially delaying them. .

According to the present invention, the inverter leg composed of two series semiconductor switching elements for short-circuiting the DC voltage is composed of two or more for each phase of the UVW, and the output point of each inverter leg is provided. The connection voltage is changed by the voltage drop in the coupling reactor even though each semiconductor element is performing high-speed switching by slightly shifting the switching timing of each inverter leg after connecting with the coupling reactor. A low-rate voltage is output to reduce the noise current to the ground while performing high-speed switching.

According to a fifth aspect of the present invention, in the invention of the fourth aspect, the coupling reactors are connected to respective reactors in accordance with an order of supplying on / off command signals to switching elements constituting each inverter leg. The point is that the capacity is set.

According to the fifth aspect of the present invention, the reactors of the coupling reactors connected to each inverter leg are intentionally designed to have non-identical values in accordance with the order of the switching delay of the inverter legs, and the entire reactor is designed. The capacity is being optimized.

According to a sixth aspect of the present invention, in the invention of the fourth aspect, the coupling reactor is a first-stage coupling reactor respectively connected to the output of each AC voltage of the inverter leg, The gist is that the coupling reactor is constituted by a second-stage coupling reactor obtained by combining the coupling reactors in a predetermined combination.

In the invention according to claim 6, the inductance value of the coupling reactor connected to each inverter leg is the same regardless of the switching order.

The present invention according to claim 7 provides the invention according to claims 2 to 6
The gist of the present invention is that the delay means sets a delay time based on a resonance cycle of a current supplied to a load.

The present invention according to claim 8 provides the invention according to claims 2 to 6
The gist of the present invention is that the delay means sets the delay time based on the magnitude of the total harmonic amount of the current supplied to the load.

According to the seventh and eighth aspects of the present invention, the delay time is set so as to reduce the resonance current.
And by adjusting the total harmonics to a minimum,
While performing high-speed switching of a semiconductor switching element, reduction of a noise current of a specific harmonic to the ground is aimed at.

The present invention described in claim 9 is the first to eighth aspects of the present invention.
In the invention according to any one of the first to third aspects, a gist of the invention is to have a capacitor for connecting the phases of the load.

According to the ninth aspect of the present invention, the reactor and the capacitor constituting the coupling reactor are used to perform the LC
Harmonic current is suppressed by suppressing harmonics as a filter.

According to a tenth aspect of the present invention, in the invention according to any one of the first to ninth aspects, the coupling reactor is obtained by applying a winding short-circuited by a resistor to a core constituting the coupling reactor. Is the gist.

According to the tenth aspect of the present invention, the current circulating between the inverter legs via the coupling reactor is attenuated, thereby suppressing damage and heat generation of the semiconductor switching element due to an excessive current. ing.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a first embodiment in which the present invention is applied to a three-phase load inverter device.
The inverter device shown in the figure includes a first inverter leg 11, a second inverter leg 12, a coupling reactor 13, and a gate signal generator 1 for each of three phases of UVW.
4, an upper element delay generator 15 and a lower element delay generator 16
It is composed of

The first inverter leg 11 includes an upper semiconductor switching element 111 and an upper reverse conducting diode 112, similarly to the inverter leg of a conventional voltage source inverter.
And a lower semiconductor switching element 113 and a lower reverse conducting diode 114. Upper semiconductor switching element 111 and lower semiconductor switching element 113
Is a switching element having a high switching speed such as an IGBT.

The upper semiconductor switching element 111 performs a switching operation in accordance with an upper element gate command signal PWMu1 output from the gate signal generator 14.

[0027]

## EQU1 ## When PWMu1 = 1, the upper semiconductor switching element 111 is turned on. When PWMu1 = 0, the upper semiconductor switching element 111 is turned on.
1 off The lower semiconductor switching element 113 is a lower element gate command signal PWMx1 output from the gate signal generator 14.
The switching operation is performed according to.

[0028]

## EQU2 ## When PWMx1 = 1, the lower semiconductor switching element 113 is turned on. When PWMx1 = 0, the lower semiconductor switching element 11 is turned on.
3 off The second inverter leg 12 is connected to the first inverter leg 1
As in the case of 1, the upper semiconductor switching element 121 and the upper reverse conducting diode 122, and the lower semiconductor switching element 123 and the lower reverse conducting diode 124 are formed.

The upper semiconductor switching element 121 performs a switching operation according to the upper element gate command signal PWMu2 output from the upper element delay generator 15.

[0030]

## EQU3 ## When PWMu2 = 1, the upper semiconductor switching element 121 is turned on. When PWMu2 = 0, the upper semiconductor switching element 12 is turned on.
1 off The lower semiconductor switching element 123 is a lower element gate command signal PWMx2 output from the lower element delay generator 16.
The switching operation is performed according to.

[0031]

## EQU4 ## When PWMx2 = 1, the lower semiconductor switching element 123 is turned on. When PWMx2 = 0, the lower semiconductor switching element 12 is turned on.
FIG. 2 shows a configuration example of the coupling reactor 13. Coupling reactor 13 includes a wiring from a portion where the emitter of upper semiconductor switching element 111 of first inverter leg 11 is connected to the collector of lower semiconductor switching element 113, and an upper semiconductor switching element 121 of second inverter leg 12. And the wiring from the portion where the emitter of the lower semiconductor switching element 123 is connected to the load, and the wiring to the load. Each winding is connected to the iron core such that the direction of the magnetic field created by the current flowing from the first inverter leg 11 to the load inside the iron core and the direction of the magnetic field created by the current flowing from the second inverter leg 12 to the load inside the iron core are reversed. Wrap. When the number of windings is the same and the current flowing from the first inverter leg 1 to the load is equal to the current flowing from the second inverter leg 2, the magnetic fields generated by the two cancel each other out and the magnetic field inside the iron core becomes zero.

The current flowing from the first inverter leg 1 to the second inverter leg 2 is applied to the coupling reactor 13.
Acts as an inductance.

In the gate signal generation section 14, the upper element gate command signal PWMu1 and the lower element gate command signal P
WMx1 is output. The operation of the gate signal generator 14 will be described with reference to FIG. The triangular wave TRI is a triangular wave having a constant frequency, for example, 2 kHz and an amplitude of 1. U-phase voltage command Vu
Ref is an inverter output voltage command to be output to the load. The output gate command VuPWM takes a logical value of 1 or 0 according to the result of the magnitude comparison between the U-phase voltage command VuRef and the triangular wave TRI.

When VuRef> TRI, VuPWM = 1. When VuRef <TRI, VuPWM = 0. The upper element gate command signal PWMu1 and the lower element gate command signal PWMx1 are output as follows according to the logical value of the output gate command VuPWM.

[0035]

## EQU00005 ## When VuPWM = 1, PWMu1 = 1, PWMx1 = 0, When VuPWM = 0, PWMu1 = 0, PWMx1 = 1 In the upper element delay generator 15, the gate signal generator 1
4 receives the upper element gate command signal PWMu1, and outputs a new upper element gate command PWMu2 with a delay of a preset delay time. FIG. 4 shows a waveform example when the set delay time is, for example, 1 μsec. In lower element delay generating section 16, lower element gate command signal PWMx1 output from gate signal generating section
And outputs a new lower element gate command PWMx2 with a delay of a preset delay time. FIG. 5 shows a waveform example when the set delay time is, for example, 1 μsec.

Therefore, according to the present embodiment, after the output points of each inverter leg are connected by the coupling reactor 13 and the switching timing of each inverter leg is slightly shifted, each semiconductor element performs high-speed switching. In spite of this, the output voltage is a voltage having a low voltage change rate due to the voltage drop in the coupling reactor 13, and it is possible to reduce the noise current to the ground while performing high-speed switching.

In the above embodiment, a pair of inverter legs is used. However, the present invention is not limited to this, and more inverter legs may be used. FIG.
Shows a configuration example when four inverter legs are connected in parallel to a DC power supply. In this case, each inverter leg 1
Coupling reactors are interposed between the outputs of 1, 12, 17 and 18, respectively, and the load. However, the reactor capacity of each coupling reactor is designed to have a non-identical value, and the total reactor capacity is properly adjusted. Is effective. That is, the inductance value of the coupling reactor with respect to each inverter leg is defined by the first inverter leg inductance L1 and the second inverter leg inductance L1.
2, the third inverter leg inductance L3, and the fourth inverter leg inductance L4, the ratio of the number of turns of each winding to the iron core is set such that L1: L2: L3: L4 = 3: 1: 1: 3. Change and design. As a result, as shown in FIG. 7, the reactor current flowing from the first inverter leg 11 switched first or the fourth inverter leg 18 switched last and the second inverter leg 12 switched later or the second inverter leg 12 switched next Non-uniformity with the reactor current flowing from the third inverter leg 17 that performs switching can be eliminated.

When four or more inverter legs are connected in parallel, the two inverter legs may be connected as a set by a coupling reactor, and the coupling reactors may be connected by another coupling reactor. . The configuration in this case will be described with reference to FIG.

The inverter device shown in FIG. 8 includes a first inverter leg 11, a second inverter leg 12, a first first-stage coupling reactor 31, a third inverter leg 17, and a fourth inverter leg. 18, a second first-stage coupling reactor 33, a second-stage coupling reactor 35,
Gate signal generator 14 and first upper element delay generator 50
A first lower element delay generator 51, a second upper element delay generator 52, a second lower element delay generator 53, a third upper element delay generator 54, Element delay generator 55
It is composed of The first inverter leg 11, the second inverter leg 12, and the first first-stage coupled reactor 3
1, the operation of the gate signal generator 14, the first upper element delay generator 50, and the operation of the first lower element delay generator 51 are the same as those of the first embodiment.

In the second upper element delay generator 52,
The upper element gate command signal PWMu2 output from the first upper element delay generator 50 is input, and a new upper element gate command PWMu3 with a delay of a preset delay time is output. In the third upper element delay generator 54, the upper element gate command signal PWMu3 output from the second upper element delay generator 52 is input, and a new upper element with a delay of a preset delay time is input. The gate command PWMu4 is output. In the second lower element delay generator 53, the lower element gate command signal PWMx2 output from the first lower element delay generator 51 is input, and a new lower element with a delay of a preset delay time is input. The gate command PWMx3 is output. In the third lower element delay generator 55, the lower element gate command signal PWMx3 output from the second lower element delay generator 53 is input, and a new lower element having a preset delay time is transmitted. A gate command PWMx4 is output.

The third inverter leg 17 includes an upper semiconductor switching element 171, an upper reverse conducting diode 172, a lower semiconductor switching element 173, and a lower reverse conducting diode 174, similarly to the inverter leg of the conventional voltage source inverter. Be composed. The upper semiconductor switching element 171 performs a switching operation according to the upper element gate command signal PWMu3 output from the second upper element delay generator 52.

[0042]

## EQU6 ## When PWMu3 = 1, the upper semiconductor switching element 171 is turned on. When PWMu3 = 0, the upper semiconductor switching element 171 is turned on.
1 off The lower semiconductor switching element 173 outputs the lower element gate command signal PW output from the second lower element delay generator 53.
The switching operation is performed according to Mx3.

[0043]

When PWMx3 = 1, the lower semiconductor switching element 173 is turned on. When PWMx3 = 0, the lower semiconductor switching element 173 is turned on.
3 OFF The fourth inverter leg 18 includes an upper semiconductor switching element 181, an upper reverse conducting diode 182, a lower semiconductor switching element 183, and a lower reverse conducting diode 184, similarly to the inverter leg of the conventional voltage source inverter.
It is composed of

The upper semiconductor switching element 181 performs a switching operation according to the upper element gate command signal PWMu4 output from the third upper element delay generator 54.

[0045]

## EQU8 ## When PWMu4 = 1, the upper semiconductor switching element 181 is turned on. When PWMu4 = 0, the upper semiconductor switching element 181 is turned on.
1 off The lower semiconductor switching element 183 is connected to the lower element gate command signal PW output from the third lower element delay generator 54.
The switching operation is performed according to Mx4.

[0046]

## EQU9 ## When PWMx4 = 1, the lower semiconductor switching element 183 is turned on. When PWMx4 = 0, the lower semiconductor switching element 18 is turned on.
3 off The second first-stage coupling reactor 33 includes: a wiring from a portion where the emitter of the upper semiconductor switching element 171 and the collector of the lower semiconductor switching element 173 of the third inverter leg 17 are connected; Leg 18
The wiring from the portion where the emitter of the upper semiconductor switching element 181 and the collector of the lower semiconductor switching element 184 are connected, and the wiring to the second-stage coupling reactor 35 are connected. The wiring from the output of the first first-stage coupling reactor 31, the wiring from the output of the second first-stage coupling reactor 33, and the wiring to the load are connected to the second-stage coupling reactor 35.

With the inverter device of this configuration, the inductance value of the coupling reactor connected to each inverter leg can be made the same regardless of the switching order, and the cost can be easily reduced by mass production of standard products. Become.

FIG. 9 is a diagram showing a configuration of an inverter device according to a second embodiment of the present invention. As a feature, based on the resonance cycle of the resonance current superimposed on the load current,
This is because a delay time setting unit 21 for adjusting the delay time in the delay generation units 15 and 16 so as to reduce the resonance current is provided.

The delay time setting unit 21 includes a frequency analysis unit 21
1, a reduced harmonic frequency selection section 212, and a delay time calculation section 213. Frequency analysis unit 211
, The inverter load current detection value is input and
The relationship between the harmonic frequency and the current amplitude at each frequency is analyzed by fast Fourier transform (FFT). The reduced harmonic frequency selecting section 212 selects and outputs the harmonic frequency fres to be reduced most based on the current harmonic analyzed by the frequency analyzing section 211. For example, from 500 kHz
The frequency with the highest current amplitude in the range of 1 MHz is
Output as s. In the delay time calculation unit 213,
Using the harmonic frequency fres output from the reduced harmonic frequency selection section 212 as an input, a delay time Td is obtained and output by the following calculation.

[0050]

(Equation 10) Even if this equation is replaced by the following equation, there is an effect of reducing the resonance harmonic current.

[0051]

[Equation 11] The delay time Td is input to the upper element delay generator 15 and the lower element delay generator 16, and each delay generator outputs a gate command signal transmitted by the input delay time Td. Specifically, for example, a delay time equal to or more than ４ and equal to or less than ／ of the resonance cycle is set.

Therefore, according to the present embodiment, after connecting the output points of the respective inverter legs by the coupling reactor 13 and shifting the switching timing of the respective inverter legs by a delay time capable of reducing the resonance current, the respective semiconductor devices are connected to each other. Although the switching element is performing high-speed switching, the output voltage is a voltage having a low voltage change rate due to the voltage drop in the coupling reactor 13, and the ground wave of the specific harmonic is most effectively performed while performing high-speed switching. The current can be reduced.

It is needless to say that the above embodiment can be applied to an inverter device having a configuration in which four or more inverter legs are used as shown in FIG. 6 or FIG.

FIG. 10 is a diagram showing a configuration of an inverter device according to a third embodiment of the present invention. The feature is that a delay time setting unit 23 that detects the total amount of harmonics in the load current and adjusts the delay time in the delay generation units 15 and 16 so as to minimize the total amount of harmonics is provided.

The delay time setting unit 22 includes a frequency analysis unit 22
1, a load current total harmonic amount calculation unit 222, and a delay time calculation unit 223. The frequency analysis unit 221 analyzes the relationship between the harmonic frequency and the current amplitude at each frequency by fast Fourier transform (FFT) using the inverter load current detection value as an input. In the load current harmonic total amount calculation unit 222, the harmonic frequency f (N) output from the frequency analysis unit 221 and the current amplitude I
(N) as an input and the total harmonic amount Ial by the following calculation
Find and output l.

[0056]

(Equation 12) The operation of the delay time calculator 223 will be described with reference to FIG. In the delay time calculation unit 223, the total harmonic amount Ia
With the input of ll and the previously output delay time Td, a new delay time Td is calculated and output by the following algorithm.

When the delay time Td is increased, (1) the total harmonic amount Iall decreases → the delay time Td is further increased. (2) The harmonic total amount Iall increases → the delay time Td is reduced. The delay time Td is reduced. (1) The total harmonic amount Iall decreases → further reduces the delay time Td. (2) The total harmonic amount Iall increases → increases the delay time Td. The delay time Td is lower than that of the upper element delay generator 15. Input to the element delay generator 16, each delay generator outputs a gate command signal sent for the input delay time Td.

Therefore, according to the present embodiment, after the output points of each inverter leg are connected by the coupling reactor 13, the switching timing of each inverter leg is shifted by the delay time at which the total amount of harmonics is minimized. Although each semiconductor switching element is performing high-speed switching, the output voltage is a voltage having a low voltage change rate due to a voltage drop in the coupling reactor 13, and the most effective switching of the specific harmonic is performed while performing high-speed switching. The noise current to the ground can be reduced.

It is needless to say that the above embodiment can be applied to an inverter device having a configuration in which four or more inverter legs are used as shown in FIG. 6 or FIG.

FIG. 12 is a diagram showing a configuration of an inverter device according to a fourth embodiment of the present invention. The feature is that a capacitor 43 is connected between the three phases of the load. 12, the same reference numerals as those in FIG. 1 indicate the same components.

Therefore, according to the present embodiment, first and second reactors 41 and 4 connected to the outputs of first and second inverter legs 11 and 12 respectively.
2 is connected to the capacitor 43 to suppress harmonics as an LC filter, and, like the coupling reactor in the first embodiment, the voltage of the first inverter leg 11 and the voltage of the second inverter leg 12. It has the function of suppressing the short-circuit current flowing due to the difference with the voltage, and thus the harmonic current can be further suppressed by the combined effect of suppressing the generation of the harmonic current by the delay circuit and reducing the harmonic by the LC filter.

The above-described embodiment is directed to an inverter device having a configuration in which four or more inverter legs as shown in FIGS. 6 and 8 are used, or FIGS.
Needless to say, the present invention can be applied to an inverter device having a configuration such as 0.

On the other hand, as shown in FIG. 13, a resistor 1 is connected to an iron core as a coupling reactor in each of the above-described embodiments.
A configuration in which windings short-circuited at 31 may be provided. By using such a coupling reactor, the circulating current circulating through the first inverter leg 11, the coupling reactor, and the second inverter leg 12 is attenuated by the resistor 131, and the semiconductor switching element due to an excessive current. Damage and heat generation can be suppressed.

FIG. 14 shows a case where the inverter device in each of the above embodiments is modularized for each phase.
FIG. 15 shows an example in which a three-phase inverter device is configured using this module. The connection terminal from the outside is the same as the conventional 2in1 semiconductor switching element module, and is characterized in that only the internal configuration is different. External connection terminals include a DC positive side voltage connection terminal DC +, a DC negative side voltage connection terminal DC−, and a load output terminal Output.
And Gat for inputting upper element gate command signal PWMu1
eU and G for inputting the lower element gate command signal PWMx1
ataX. As a result, the connection is the same as that of the conventional semiconductor switching device, so that the device designer can reduce the noise current to the ground without taking special external circuits such as coupling reactors or taking control measures such as the occurrence of gate delay. Can be achieved.

In each of the above embodiments,
For the sake of simplicity, only the U-phase configuration has been described, but it goes without saying that the same configuration and operation apply to other V-phases and W-phases.

[0066]

As described above, according to the first and second aspects of the present invention, the output point of the inverter leg composed of two series semiconductor switching elements for short-circuiting a DC voltage is connected by a coupling reactor. Above, the switching timing of each inverter leg is slightly shifted, so that the output voltage is low due to the voltage drop in the coupling reactor even though each semiconductor switching element is performing high-speed switching. Is output, and the ground noise current can be reduced while performing high-speed switching.

According to the third aspect of the present invention, the output point of the inverter leg composed of two series semiconductor switching elements for short-circuiting a DC voltage is connected by a coupling reactor, and then the ON / OFF signal from the gate signal generating means is turned on. Since the switching timing of each inverter leg based on the OFF command signal is shifted by a delay, the output voltage is reduced by the voltage drop in the coupling reactor even though each semiconductor switching element performs high-speed switching. A low voltage is output, and it is possible to reduce the noise current to the ground while performing high-speed switching.

According to the fourth aspect of the invention, the inverter leg composed of two series semiconductor switching elements for short-circuiting a DC voltage is composed of two or more for each phase of UVW, and the output points of each inverter leg are connected. Since the switching timing of each inverter leg is slightly shifted sequentially after connecting with a reactor, the output voltage changes due to the voltage drop in the coupling reactor even though each semiconductor element performs high-speed switching. A voltage with a low rate is output, and it is possible to reduce the noise current to the ground while performing high-speed switching.

According to the fifth aspect of the present invention, the reactor capacity of the coupling reactor connected to each inverter leg is intentionally designed so as not to have the same value according to the order of the switching delay of the inverter leg. The capacity can be optimized.

According to the sixth aspect of the present invention, since the inductance values of the coupling reactors connected to the respective inverter legs are the same regardless of the switching order, it is easy to reduce the cost by mass-producing standard products. Can be realized.

According to the seventh and eighth aspects of the present invention,
Since the delay time is adjusted to reduce the resonance current and minimize the total amount of harmonics, the output voltage is coupled even though each semiconductor switching element performs high-speed switching. Due to the voltage drop in the reactor, a voltage having a low voltage change rate is output, and it is possible to most effectively reduce the noise current of the specific harmonic to the ground while performing high-speed switching.

According to the ninth aspect of the present invention, the harmonics are suppressed as an LC filter by the reactor and the capacitor constituting the coupling reactor. Suppression can be achieved.

According to the tenth aspect of the present invention, since the current circulating between the inverter legs via the coupling reactor is attenuated, damage and heat generation of the semiconductor switching element due to an excessive current can be suppressed. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an inverter device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a coupling reactor included in the inverter device according to the first embodiment.

FIG. 3 is a diagram for explaining the operation of the first embodiment.

FIG. 4 is a diagram for explaining the operation of the first embodiment.

FIG. 5 is a diagram for explaining the operation of the first embodiment.

FIG. 6 is a diagram showing a modification of the first embodiment.

FIG. 7 is a diagram for explaining the operation of the modification.

FIG. 8 is a diagram showing another modified example of the first embodiment.

FIG. 9 is a diagram illustrating a configuration of an inverter device according to a second embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of an inverter device according to a third embodiment of the present invention.

FIG. 11 is a diagram for explaining the operation of the third embodiment.

FIG. 12 is a diagram illustrating a configuration of an inverter device according to a fourth embodiment of the present invention.

FIG. 13 is a diagram showing another configuration example of the coupling reactor.

FIG. 14 is a diagram showing a configuration example when the inverter device according to the present invention is modularized.

FIG. 15 is a diagram showing a configuration example when the inverter device according to the present invention is modularized.

FIG. 16 is a diagram showing a conventional configuration.

[Description of Signs] 11 First inverter leg 12 Second inverter leg 13 Coupling reactor 14 Gate signal generator 15 Upper element delay generator 16 Lower element delay generator 17 Third inverter leg 18 Fourth inverter leg 21 , 23 Delay time setting unit 31 First first-stage coupling reactor 33 Second first-stage coupling reactor 35 Second-stage coupling reactor 41 First reactor 42 Second reactor 43 Capacitor 50 First upper element delay generation Unit 51 first lower element delay generator 52 second upper element delay generator 53 second lower element delay generator 54 third upper element delay generator 55 third lower element delay generator 101, 102, 103 Inverter legs 111, 121, 171, 181 Upper semiconductor switching elements 112, 122, 172, 182 Upper reverse Through diodes 113, 123, 173, 183 Lower semiconductor switching elements 114, 124, 174, 184 Lower reverse conducting diodes 211, 221 Frequency analyzer 212 Reduced harmonic frequency selectors 213, 223 Delay time calculator 222 Load current Harmonic total calculation section

Claims (10)

[Claims] 1. A pair of inverter legs for short-circuiting a DC voltage, connected in series, outputting an AC voltage from a connection point of the series connection of the two switching devices, and a pair of inverter legs. The coupling reactor connected between the output of each AC voltage and the load, and the short-circuit timing of the switching element constituting one of the pair of inverter legs of the pair of inverter legs, the other corresponding to the switching element. And a short-circuit timing adjusting means for shifting a short-circuit timing of a switching element constituting the inverter leg for each phase. 2. The short-circuit timing adjusting means delays a short-circuit timing of a switching element constituting one inverter leg with respect to a short-circuit timing of a switching element constituting one inverter leg. 2. The inverter device according to claim 1, wherein the inverter device is a means. 3. An inverter device for generating and outputting a desired AC voltage from a DC voltage, wherein the first inverter leg and the second inverter each include two series-connected semiconductor switching elements for short-circuiting the DC voltage. And a coupling reactor that connects the intermediate points of the series-connected semiconductor switching elements of the first and second inverter legs to each other and supplies power to the load from the intermediate point, and forms a first inverter leg. A gate signal generating means for outputting an on / off command signal to each of the two semiconductor switching elements; a semiconductor for the first inverter leg by delaying the on / off command signals output from the gate signal generating means by a predetermined time; The semiconductor switching element of the second inverter leg corresponding to the switching element Inverter device and having a delay means for respectively outputting each phase. 4. A DC positive potential side switching element and a DC negative potential side switching element for short-circuiting a DC voltage connected in series between DC power supplies, and the two switching elements are connected in series. A plurality of inverter legs connected in parallel to the DC power supply that outputs an AC voltage from a point; a coupling reactor connected between each AC voltage output of the inverter legs and a load; A gate signal generating means for outputting an on / off command signal to each of the two switching elements constituting the leg, and an on / off command signal output from the gate signal generating means for a corresponding switching element of another inverter leg And a delay means for supplying a delay while sequentially delaying each phase. 5. The reactor according to claim 4, wherein the coupling reactors have respective reactor capacities set in accordance with the order in which on / off command signals are supplied to switching elements constituting each inverter leg. Inverter device. 6. The coupling reactor includes a first-stage coupling reactor connected to each AC voltage output of the inverter leg, and a second-stage coupling reactor combining the first-stage coupling reactor in a predetermined combination. The inverter device according to claim 4, wherein: 7. The inverter device according to claim 2, wherein said delay means sets a delay time based on a resonance cycle of a current supplied to a load. 8. The inverter device according to claim 2, wherein said delay means sets a delay time based on a total harmonic amount of a current supplied to a load. 9. The inverter device according to claim 1, further comprising a capacitor for connecting the phases of the load. 10. The inverter device according to claim 1, wherein the coupling reactor is formed by winding a wire short-circuited by a resistor on an iron core constituting the coupling reactor.