JP2000092703A - Input/output buffer circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration and destruction of a group of LSIs in different kinds of power supply systems, by inputting one rank higher power supply voltages to voltage regulators, and by correcting the natural logarithmic discharging characteristic between each of the power supplies at the time of power interruption in response to each load condition of the power supplies. SOLUTION: Correcting capacity 71 is provided for correcting the natural logarithmic discharging characteristic at the time of power interruption. Also, this device is structured in such a way that power in inputted from power supply higher by one rank into each of voltage regulators 2, 3. Then, when power is impressed, each input voltage raises the output sides in sequence with the minimum drop voltage of the voltage regulators 2, 3 so that the power supply secures the electric potential of VCC1>VCC2>VCC3, a condition needed to be observed. On the other hand, when the power supply unit 1 is turned off, the addition of the correcting capacity 71 makes it possible to maintain VCC1>VCC2>VCC3, a condition needed to be observed at the time of power interruption. As a result, the deterioration and destruction of a group of LSIs can be prevented in different kinds of power supply systems.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control controller or a power sequence circuit device of an information processing apparatus, and more particularly, to a withstand voltage protection of a power receiving side LSI due to a potential difference between different power sources when a power source is turned on and off in a mixed power source system. The present invention relates to a power sequence circuit device for protecting an LSI from deterioration and destruction.

[0002]

2. Description of the Related Art In recent years, in a control controller or an information processing apparatus, a heterogeneous power supply mixed system requiring a plurality of power supply voltages in the system has been constructed and demanded. At this time, in order to protect the mounted LSI, it is necessary to pay attention to the potential reversal and the potential difference between the different types of power supplies particularly when the power is turned on and off, which is a problem.

The contents are as follows. (1) LS
When a voltage equal to or higher than the power supply voltage VCC is applied to the input of I, the gate oxide film of the MOS transistor of the input circuit is destroyed. (2) Similarly, when a high electric field is applied to the input, the drain of the MOS transistor of the output circuit is (3) Similarly, when a voltage equal to or higher than the power supply voltage VCC is applied to the input, the reverse bias becomes a forward bias, and a current path is generated in the parasitic diode. May cause latch-up. Therefore,
In a system with a mixture of different power sources, care is taken to prevent the voltage values of the power sources from being reversed, particularly when the power is turned on and turned off in a state other than the normal operation state. Generally, a procedure is followed in which a high power supply is turned on first when the power supply is turned on, and a high power supply is turned off later when the power supply is turned off. Furthermore, (4) Some LSIs have a built-in tolerant circuit that allows the application of a voltage higher than the power supply voltage to the input. It is necessary to pay attention not to increase the mutual potential difference value other than the reverse rotation holding.

FIG. 5 shows one of the conventional examples. The plurality of different power supplies indicate VCC1>VCC2> VCC3. For example, VCC1 = 5.0V, VCC2 = 3.3V, VCC3 =
1.8V. The power supply unit 1 generates VCC, the capacity (C5) 11 is a capacity connected to an output terminal in the power supply unit 1, and the voltage regulator 2 is configured such that the transistor 21 is connected in series to the input side (VCC1) and the output side (VCC2) in an example. In an example, the voltage regulator 4 is an IC that generates a VCC2 from the power supply VCC1 by connecting and connecting the transistors 41 to the input side (VCC1) and the output side (VCC3).
The load capacity (CL5) 5 is the total load capacity of the load-side LSI that receives the power supply VCC1, and the load resistance (RL5) 6 is the load-side LSI that receives the power supply VCC1. Consumption current (i5)
The total load resistance and load capacity (CL 3.3) 7
The total load capacity and load resistance (RL3.3) 8 of the load-side LSI receiving the CC2 are the load-side LSI receiving the power VCC2.
The total load resistance and load capacitance (CL1.8) 9 for the current consumption (i3.3) of the
I total load capacity, load resistance (RL1.8) 10 is power supply VC
This is the total load resistance with respect to the current consumption (i1.8) of the load-side LSI that receives C3. When the power supply unit 1 is turned on, the voltage rises due to the active operation of the voltage regulators 2 and 3, but as shown in FIG.
Since the input is set to VCC1 like VCC2, the power supply rises faster than VCC2 in some cases, and the potential of VCC2> VCC3, which is a matter to be observed, cannot be secured. On the other hand, FIG. 7 shows when the power supply unit 1 is turned off. In the operation shown in the figure, the point a is the start point of the drop of VCC1, and the point b is the VC due to the minimum voltage drop of the voltage regulator.
The drop point of C2, the point b 'is the drop point of VCC3 due to the minimum voltage drop of the voltage regulator, and the point c is the output stop point of VCC1. At the beginning (a to c) at the time of cutoff, VCC1>
Although VCC2> VCC3 is maintained, natural logarithmic discharge occurs in the inactive state (c to) due to a decrease in the power supply voltage, and conditions on the load side (C5, CL5, RL5 / CL3.3, RL3.
3 / CL1.8, RL1.8) determines the discharge operation of each power supply voltage. Therefore, C is connected between VCC1 and VCC2.
Since 5 >> CL3.3, the ratio of RL5 and RL3.3 is absorbed and the discharge time of VCC1 and VCC2 can secure t5> t3.3. However, the discharge time t3.3 = −3.3 between VCC2 and VCC3 depending on the load condition. CL3.3 ・ RL3.3 ・ ln (V0 /
VCC3.3), t1.8 = -CL1.8.RL1.8.l
From n (V0 / VCC1.8), t3.3> t1.8 cannot be ensured, that is, there is a case where VCC3> VCC2 is reversed.

As another conventional method, there is also a forced discharge method by time control when the power supply is cut off. However, 1) the circuit scale is increased. 2) Depending on the time control, the potential difference VCC3 is zero and the potential of VCC2 is reduced due to the fall time difference between the power supplies. 3) If the discharge speed of the power supply terminal by the forced discharge circuit is too fast than that of the IC group input terminal, latch-up may occur and affect the IC elements.

[0006]

In the power sequence circuit device described above, a plurality of power supply voltages are operated as VCC1>VCC2> VCC3 when the different types of power supplies are turned on and off, and the potential difference between the power supplies is set to <VCC1, <VCC1. VC
The circuit configuration is to secure C2.

[0007]

In the power sequence circuit device of the present invention, the input of the voltage regulator is a power supply voltage one rank higher, and the natural logarithmic discharge characteristics between the power supplies when the power supply is cut off correspond to the mutual power supply load conditions. Then, the correction is performed only with the additional capacity.

According to the present invention, in a plurality of heterogeneous power supply systems, it is possible to realize a simple power sequence circuit device capable of protecting the LSI group in the system from deterioration and destruction.

[0009]

FIG. 1 shows an embodiment of an input / output buffer circuit device according to the present invention.

The power supply unit 1 generates VCC and has a capacity
(C5) 11 is a capacitor connected to the output terminal in the power supply unit 1, and the voltage regulator 2 is an IC that generates the VCC2 from the power supply VCC1 by connecting the transistor 21 to the input side (VCC1) and the output side (VCC2) in series. , The voltage regulator 3 has the transistor 31 on the input side
(VCC2) and an output side (VCC3) are connected in series to generate VCC3 from the power supply VCC2. The load capacity (CL5) 5 is the total load capacity and load resistance (RL5) of the load side LSI receiving the power supply VCC1. 6 is the total load resistance with respect to the current consumption (i5) of the load side LSI receiving the power supply VCC1,
The load capacity (CL 3.3) 7 is the total load capacity of the load-side LSI receiving the power supply VCC2, the capacity (CLadd) 71 is a capacitor for correcting the natural logarithmic discharge characteristic when the power supply is cut off,
The load resistance (RL3.3) 8 is the total load resistance for the consumption current (i3.3) of the load-side LSI receiving the power supply VCC2, and the load capacitance (CL1.8) 9 is the total load of the load-side LSI receiving the power supply VCC3. The capacitance and load resistance (RL1.8) 10 are the current consumption (i1.8) of the load-side LSI receiving the power supply VCC3.
Is the total load resistance. In this circuit configuration, when the power supply unit 1 is powered on, the active operation and the input of the voltage regulators 2 and 3 become 1 respectively.
Since the input voltage rises at the minimum voltage drop of the voltage regulator, the output side rises in order by the configuration of supplying power from the rank higher power supply. As shown in FIG. it can. On the other hand, the operating characteristics when the power supply unit 1 is shut off are shown in FIG. In the operation in the figure, the point a is the point where VCC1 starts to decrease,
Point b is the drop point of VCC2 due to the minimum voltage drop of the voltage regulator, point b 'is the drop point of VCC3 due to the minimum drop voltage of the voltage regulator, and point c is V
This is the output stop point of CC1. At the beginning of the cutoff (ac), VCC1>VCC2> VCC3 can be maintained by the active operation of the voltage regulators 2 and 3. In addition, in a non-active state (c to) due to a drop in the power supply voltage, each power supply voltage is set to a load-side condition (C5, CL5, RL5 / CL3.
3, RL3.3 / CL1.8, RL1.8), but the natural logarithmic discharge characteristic is determined by C5 >> CL between VCC1 and VCC2.
Since the ratio is 3.3, the ratio of RL5 and RL3.3 is absorbed, and the discharge time of VCC1 and VCC2 can satisfy t5> t3.3. Further, even if the load condition is reversed between VCC2 and VCC3, the natural logarithmic characteristic is corrected only by the additional capacitor 71 connected to the VCC2 line, so that VCC1>VCC2> V.
CC3 can be secured. The magnitude of the load condition is a ratio of the total load capacity of each load, which is a function value of the discharge time, the consumption current value, and the power supply voltage value. That is, (CL3.3 + C
Ladd) · VCC 3.3 / i 3.3 vs CL 1.8 · VCC
1.8 / i1.8. FIG. 4 shows the discharge characteristic formula and the formula for deriving the correction capacitance value. The discharge time of VCC2 and VCC3 is t3.3 =-(CL3.3 + CLadd) .RL3.3
Ln (V0 / Vcc 3.3), t1.8 = -CL1.8
RL1.8 · ln (V0 / Vcc1.8), and the correction capacitance value is (CL3.3 + CLadd) · V depending on the load condition.
CC3.3 / i3.3 ≧ CL1.8.VCC1.8 / i1.
8 Therefore, by adding the correction capacitor CLadd, t3.3> t1.8 can be ensured, and it is possible to maintain the compliance items VCC1>VCC2> VCC3 when the power is turned off. In addition, the potential difference value between the power supplies, which is the other compliance item, is also activated by the active operation (in the vicinity of VCC1-VCC2) <VCC1, (in the vicinity of VCC2-VCC3) <V
CC2 can be secured.

[0011]

According to the present invention, in a multiple heterogeneous power supply system such as a control controller or an information control processing device, a simple and effective effect of protecting a group of LSIs to which power is supplied from withstand voltage, preventing deterioration and destruction of elements. A power sequence circuit device having a simple circuit configuration can be realized.

[Brief description of the drawings]

FIG. 1 shows a power sequence circuit device according to an embodiment of the present invention.

FIG. 2 is an operation waveform of a power sequence circuit device according to one embodiment of the present invention.

FIG. 3 is an operation waveform of the power sequence circuit device according to one embodiment of the present invention.

FIG. 4 is a discharge characteristic of the power sequence circuit device according to one embodiment of the present invention.

FIG. 5 is a power sheath circuit device according to a conventional example.

FIG. 6 is an operation waveform of a power sheath circuit device according to a conventional example.

FIG. 7 is an operation waveform of a power sheath circuit device according to a conventional example.

[Explanation of Signs] 1. Power supply unit, 2, 3 ... Voltage regulator,
5, 7, 9 ... load capacity, 6, 8, 10 ... load resistance, 11
... capacitance, 21, 31 ... transistor, 71 ... correction capacity.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsutomu Yamada 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Kenichi Kurosawa 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 F-term (reference) in Hitachi, Ltd. Omika Plant 5G065 BA01 DA07 EA01 FA02 GA06 HA05 HA06 JA02 KA02 KA05 MA09 MA10 NA01

Claims (3)

[Claims] In a power sequence circuit device of a heterogeneous power supply mixed system in which a plurality of power supplies are applied to and cut off from an LSI group, a discharge characteristic is corrected only by a capacity in order to maintain a power supply voltage level and secure a potential difference when the power supply is cut off. A power sequence circuit device. 2. A power sequence circuit device of a heterogeneous power supply mixed system for applying and shutting down a plurality of power supplies to a group of LSIs. A power sequence circuit device supplied from a power source on a rank. 3. The power sequence circuit device according to claim 1, wherein a correction capacitor is added to the second power supply VCC2.