JP2000091513A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000091513A JP2000091513A JP11181675A JP18167599A JP2000091513A JP 2000091513 A JP2000091513 A JP 2000091513A JP 11181675 A JP11181675 A JP 11181675A JP 18167599 A JP18167599 A JP 18167599A JP 2000091513 A JP2000091513 A JP 2000091513A
- Authority
- JP
- Japan
- Prior art keywords
- film
- hydrogen
- semiconductor device
- insulating film
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、ＰＺＴ（Ｐｂ（ＴｉxＺｒy）
Ｏ3）などの強誘電体膜を用いたキャパシタ構造を有す
る半導体メモリや多結晶シリコン・ゲートを用いたＣＭ
ＯＳ半導体集積回路における保護膜構造及びその成膜法
に関するものである。The present invention relates to relates to a semiconductor device and a manufacturing method thereof, in particular, PZT (Pb (Ti x Zr y)
Semiconductor memory having a capacitor structure using a ferroelectric film such as O 3 ) or CM using a polycrystalline silicon gate
The present invention relates to a protective film structure in an OS semiconductor integrated circuit and a method for forming the same.
【０００２】[0002]
【従来の技術】従来、強誘電体を用いたストレージ・キ
ャパシタ構造を有する半導体不揮発性メモリ・セルは、
例えば図６に示す構造を備えている。このメモリ・セル
は、単一の転送ゲート・トランジスタ（ＭＯＳトランジ
スタ）Ｔに強誘電体膜を用いたストレージ・キャパシタ
（コンデンサ）Ｃを直列接続したものである。転送ゲー
ト・トランジスタＴは、ｐ型半導体基板１の上にゲート
絶縁膜２を介して形成されて多結晶シリコン・ゲート３
と、この多結晶シリコン・ゲート３をマスクとしてｐ型
半導体基板１の表面側にセルフアラインで形成された高
濃度ｎ型領域たるソース・ドレイン領域４，５とから構
成されている。なお、ソース・ドレイン領域4はビット
線に、多結晶シリコン・ゲート３はワード線にそれぞれ
接続されている。一方、ストレージ・キャパシタＣはフ
ィールド酸化膜たるＬＯＣＯＳ（局所酸化膜）６上に溝
成されている。ＬＯＣＯＳ６，多結晶シリコン・ゲート
３の上には、例えばＣＶＤによりＳｉＯ2又はスパッタ
法によるＳｉＮの第１の層間絶縁膜７が形成され、この
層間絶縁膜７のうちＬＯＣＯＳ６の真上にスパッタ法で
白金（Pt）の下部平板電極８が形成される。この下部平
板電極８上の一部にはスパッタ法又は塗布法により強誘
電体たるＰＺＴ（Ｐｂ（Ｔｉx Ｚｒy）Ｏ3）の誘電体膜
９が形成され、またこの誘電体膜９の上にはスパッタ法
で白金の上部平板電極１０が形成される。次に、第１の
層間絶縁膜７の上には例えばＣＶＤによるＳｉＯ2又は
スパッタ法によるＳｉＮの第２の層間絶縁膜１１が形成
され、この層間絶縁膜１１の上にスパッタ法によりＡｌ
配線が形成される。Ａｌ配線１２ａはソース・ドレイン
領域５と上部平板電極１０とをコンタクト穴を介して導
通させるセル内部配線で、Ａｌ配線１２ｂは下部平板電
極８と図示しないパッド部とを導通させる接地配線であ
る。なお、図６には示されていないが、多結晶シリコン
・ゲート３に導通するワード線及びソース・ドレイン領
域４に導通するビット線は上記Ａｌ配線と同一層に形成
されている。Ａｌ配線１２ａ，１２ｂの上にはスパッタ
法によるＳｉＮのパッシベーション膜１３が形成されて
いる。2. Description of the Related Art Conventionally, a semiconductor nonvolatile memory cell having a storage capacitor structure using a ferroelectric material has
For example, it has a structure shown in FIG. In this memory cell, a single transfer gate transistor (MOS transistor) T and a storage capacitor (capacitor) C using a ferroelectric film are connected in series. The transfer gate transistor T is formed on a p-type semiconductor substrate 1 via a gate insulating film 2 to form a polycrystalline silicon gate 3.
And source / drain regions 4 and 5 which are high-concentration n-type regions formed by self-alignment on the surface side of p-type semiconductor substrate 1 using polycrystalline silicon gate 3 as a mask. The source / drain region 4 is connected to a bit line, and the polysilicon gate 3 is connected to a word line. On the other hand, the storage capacitor C is formed on a LOCOS (local oxide film) 6 which is a field oxide film. On the LOCOS 6 and the polycrystalline silicon gate 3, for example, a first interlayer insulating film 7 of SiO 2 or SiN is formed by sputtering by CVD, and the first insulating film 7 of the interlayer insulating film 7 is formed on the LOCOS 6 by sputtering. A lower plate electrode 8 of platinum (Pt) is formed. The dielectric film 9 of the portion of the lower plate electrode 8 serving ferroelectric by a sputtering method, a coating method, or PZT (Pb (Ti x Zr y ) O 3) is formed, also on the dielectric film 9 The upper flat plate electrode 10 of platinum is formed by sputtering. Next, a second interlayer insulating film 11 of, for example, SiO 2 by CVD or SiN by sputtering is formed on the first interlayer insulating film 7, and an Al film is formed on the interlayer insulating film 11 by sputtering.
Wiring is formed. The Al wiring 12a is a cell internal wiring that connects the source / drain region 5 and the upper plate electrode 10 through the contact hole, and the Al wiring 12b is a ground wiring that connects the lower plate electrode 8 and a pad (not shown). Although not shown in FIG. 6, the word line conducting to the polysilicon gate 3 and the bit line conducting to the source / drain region 4 are formed in the same layer as the Al wiring. On the Al wirings 12a and 12b, a passivation film 13 of SiN is formed by a sputtering method.
【０００３】[0003]
【発明が解決しようとする課題】誘電体膜９に使用され
る強誘電体たるＰＺＴ（Ｐｂ（Ｔｉx Ｚｒy）Ｏ3）は電
界に対してヒステリシス曲線を持ち、書き込み電圧を取
り除くと、残留分極を保持し続けるため、上述のような
不揮発性メモリとして利用されたり、また比誘電率が約
１０００程度の値でＳｉＯ2膜と比較して２桁以上も大
きいので、ダイナミックＲＡＭのキャパシタとしても利
用される。Serving ferroelectric is used in the dielectric film 9 [0005] PZT (Pb (Ti x Zr y ) O 3) has a hysteresis curve to an electric field, when removing the write voltage, the residual It is used as a non-volatile memory as described above to keep the polarization, and has a relative dielectric constant of about 1000, which is two orders of magnitude or more larger than that of a SiO 2 film, so it can be used as a capacitor of a dynamic RAM. Used.
【０００４】しかしながら、水素に晒されると残留分極
の値が減少してしまい、記憶機能に必要な２値論理の幅
（マージン）が狭くなる。また比誘電率の値も低下す
る。このような特性劣化は歩留りの低下を招くので、誘
電体膜９の形成工程の後においては水素を誘電体膜９に
晒さないような成膜法に顧慮する必要がある。However, when exposed to hydrogen, the value of the remanent polarization decreases, and the width (margin) of the binary logic required for the storage function decreases. Also, the value of the relative dielectric constant decreases. Since such a characteristic deterioration causes a decrease in yield, it is necessary to consider a film forming method that does not expose hydrogen to the dielectric film 9 after the step of forming the dielectric film 9.
【０００５】プラズマＣＶＤ法によるＳｉＮや常圧又は
減圧ＣＶＤ法によるＳｉＯ2の形成にあっては成膜中水
素雰囲気にあるため、これらの膜を誘電体膜９の上部に
形成すると、水素が誘電体膜９へ侵入し、その特性を劣
化させてしまうので、これらの成膜法を採用することは
できない。そこで、上記従来の不揮発性メモリの構造に
おいては、第２の層間絶縁膜１１とパッシベーション膜
１３はスパッタ法の成膜によるＳｉＮ膜とされる。これ
は水素不放出の工程による成膜だからである。一方、パ
ッシベーション膜１３は本来的に耐湿性の緻密な膜質が
要求されるが、スパッタ法によるＳｉＮ膜は膜質の稠密
性に欠け、耐湿性に劣るので、パッシベーション膜とし
ては不向きである。 本発明は上記問題点を解決するも
のであり、その課題は、強誘電体膜の上部にこの強誘電
体膜への水素侵入を防止する成膜法を採用することによ
り、残留分極及び比誘電率の高い強誘電体膜を要素とす
る半導体装置及びその製造方法を提供することにある。In the formation of SiN by plasma CVD or SiO 2 by normal pressure or low pressure CVD, a hydrogen atmosphere is present during the film formation. Therefore, when these films are formed on the dielectric film 9, hydrogen These film forming methods cannot be adopted because they penetrate into the body film 9 and deteriorate its characteristics. Therefore, in the structure of the above-mentioned conventional nonvolatile memory, the second interlayer insulating film 11 and the passivation film 13 are formed as SiN films formed by a sputtering method. This is because the film is formed by a process of non-hydrogen release. On the other hand, the passivation film 13 is inherently required to have a moisture-resistant and dense film quality. However, the SiN film formed by the sputtering method is not suitable as a passivation film because the film quality lacks the denseness and is poor in the moisture resistance. The present invention has been made to solve the above problems, and the problem is to solve the above problem by adopting a film formation method on the ferroelectric film to prevent hydrogen from entering the ferroelectric film, thereby achieving remanent polarization and relative dielectric constant. An object of the present invention is to provide a semiconductor device including a ferroelectric film having a high efficiency as an element and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】殊にＰＺＴなどの耐水素
性に乏しい強誘電体を用いたキャパシタ構造を有する半
導体装置において、本発明の講じた手段は、例えばスパ
ッタ法又は塗布法により形成された強誘電体膜の上部に
水素不放出性の成膜法による耐湿性の水素バリア膜を設
けたものである。この水素バリア膜の被覆範囲は全面に
限らず、キャパシタ構造を覆う範囲にあれば良い。この
水素バリア膜としてはスパッタ法によるＴｉＮ膜でも良
いし、また酸素侵入型のＴｉＯＮでも良い。ＴｉＯＮ膜
の成膜法としては、ＴｉＮ膜の酸素雰囲気でのプラズマ
処理又は熱処理、窒素及び酸素雰囲気中でのＴｉターゲ
ットによるスパッタ法やＴｉＯＮのスパッタ法である。
ＴｉＯＮは酸素含有率が小さいときは導電性で、酸素含
有率が大きいときは絶縁性である。また酸素含有率の高
いＴｉＯＮ膜は水素阻止能が高くなる。In particular, in a semiconductor device having a capacitor structure using a ferroelectric material having poor hydrogen resistance such as PZT, the means taken by the present invention is formed by, for example, a sputtering method or a coating method. A moisture-resistant hydrogen barrier film is formed on the ferroelectric film by a film formation method that does not release hydrogen. The coverage of the hydrogen barrier film is not limited to the entire surface, but may be any range that covers the capacitor structure. The hydrogen barrier film may be a TiN film formed by a sputtering method or an oxygen intrusion type TiON. Examples of the method for forming the TiON film include a plasma treatment or heat treatment of the TiN film in an oxygen atmosphere, a sputtering method using a Ti target in a nitrogen and oxygen atmosphere, and a TiON sputtering method.
TiON is conductive when the oxygen content is low, and is insulative when the oxygen content is high. In addition, a TiON film having a high oxygen content has a high hydrogen stopping power.
【０００７】この水素バリア膜の上に直接又は層間絶縁
膜を介して腐食防止膜（プラズマＣＶＤ法によるＳｉＮ
や常圧又は減圧ＣＶＤ法によるＳｉＯ2など）を被着さ
せた構造も採用される。A corrosion prevention film (SiN film formed by plasma CVD) is formed directly on this hydrogen barrier film or through an interlayer insulating film.
And normal pressure or was deposited and SiO 2) by reduced pressure CVD method structure is also employed.
【０００８】[0008]
【作用】水素不放出性の成膜法による耐湿性の水素バリ
ア膜を強誘電体膜の上部に覆うと、強誘電体膜の形成後
において、プロセス中で発生する水素の当該強誘電体膜
の侵入を防止することができ、残留分極や比誘電率の低
下を回避できる。それ故、残留分極や比誘電率の高い強
誘電体膜を有する半導体装置を得ることができる。水素
バリア膜の上部に腐食防止膜を形成した構造において
は、水素バリア膜の腐食を防止できる。この腐食防止膜
は膜質の緻密性を必要とするので、主にＣＶＤ法による
成膜で、水素放出の成膜法に依らざる得ない。しかし、
下層には水素バリア膜が存在するので、強誘電体への水
素侵入の問題は発生しない。When a moisture-resistant hydrogen barrier film is formed on the upper part of the ferroelectric film by a hydrogen non-releasing film forming method, after the ferroelectric film is formed, the hydrogen generated in the process after the ferroelectric film is formed. Can be prevented, and a decrease in remanent polarization and relative permittivity can be avoided. Therefore, it is possible to obtain a semiconductor device having a ferroelectric film having high remanent polarization and relative permittivity. In the structure in which the corrosion prevention film is formed on the hydrogen barrier film, the corrosion of the hydrogen barrier film can be prevented. Since this corrosion prevention film requires denseness of film quality, the film is mainly formed by the CVD method and cannot be relied on the film formation method of releasing hydrogen. But,
Since there is a hydrogen barrier film in the lower layer, the problem of hydrogen penetration into the ferroelectric does not occur.
【０００９】上記の製造方法は汎用的な手段であるが、
水素バリア膜として絶縁性（酸素含有率が大）のＴｉＯ
Ｎ膜を成膜する場合には、上述の腐食防止膜の成膜工程
を削減できる。Although the above-mentioned manufacturing method is a general-purpose means,
Insulating (high oxygen content) TiO as hydrogen barrier film
When the N film is formed, the step of forming the corrosion prevention film can be reduced.
【００１０】[0010]
【発明の実施の形態】次に、本発明の実施例を添付図面
に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings.
【００１１】［第１実施例］図１は本発明の第１実施例
に係る半導体メモリの構造を示す断面図である。[First Embodiment] FIG. 1 is a sectional view showing a structure of a semiconductor memory according to a first embodiment of the present invention.
【００１２】ｐ型半導体基板１の表面には熱酸化による
ゲート絶縁膜２とＭＯＳのアクティブ領域を区画形成す
べき厚い酸化膜のＬＯＣＯＳ（局所酸化膜）６が形成さ
れる。転送トランジスタＴはゲート絶縁膜２を介して形
成された多結晶シリコン・ゲート３と、この多結晶シリ
コン・ゲート３をマスクとしてｐ型半導体基板１の表面
側にセルフアラインで形成された高濃度ｎ型領域たるソ
ース・ドレイン領域４，５とから構成されている。一
方、ストレージ・キャパシタＣはフィールド酸化膜たる
ＬＯＣＯＳ（局所酸化膜）６上に構成されている。On the surface of the p-type semiconductor substrate 1, a gate insulating film 2 by thermal oxidation and a thick oxide film LOCOS (local oxide film) 6 for forming an active region of a MOS are formed. The transfer transistor T has a polycrystalline silicon gate 3 formed via a gate insulating film 2 and a high-concentration n formed by self-alignment on the surface side of the p-type semiconductor substrate 1 using the polycrystalline silicon gate 3 as a mask. It is composed of source / drain regions 4 and 5, which are mold regions. On the other hand, the storage capacitor C is formed on a LOCOS (local oxide film) 6 which is a field oxide film.
【００１３】先ず、ＬＯＣＯＳ６，多結晶シリコン・ゲ
ート３の上にはＣＶＤにより緻密な第1の層間絶縁膜
（ＳｉＯ2又はＳｉＮ）７が全面形成される。次に、こ
の層間絶縁膜７のうちＬＯＣＯＳ６の真上にスパッタ法
で白金（Pt）の下部平板電極８が形成される。次に、こ
の下部平板電極８上の一部にはスパッタ法又は塗布法に
より強誘電体たるＰＺＴ（Ｐｂ（Ｔｉx Ｚｒy）Ｏ3）の
誘電体膜９が形成される。また次に、この誘電体膜９の
上にはスパッタ法で白金の上部平板電極１０が形成さ
れ、ストレージ・キャパシタＣが得られる。First, a dense first interlayer insulating film (SiO 2 or SiN) 7 is entirely formed on the LOCOS 6 and the polycrystalline silicon gate 3 by CVD. Next, a lower plate electrode 8 made of platinum (Pt) is formed on the interlayer insulating film 7 directly above the LOCOS 6 by a sputtering method. Next, the dielectric film 9 of this part of the lower plate electrode 8 serving ferroelectric by a sputtering method, a coating method, or PZT (Pb (Ti x Zr y ) O 3) is formed. Next, an upper plate electrode 10 made of platinum is formed on the dielectric film 9 by a sputtering method, and a storage capacitor C is obtained.
【００１４】次に、第１の層間絶縁膜７の上にはスパッ
タ法によるＳｉＮの第２の層間絶縁膜（下部層間絶縁
膜）１１が形成される。そして、ソース・ドレイン領域
５，上部平板電極１０，下部平板電極８の部位にコンタ
クト穴が窓明けされる。Next, a second interlayer insulating film (lower interlayer insulating film) 11 of SiN is formed on the first interlayer insulating film 7 by a sputtering method. Then, contact holes are opened in the portions of the source / drain regions 5, the upper plate electrode 10, and the lower plate electrode 8.
【００１５】次に、この層間絶縁膜１１の上にはスパッ
タ法によりＡｌ配線が形成される。Ａｌ配線１２ａはソ
ース・ドレイン領域５と上部平板電極１０とをコンタク
ト穴を介して導通させるセル内部配線で、Ａｌ配線１２
ｂは下部平板電極８と図示しないパッド部とを導通させ
る接地配線である。なお、図１には示されていないが、
多結晶シリコン・ゲート３に導通するワード線及びソー
ス・ドレイン領域４に導通するビット線は上記Ａｌ配線
と同一層に形成されている。Next, an Al wiring is formed on the interlayer insulating film 11 by a sputtering method. The Al wiring 12a is a cell internal wiring for electrically connecting the source / drain region 5 and the upper plate electrode 10 through the contact hole.
Reference numeral b denotes a ground wiring for conducting the lower plate electrode 8 to a pad (not shown). Although not shown in FIG. 1,
The word line connected to the polycrystalline silicon gate 3 and the bit line connected to the source / drain region 4 are formed in the same layer as the Al wiring.
【００１６】次に、Ａｌ配線１２ａ，１２ｂの上にはス
パッタ法によるＳｉＮの第３の層間絶縁膜（上部層間絶
縁膜）１３’が形成されている。勿論、この工程中では
水素不放出であることから、誘電体膜９の特性劣化の問
題は発生しない。第３の層間絶縁膜１３’の膜質は緻密
性に欠けるがので、パッシベーション膜としての意義は
少なく、後述するように、導電性で耐湿性の水素バリア
膜１４とＡｌ配線１２ａ，１２ｂとの層間絶縁膜たる意
義を有する。Next, a third interlayer insulating film (upper interlayer insulating film) 13 'of SiN is formed on the Al wirings 12a and 12b by a sputtering method. Needless to say, since hydrogen is not released during this step, there is no problem of characteristic deterioration of the dielectric film 9. Since the film quality of the third interlayer insulating film 13 ′ lacks in density, it has little significance as a passivation film. As will be described later, an interlayer between the conductive and moisture-resistant hydrogen barrier film 14 and the Al wirings 12 a and 12 b is used. It has significance as an insulating film.
【００１７】次に、第３の層間絶縁膜１３’の上にスパ
ッタ法でＴｉＮ膜を耐湿性の水素バリア膜１４として形
成する。この成膜過程においては水素の発生がないた
め、誘電体膜９の特性劣化の問題は発生しない。本発明
者は水素バリア膜１４としてこのＴｉＮ膜が好適である
を見出した。一般に半導体技術においてＴｉＮ膜はシリ
コンとＡｌのバリアメタルとして知られているが、この
ＴｉＮ膜は緻密性に富み、導電性の膜であるため、耐湿
性で水素非透過性の保護膜であると共に、電磁シールド
機能をも果たす。この窒化チタン（ＴｉＮ；チタンナイ
トライド）は酸化して酸素侵入型のＴｉＯＮとなり易
い。酸素含有率の高いＴｉＯＮは水素非透過性がより高
くなり、水素バリア膜として優れている。したがって、
この水素バリア膜１４としてはＴｉＯＮ膜であっても良
い。ＴｉＯＮ膜の成膜法としては次のいずれかの方法を
採用する。Next, a TiN film is formed as a moisture-resistant hydrogen barrier film 14 on the third interlayer insulating film 13 'by a sputtering method. Since no hydrogen is generated during this film forming process, the problem of characteristic deterioration of the dielectric film 9 does not occur. The present inventor has found that this TiN film is suitable as the hydrogen barrier film 14. Generally, in semiconductor technology, a TiN film is known as a barrier metal of silicon and Al. However, since this TiN film is a dense and conductive film, it is a moisture-resistant and hydrogen-impermeable protective film. , Also performs an electromagnetic shielding function. This titanium nitride (TiN; titanium nitride) is likely to be oxidized to form oxygen-invasive TiON. TiON having a high oxygen content has higher hydrogen non-permeability and is excellent as a hydrogen barrier film. Therefore,
The hydrogen barrier film 14 may be a TiON film. One of the following methods is adopted as a method of forming the TiON film.
【００１８】 ＴｉＮ膜の酸素雰囲気でのプラズマ処
理法 ＴｉＮ膜の酸素雰囲気での熱処理法 Ｎ2，Ｏ2雰囲気中でのＴｉターゲットによるスパッ
タ法 ＴｉＯＮのスパッタ法 なお、水素バリア膜が酸素含有率の高いＴｉＯＮである
場合には、導電性でないから層間絶縁膜１３’の形成は
不要である。Plasma treatment method of TiN film in oxygen atmosphere Heat treatment method of TiN film in oxygen atmosphere Sputtering method using Ti target in N 2 , O 2 atmosphere Sputtering method of TiON In the case of high TiON, there is no need to form the interlayer insulating film 13 'because it is not conductive.
【００１９】ところで、水素バリア膜１４はＴｉＮ膜又
ＴｉＯＮ膜であるので、一般に導電性を有しているが、
酸素侵入型のＴｉＯＮは酸素含有率が小なるときは導電
性を帯び、酸素含有率が大なるときは絶縁性となる。Since the hydrogen barrier film 14 is a TiN film or a TiON film, it generally has conductivity.
The oxygen penetration type TiON becomes conductive when the oxygen content is small, and becomes insulating when the oxygen content is large.
【００２０】［第２実施例］図２は本発明の第２実施例
に係る半導体メモリの構造を示す断面図である。なお、
図２において図１に示す部分と同一部分には同一参照符
号を付し、その説明は省略する。[Second Embodiment] FIG. 2 is a sectional view showing a structure of a semiconductor memory according to a second embodiment of the present invention. In addition,
In FIG. 2, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
【００２１】この実施例においては、水素バリア膜１４
の上にプラズマＣＶＤ法によるＳｉＮ膜や常圧又は減圧
ＣＶＤ法によるＳｉＯ2膜の腐食防止膜１５を形成す
る。この膜は緻密性に富み湿気の侵透を阻止するので、
水素バリア膜１４の腐食を防止することができる。プラ
ズマＣＶＤ法によるＳｉＮ膜や常圧又は減圧ＣＶＤ法に
よるＳｉＯ2膜の成膜法は、水素の発生又は水素雰囲気
中でのプロセスであるが、その水素侵入は既に形成され
た水素バリア膜１４によって阻止されるため、誘電体膜
９への影響を惹起させることはない。In this embodiment, the hydrogen barrier film 14
An anti-corrosion film 15 of a SiN film by plasma CVD or a SiO 2 film by normal pressure or reduced pressure CVD is formed thereon. Since this film is dense and prevents moisture penetration,
Corrosion of the hydrogen barrier film 14 can be prevented. The method of forming a SiN film by a plasma CVD method or a SiO 2 film by a normal pressure or reduced pressure CVD method is a process of generating hydrogen or a process in a hydrogen atmosphere. Since this is prevented, the influence on the dielectric film 9 is not caused.
【００２２】［第３実施例］図３は本発明の第３実施例
に係る半導体メモリの構造を示す断面図である。なお、
図３において図２に示す部分と同一部分には同一参照符
号を付し、その説明は省略する。[Third Embodiment] FIG. 3 is a sectional view showing a structure of a semiconductor memory according to a third embodiment of the present invention. In addition,
3, the same parts as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.
【００２３】この第３実施例の第２実施例に対して異な
る点は、ＴｉＮ膜又はＴｉＯＮ膜の水素バリア膜１４’
の形成領域をストレージ・キャパシタ構造を覆う範囲に
限定したところにある。水素バリア膜１４’の意義は、
耐湿性のあることは勿論のこと、その成膜中では水素不
放出性で且つ水素非透過性であれば良い。水素バリア膜
牒１４’の上に形成するプラズマＣＶＤ法によるＳｉＮ
膜や常圧又は減圧ＣＶＤ法によるＳｉＯ2膜の腐食防止
膜１５は、その成膜中に水素の発生を招くが、積層構造
の下層へ水素が侵入しても誘電体膜９へ到達しないよう
水素バリア膜１４’が水素侵入を遮蔽すれば充分であ
る。水素バリア１４’はストレージ・キャパシタ構造を
覆う範囲で水素の侵入を遮蔽する。横方向からの水素の
侵入到達距離が長いことから殆ど問題とはならない。The difference between the third embodiment and the second embodiment is that the hydrogen barrier film 14 ′ is a TiN film or a TiON film.
Is limited to a range that covers the storage capacitor structure. The significance of the hydrogen barrier film 14 ′
Needless to say, it is sufficient if the film is non-hydrogen permeable and non-permeable to hydrogen during the film formation as well as being moisture-resistant. SiN by plasma CVD formed on hydrogen barrier film 14 '
The corrosion prevention film 15 of the film or the SiO 2 film formed by the normal pressure or low pressure CVD method causes generation of hydrogen during the film formation, but does not reach the dielectric film 9 even if hydrogen enters the lower layer of the laminated structure. It is sufficient that the hydrogen barrier film 14 'shields hydrogen from entering. The hydrogen barrier 14 'shields the entry of hydrogen to the extent that it covers the storage capacitor structure. There is almost no problem because the penetration distance of hydrogen from the lateral direction is long.
【００２４】ところで、第１実施例や第２実施例におい
て、全面的に形成される水素バリア膜１４がＴｉＮ膜や
酸素含有率の小なるＴｉＯＮ膜の場合は導電性を有する
ので、Ａｌ配線１２ｂと同一層に形成されるパッド部と
これに接続すべきボンディング・ワイヤとの接続方法に
ついて検討する必要がある。一般的な接続方法を図４に
示す。先ず、図４（Ａ）に示すように、第２の層間絶縁
膜の上にＡｌパッド部１２ｃをＡｌ配線１２ｂと同一層
で形成した後、第２の層間絶縁膜１３’，導電性の水素
バリア膜１４及び腐食防止膜１５を順次形成し、次に、
図４（Ｂ）に示す如く、Ａｌパッド部１２ｃの真上の３
層をエッチング処理で除去してコンタクト穴１６を形成
してから、図４（Ｃ）に示すように、ボンディング・ワ
イヤ１７をＡｌパッド部１２ｃの露出領域に対し圧着す
る。かかる接続法によれば、ボンディング・ワイヤ１７
の圧着によってＡｌパッド部１２ｃのみならずコンタク
ト穴の側壁に望む導電性の水素バリア膜１４にもボンデ
ィング・ワイヤ１７が導通してしまう。これは他のボン
ディング・ワイヤとのショートを引き起こす。In the first and second embodiments, when the hydrogen barrier film 14 formed over the entire surface is a TiN film or a TiON film having a small oxygen content, the hydrogen barrier film 14 has conductivity. It is necessary to consider a method of connecting a pad portion formed on the same layer with a bonding wire to be connected to the pad portion. FIG. 4 shows a general connection method. First, as shown in FIG. 4A, after an Al pad portion 12c is formed in the same layer as the Al wiring 12b on the second interlayer insulating film, the second interlayer insulating film 13 'and conductive hydrogen are formed. A barrier film 14 and a corrosion prevention film 15 are sequentially formed, and then,
As shown in FIG. 4 (B), 3 directly above the Al pad portion 12c
After the layer is removed by an etching process to form a contact hole 16, a bonding wire 17 is pressed against the exposed region of the Al pad portion 12c as shown in FIG. According to such a connection method, the bonding wire 17
The bonding wire 17 conducts not only to the Al pad portion 12c but also to the conductive hydrogen barrier film 14 desired on the side wall of the contact hole. This causes a short circuit with other bonding wires.
【００２５】図５は、上記問題点を解決するため、パッ
ド部とボンディング・ワイヤとの改善接続方法を示す工
程図である。FIG. 5 is a process chart showing an improved connection method between a pad portion and a bonding wire to solve the above problem.
【００２６】先ず、図５（Ａ）に示すように、第２の層
間絶縁膜の上にＡｌパッド部１２ｃをＡｌ配線１２ｂと
同一層で形成し、この上に第２の層間絶縁膜１３’及び
導電性の水素バリア膜１４を順次形成する。First, as shown in FIG. 5A, an Al pad portion 12c is formed in the same layer as the Al wiring 12b on the second interlayer insulating film, and a second interlayer insulating film 13 'is formed thereon. And a conductive hydrogen barrier film 14 are sequentially formed.
【００２７】次に、図５（Ｂ）に示す如く、腐食防止膜
１５の形成の前に、Ａｌパッド部１２ｃの真上の３層を
エッチング処理で除去して窓明け部１６ａを形成して一
旦Ａｌパッド部１２ｃを露出させる。その露出領域をＸ
とする。Next, as shown in FIG. 5B, before the formation of the corrosion prevention film 15, three layers immediately above the Al pad portion 12c are removed by etching to form a window opening portion 16a. The Al pad portion 12c is once exposed. The exposed area is X
And
【００２８】次に、図５（Ｃ）に示すように、上記露出
領域Ｘをも含めて水素バリア膜１４の上に腐食防止膜１
５’を形成する。ここではコンタクト穴１６ａ内も腐食
防止膜１５’で覆われる。Next, as shown in FIG. 5C, the corrosion prevention film 1 is formed on the hydrogen barrier film 14 including the exposed region X.
5 'is formed. Here, the inside of the contact hole 16a is also covered with the corrosion prevention film 15 '.
【００２９】次に、図５（Ｄ）に示すように、Ａｌパッ
ド部１２ｃの真上の１層の腐食防止膜１５をエッチング
処理で除去してコンタクト穴１６ｂを形成する。Ａｌパ
ッド部１２ｃ表面に形成すべき露出領域の広さ範囲Ｙは
上記露出領域の広さ範囲Ｘに比して狭く設定する。Next, as shown in FIG. 5D, a single layer of the corrosion prevention film 15 immediately above the Al pad portion 12c is removed by etching to form a contact hole 16b. The width range Y of the exposed region to be formed on the surface of the Al pad portion 12c is set narrower than the width range X of the exposed region.
【００３０】次に、図５（Ｅ）に示すように、ボンィン
グ・ワイヤ１７をＡｌパッド部１２ｃの露出領域Ｙに対
し圧着する。Next, as shown in FIG. 5E, the bonding wire 17 is pressed against the exposed region Y of the Al pad portion 12c.
【００３１】このような接続方法を採用すると、ボンデ
ィング・ワイヤ１７がＡｌパッド部１２ｃにのみ導通
し、導電性の水素バリア膜１４には導通しない。水素バ
リア膜１４とボンディング・ワイヤ１７とは腐食防止膜
１５で絶縁されているからである。なお、Ａｌパッド部
１２ｃとボンディング・ワイヤ１７との接続に限らず、
Ａｌパッド部１２ｃとバンプとの接続、Ａｌ配線と上層
のＡｌの接続（スルーホール接続）にも上記接続方法を
適用できる。When such a connection method is adopted, the bonding wire 17 conducts only to the Al pad portion 12c and does not conduct to the conductive hydrogen barrier film 14. This is because the hydrogen barrier film 14 and the bonding wires 17 are insulated by the corrosion prevention film 15. Not only the connection between the Al pad portion 12c and the bonding wire 17 but also
The above connection method can also be applied to the connection between the Al pad portion 12c and the bump and the connection between the Al wiring and the upper layer Al (through hole connection).
【００３２】水素侵入による特性劣化の問題は、強誘電
体膜に限らず、多結晶シリコン・ゲートを有するＣＭＯ
Ｓ集積回路等においても問題となる。多結晶シリコン・
ゲートが水素に触れると、しきい値の変動を招き、歩留
まりの悪化要因となる。それ故、耐湿性の水素バリア膜
を強誘電体膜の保譲だけでなく、多結晶シリコン・ゲー
トの保覆膜をしてその上部に形成しておくことは、多結
晶シリコン・ゲートの特性の安定性に寄与する。The problem of characteristic deterioration due to hydrogen intrusion is not limited to the ferroelectric film, but the problem of the CMO having a polycrystalline silicon gate
A problem also occurs in S integrated circuits and the like. Polycrystalline silicon
When the gate comes into contact with hydrogen, the threshold value fluctuates, causing a reduction in yield. Therefore, not only the transfer of the ferroelectric film but also the formation of a protective film for the polycrystalline silicon gate and the formation of a moisture-resistant hydrogen barrier film on the polycrystalline silicon gate are necessary. Contributes to the stability of
【００３３】[0033]
【発明の効果】以上説明したように、本発明は、強誘電
体又は多結晶シリコン・ゲートを要素とする半導体装置
において、強誘電体又は多結晶シリコン・ゲートの上部
に水素不放出性の成膜法によりなるＴｉＮ膜やＴｉＯＮ
膜等の耐湿性の水素バリア膜を形成した点に特徴を有す
るものである。従って以下の効果を奏する。As described above, according to the present invention, in a semiconductor device having a ferroelectric or polycrystalline silicon gate as an element, a hydrogen non-releasing component is formed above the ferroelectric or polycrystalline silicon gate. TiN film or TiON by film method
It is characterized in that a moisture-resistant hydrogen barrier film such as a film is formed. Therefore, the following effects are obtained.
【００３４】 水素バリア膜の形成自体が水素を発生
しないので、強誘電体又は多結晶シリコン・ゲートヘの
水素侵入の影響がない。また水素バリア膜の形成後に水
素放出性の成膜法が使用された場合や水素雰囲気に半導
体装置自身が置かれた場合でも水素バリア膜がその水素
の侵入を阻止する。従って、強誘電体の残留分極や比誘
電率の低下、多結晶シリコン・ゲートのしきい値の変動
等のような水素侵入による特性劣化の問題を回避でき
る。Since the formation of the hydrogen barrier film itself does not generate hydrogen, there is no effect of hydrogen penetration into the ferroelectric or polycrystalline silicon gate. The hydrogen barrier film prevents the intrusion of hydrogen even when a hydrogen releasing film formation method is used after the formation of the hydrogen barrier film or when the semiconductor device itself is placed in a hydrogen atmosphere. Therefore, it is possible to avoid a problem of characteristic deterioration due to hydrogen intrusion such as a decrease in remanent polarization or relative permittivity of a ferroelectric substance, a change in a threshold value of a polycrystalline silicon gate, and the like.
【００３５】 腐食性の水素バリアの場合、その上に
腐食防止膜を形成した構造を採用すると、水素バリアの
腐食を防止できることは勿論、その腐食防止膜の形成が
水素放出性の成膜法による場合であっても、強誘電体又
は多結晶シリコン・ゲートヘの水素の侵入の問題は生じ
させない。In the case of a corrosive hydrogen barrier, if a structure in which a corrosion prevention film is formed thereon is adopted, not only can the corrosion of the hydrogen barrier be prevented, but also the formation of the corrosion prevention film can be achieved by a hydrogen releasing film forming method. Even so, the problem of hydrogen penetration into the ferroelectric or polysilicon gate does not arise.
【００３６】 絶縁性のあるＴｉＯＮ膜を耐湿性の水
素バリア膜として形成した場合には、水素阻止能が高い
構造を得ることができる。また層間絶縁膜も削減するこ
とができる。When the insulating TiON film is formed as a moisture-resistant hydrogen barrier film, a structure having a high hydrogen blocking ability can be obtained. Further, the number of interlayer insulating films can be reduced.
【図１】 本発明の第１実施例に係る半導体メモリの構
造を示す断面図である。FIG. 1 is a sectional view showing a structure of a semiconductor memory according to a first embodiment of the present invention.
【図２】 本発明の第２実施例に係る半導体メモリの構
造を示す断面図である。FIG. 2 is a sectional view showing a structure of a semiconductor memory according to a second embodiment of the present invention.
【図３】 本発明の第３実施例に係る半導体メモリの構
造を示す断面図である。FIG. 3 is a sectional view showing a structure of a semiconductor memory according to a third embodiment of the present invention.
【図４】 （Ａ）乃至（Ｃ）は同半導体メモリにおける
パッド部とボンディング・ワイヤとの一般的な接続方法
を示す工程図である。FIGS. 4A to 4C are process diagrams showing a general method of connecting a pad portion and a bonding wire in the semiconductor memory.
【図５】 （Ａ）乃至（Ｅ）は同半導体メモリにおける
パッド部とボンディング・ワイヤとの改善された接続方
法を示す工程図である。FIGS. 5A to 5E are process diagrams showing an improved connection method between a pad portion and a bonding wire in the semiconductor memory.
【図６】 従来における半導体メモリの構造の一例を示
す断面図である。FIG. 6 is a cross-sectional view showing an example of the structure of a conventional semiconductor memory.
１・・・ｐ型半導体基板 ２・・・ゲート絶縁膜 ３・・・多結晶シリコン・ゲート ４、５・・・高濃度ｎ型のソース・ドレイン領域 ６・・・ＬＯＣＯＳ（局所酸化膜） ７・・・第１の層間絶縁膜 ８・・・白金の下部平板電極 ９・・・強誘電体たるＰＺＴ（Ｐｂ（Ｔｉx Ｚｒy）
Ｏ3）の誘電体膜 １０・・・白金の上部平板電極 １１・・・第２の層間絶縁膜 １２ａ，１２ｂ・・・Ａｌ配線 １２ｃ・・・Ａｌパッド部 １３’・・・第３の層間絶縁膜 １４、１４’・・・水素バリア膜（スパッタ法等による
ＴｉＮ膜やＴｉＯＮ膜） １５・・・腐食防止膜 １６ａ・・・窓明け部 １６ｂ・・・コンタクト穴 １７・・・ボンディング・ワイヤ Ｔ・・・転送トランジスタ Ｃ・・・ストレージ・キャパシタ Ｘ，Ｙ・・・露出領域の広さ範囲DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate 2 ... gate insulating film 3 ... polycrystalline silicon gate 4, 5 ... high-concentration n-type source / drain region 6 ... LOCOS (local oxide film) 7 ... first interlayer insulating film 8 ... platinum lower plate electrode 9 ... ferroelectric serving PZT (Pb (Ti x Zr y )
O 3 ) dielectric film 10: upper flat plate electrode of platinum 11: second interlayer insulating film 12a, 12b: Al wiring 12c: Al pad portion 13 ': third interlayer Insulating films 14, 14 ': hydrogen barrier film (TiN film or TiON film by sputtering or the like) 15: corrosion prevention film 16a: window opening 16b: contact hole 17: bonding wire T: transfer transistor C: storage capacitor X, Y: width of exposed area
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１１年７月１２日（１９９９．７．１
２）[Submission date] July 12, 1999 (1999.7.1)
2)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】発明の名称[Correction target item name] Name of invention
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【発明の名称】 半導体装置[Title of the Invention] Semiconductor device
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 27/092 Ｈ０１Ｌ 29/78 ３０１Ｎ 27/108 21/8242 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 29/78 301N 27/108 21/8242 29/78
Claims (9)
を要素とする半導体装置であって、該要素の上部におい
て少なくとも該要素を覆う範囲に、水素不放出性の成膜
法によりなる耐湿性の水素バリア膜を具有することを特
徴とする半導体装置。1. A semiconductor device comprising a ferroelectric film or a polycrystalline silicon gate as an element, wherein at least a part of the element covering at least the element is covered with moisture by a non-hydrogen deposition method. And a hydrogen barrier film.
リア膜の上部にはこれを覆う腐食防止膜を具有すること
を特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein an upper part of said hydrogen barrier film is provided with a corrosion prevention film covering said hydrogen barrier film.
前記バリア膜がＴｉＮ膜であることを特徴とする半導体
装置。3. The method according to claim 1, wherein
A semiconductor device, wherein the barrier film is a TiN film.
前記水素バリア膜がＴｉＯＮ膜であることを特徴とする
半導体装置。4. The method according to claim 1, wherein
A semiconductor device, wherein the hydrogen barrier film is a TiON film.
一項記載において、前記腐食防止膜はＳｉＮ膜であるこ
とを特徴とする半導体装置。5. The semiconductor device according to claim 2, wherein the corrosion prevention film is a SiN film.
記載の半導体装置を用いた半導体メモリ。6. A semiconductor memory using the semiconductor device according to claim 1. Description:
項記載の半導体装置を用いたＣＭＯＳ半導体集積回路。7. A CMOS semiconductor integrated circuit using the semiconductor device according to claim 1. Description:
を要素とする半導体装置の製造方法において、該強誘電
体膜又は多結晶シリコン・ゲートを形成した後に水素不
放出性の成膜法により層問絶縁膜を形成する工程と、該
要素の上部で少なくとも該要素を覆う範囲に、水素不放
出性の成膜法により耐湿性の水素バリア膜を形成する工
程と、を有することを特徴とする半導体装置の製造方
法。8. A method of manufacturing a semiconductor device comprising a ferroelectric film or a polycrystalline silicon gate as an element, wherein the ferroelectric film or the polycrystalline silicon gate is formed and then a hydrogen non-releasing film forming method is performed. A step of forming an insulating film between layers, and a step of forming a moisture-resistant hydrogen barrier film by a non-hydrogen-forming film formation method in a range covering at least the element above the element. Semiconductor device manufacturing method.
て、前記水素バリア膜の形成工程の後、該水素バリア膜
の上に腐食防止膜を覆う工程、を有することを特徴とす
る半導体装置の製造方法。9. The semiconductor device according to claim 8, further comprising, after the step of forming the hydrogen barrier film, a step of covering a corrosion prevention film on the hydrogen barrier film. Manufacturing method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18167599A JP3332013B2 (en) | 1999-06-28 | 1999-06-28 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18167599A JP3332013B2 (en) | 1999-06-28 | 1999-06-28 | Semiconductor device and manufacturing method thereof |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02220905A Division JP3131982B2 (en) | 1990-08-21 | 1990-08-21 | Semiconductor device, semiconductor memory, and method of manufacturing semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2000091513A true JP2000091513A (en) | 2000-03-31 |
| JP3332013B2 JP3332013B2 (en) | 2002-10-07 |
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ID=16104917
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8659124B2 (en) | 2008-12-29 | 2014-02-25 | Nxp B.V. | Physical structure for use in a physical unclonable function |
-
1999
- 1999-06-28 JP JP18167599A patent/JP3332013B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8659124B2 (en) | 2008-12-29 | 2014-02-25 | Nxp B.V. | Physical structure for use in a physical unclonable function |
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| Publication number | Publication date |
|---|---|
| JP3332013B2 (en) | 2002-10-07 |
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