JP2000090685A - Current type sense amplifier circuit and sensing method thereof and current type sense amplifier circuit having low current function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a consumption current largely without changing a data read time written in a ROM and the layout area of a circuit by flowing a current through a sense amplifier circuit only at the time of the fall time and rise time of an output from a sense amplifier at a Low or High level corresponding to a pre-charge signal. SOLUTION: When a pre-charge signal rises to a High level, a Pch transistor 1 is turned off, a current begins to flow through a Pch transistor 2, the current also begins to flow through a Pch transistor 3 in current-mirror relationship with the Pch transistor 2, and a node SOUT is elevated up to the High level. When the node SOUT exceeds threshold voltage at 2 NAND: 8, an Nch transistor 5 is turned off and the DC current is cut, and the node SOUT is held at the High level and stabilized. Accordingly, the current is flowed through the Pch transistor 3 only at the time of the fall and rise of an output from a sense amplifier at a Low level or the High level corresponding to the pre-charge signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current-type sense amplifier circuit used for reading data written in a ROM at a high speed, a sensing method therefor, and a current-type sense amplifier circuit having a low-current function.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open No.
Japanese Patent Application Laid-Open No. 070591, Japanese Patent Application Laid-Open No. 04-214292 and the like are known. FIG.
FIG. 6 is a circuit diagram showing a sense amplifier circuit disclosed in Japanese Patent Application Laid-Open No. 0-705591, and FIG. That is, when an address for selecting the ROM cell 28 is input, a current flows to the Pch transistor 22 via the Nch transistor 24. A current also flows through the Pch transistor 23 that has a current mirror relationship with the Pch transistor 22, and the level of the node SOUT changes from the Low level to the High level. Node S
When the level of OUT exceeds the threshold voltage of the inverter 27, the sense amplifier output SOUTZ changes from the high level to the low level.
Change to a level. In the figure, reference numeral 25 denotes an inverter,
26 indicates Nch transistors, respectively.

FIG. 7 is a circuit diagram showing a sense amplifier circuit disclosed in JP-A-04-214292. That is, when the CNT2 signal of the control circuit 40 changes to High, the Pch transistor 31 turns off, and a current flows through the Pch transistor 32. P
Pch in a current mirror relationship with the channel transistor 32
A current also flows through the transistor 33, and the level of the node SOUT changes from the Low level to the High level. When the level of the node SOUT exceeds the threshold voltage of the inverter 37, the output OUT1 of the sense amplifier changes from the high level to the low level, and the signal is output to the latch circuit 39 and the control circuit 40.
Is input to Then, the CLK signal, the STBY signal, the φ0 signal, the φ1 signal, and the sense amplifier outputs OUT1 to OUTn are operated by the control circuit 40 and output as the CNT1 signal, the CNT2 signal, and the CK signal. Of those output signals, CNT1 is 2NOR3
6, CNT2 is input to the gate of the Pch transistor 31, and CK is input to the latch circuit 39. The signal order relationship is such that CNT1 and CN
2 changes. That is, the current consumption is reduced by performing the operation of stopping the current of the sense amplifier circuit after the sense amplifier output OUT1 is latched. Reference numerals 34 and 35 in the figure are Nch transistors, and 38 is a ROM.
Each cell is shown.

[0004]

However, in the above-mentioned prior art of the prior art, as shown in FIG.
Pc until the address changes even if SOUT rises to High
DC current continues to flow between the h transistor 23 and the Nch transistor 26. Therefore, there is a problem that current consumption of the entire sense amplifier circuit is increased.

On the other hand, in the latter prior art, since the operation of stopping the current of the sense amplifier circuit is performed after the sense amplifier output OUT1 is latched, the current consumption of the entire sense amplifier circuit is reduced. However, since the control circuit 40 is required to reduce power consumption, the sense amplifier circuit has a complicated configuration, and there is a problem that the layout area is increased. The control circuit 4
Since the circuit in 0 is configured using a delay circuit, there is a drawback that the limit point is reached quickly when trying to speed up the circuit configuration. In other words, it is necessary to reduce the clock frequency to cope with this, which hinders an increase in the speed of the circuit configuration.

Japanese Patent Application Laid-Open No. 63-184990 discloses a method of reducing the current at the time of reading data from a memory. For example, the output data of a sense amplifier changes to "1". The current can be reduced only at the time, but the total current cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in view of the above circumstances. Therefore, it is possible to significantly reduce the current consumption without changing the data reading time written in the ROM and the circuit layout area. An object of the present invention is to provide a current-type sense amplifier circuit having a low-current function and a low-current function.

[0008]

According to a first aspect of the present invention, there is provided a current type sense amplifier circuit, comprising: a first to third Pch transistors and a NAND gate which output a sense amplifier according to a precharge (PRCHB) signal; Fifth and sixth Nch transistors that supply current to the third Pch transistor only when the charge (PRCHB) signal rises or falls, and ROM when the precharge (PRCHB) signal is low level
A fourth Nch transistor and a first inverter for holding a bit line potential of a cell at a high level are provided. Further, the gate of the first Pch transistor is connected to the precharge (PRCHB) signal, the source is connected to the power supply VDD, and the source and drain of the first Pch transistor and the drain and gate of the second Pch transistor are connected. Are connected, the gate of the third Pch transistor is connected to the drain of the fourth Nch transistor, the source of the second Pch transistor and the source of the third Pch transistor are connected to the power supply VDD, and the fourth The gate of the Nch transistor is connected to the output of the first inverter,
One of the M cells is connected to the bit line output, the input of the first inverter, and the source of the fourth Nch transistor.
The other of the OM cell is connected to GND, the drain of the third Pch transistor is connected to the drain of the fifth Nch transistor and one input of the NAND gate, and the source of the fifth Nch transistor is connected to the sixth Nch transistor. The drain of the transistor is connected, the other input of the NAND gate is connected to the precharge (PRCHB) signal, the output of the NAND gate is connected to the sense amplifier output and the gate of the fifth Nch transistor, and the sixth Nch transistor Can be connected to a reference voltage and its source can be connected to GND. Also, a tenth Nch transistor can be connected in parallel with the fifth and sixth Nch transistors, and the gate can be connected to a reference voltage. Further, the fifth Nch transistor can be replaced with an eleventh Pch transistor, and the second inverter can be interposed between the output of the sense amplifier and the gate of the eleventh Pch transistor. The sensing method of the current-type sense amplifier circuit according to claim 5, wherein the low-level signal or the low-level signal in response to the precharge (PRCHB) signal.
A first step of outputting a high-level sense amplifier output, a second step of flowing a current to the sense amplifier circuit only when the sense amplifier output falls and rises, and a ROM when the precharge (PRCHB) signal is at a low level. And a third step of maintaining the bit line potential of the cell at a high level. In the first to third steps, when the precharge (PRCHB) signal is in the Low period, the bit line of the ROM cell is set to High.
And turning on the fifth Nch transistor by the high level output of the NAND gate, and turning off the first Pch transistor when the precharge (PRCHB) signal rises to the high level. A process of flowing a current to a third Pch transistor having a current mirror relationship with the Pch transistor; and turning off the fifth Nch transistor when an output node of the third Pch transistor becomes High level and exceeds a threshold voltage of the NAND gate. Cutting off the current flowing through the third Pch transistor, and turning off the third Pch transistor when the precharge (PRCHB) signal falls to a low level;
At the same time, the fifth Nch transistor is turned on, the output node is lowered to Low level, and the bit line of the ROM cell is set to High.
And a step of maintaining the level. 8. A sense amplifier circuit having a low current function according to claim 7, wherein the sense amplifier circuit outputs a low or high level sense amplifier in response to a precharge (PRCHB) signal, and a sense amplifier output of the sense amplifier circuit. A current limiting circuit that supplies current to the sense amplifier circuit only at the time of falling and rising, and a potential holding circuit that holds the bit line potential of the ROM cell at the high level when the precharge (PRCHB) signal is at the low level. It is characterized by the following.
In the current-type sense amplifier circuit, the sensing method thereof, and the current-type sense amplifier circuit having a low-current function of the present invention, a low or high level corresponding to a precharge (PRCHB) signal is provided.
A current is caused to flow to the sense amplifier circuit only when the output of the level sense amplifier falls and rises.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of a current-type sense amplifier circuit according to the present invention. Pch
The gate of the transistor 1 is connected to the precharge (PRCHB) signal, and the source of the Pch transistor 1 is connected to the power supply VDD. The source and drain of the Pch transistor 1 and the drain and gate of the Pch transistor 2 are connected. The drain of the Pch transistor 2 and the drain of the Pch transistor 3 are connected. The gate of the Pch transistor 3 and the drain of the Nch transistor 4 are connected. The gate of the Nch transistor 4 is connected to the output of the inverter 7, and one of the ROM cells 9 is connected to the bit line output, the input of the inverter 7, and the source of the Nch transistor 4. The other of the ROM cells is connected to GND.
The drain of the Pch transistor 3 is connected to the drain of the Nch transistor 5 and one input of the 2NAND 8. The source of the Nch transistor 5 and the drain of the Nch transistor 6 are connected. The other input of 2 NAND8 is PR
The output of the 2NAND 8 is connected to the sense amplifier output SOUTZ and the gate of the Nch transistor 5. The gate of the Nch transistor 6 is connected to the reference voltage Vref, and the source of the Nch transistor 6 is connected to GND.

Here, the sense amplifier circuit includes Pch transistor 1, Pch transistor 2, Pch transistors 3, 2
Consists of NAND8. The current limiting circuit includes an Nch transistor 5 and an Nch transistor 6. The potential holding circuit is Nch
It comprises a transistor 4 and an inverter 7.

Next, the operation will be described with reference to FIG. While the precharge (PRCHB) signal is in the Low period, the bi-state of the ROM cell 9 is transmitted via the Pch transistor 1 and the Nch transistor 4.
The t line is charged to the high level. The gate-source voltage of the Nch transistor 4 is settled at a voltage that keeps the bit line at a high level. In other words, the bit line of the ROM cell 9 is settled by the logic threshold voltage of the inverter 7, and the output of the inverter 7 is settled to about the logic threshold voltage + Vt of the Nch transistor 4 + 0.3V. That is, the gate potential of the Nch transistor 4 is stabilized at a voltage higher than the source potential, and when the selected ROM cell 9 is turned on, the power supply VDD and GND are connected via the Pch transistor 1, the Nch transistor 4 and the ROM cell 9. DC current flows through the At this time, since the gate potential of the Pch transistor 3 is at the VDD level, the Pch transistor 3 is off. Further, since the PRCHB signal is low, the output of the 2 NAND 8 becomes high, and the Nch transistor 5 turns on. The gate of the Nch transistor 6 has the reference voltage V.
Because it is supplied from ref (VT + 0.2V), it is turned on, and the node SOUT becomes low level.

Next, when the PRCHB signal rises to High, P
The channel transistor 1 is turned off, and a current starts to flow through the Pch transistor 2. A current starts to flow also in the Pch transistor 3 having a current mirror relationship with the Pch transistor 2, and the node SOUT is raised to the high level. When the node SOUT exceeds the threshold voltage of 2NAND8, the output SOUTZ of the sense amplifier falls to the low level, and the Nch transistor 5 is turned off to cut the DC current. Then, the node SOUT is stabilized while holding High. Where Pc
h The current capability of the transistor 3 at the time of saturation is made larger than the current capability of the Nch transistor 6 at the time of saturation (2: 1
degree).

Next, when the PRCHB signal falls to Low, the sense amplifier output SOUTZ becomes Hi at almost the same time as the change of the PRCHB signal.
gh level and the Pch transistor 3 is turned off. At the same time, the Nch transistor 5 turns on and the node SOUT
At the same time, the precharge of the bit line of the ROM cell 9 is started.

As described above, in the first embodiment,
Since the current is allowed to flow through the Pch transistor 3 only at the time of falling and rising of the low or high level sense amplifier output corresponding to the precharge (PRCHB) signal, the ROM
A large reduction in current consumption can be achieved without changing the data reading time written in the cell 9 and the layout area of the circuit.

That is, for example, in a ROM operating at a high speed (f = several tens of MHz), the current consumption of a general sense amplifier circuit reaches 50% of the entire ROM. On the other hand, when the current-type sense amplifier circuit according to the first embodiment is used, the current can be reduced by about 40% only with the sense amplifier circuit as compared with the prior art shown in FIG. RO
As a whole, about 20% of the current was reduced. However, in the current type sense amplifier circuit according to the first embodiment, the mirror ratio between the Pch transistor 2 and the Pch transistor 3 is set to 1: 4, and the current when the Pch transistor 3 is saturated and the saturation of the Nch transistor 6 In this case, the current is set to 2: 1.

Compared with the circuit configuration of the prior art shown in FIG. 5, in this embodiment, the precharge (PRCHB) signal, the Pch transistor 1, the Nch transistor 5,
Since it is a configuration that adds one NAND8 each, the ROM
This can be realized with a layout that can be ignored with respect to the entire layout area (increase of 1% or less). Further, a precharge (PRCHB) signal can be easily realized by using a data latch signal output from a sense amplifier.

(Second Embodiment) FIG. 3 is a circuit diagram showing a current-type sense amplifier circuit according to a second embodiment of the present invention. In the drawings described below, the same parts as those in FIG.
In the second embodiment shown in FIG. 3, an Nch transistor 10 is connected in parallel to the Nch transistors 5 and 6 in FIG. The gate of the Nch transistor 10 is connected to the reference voltage Vref.

In such a configuration, the precharge (PRCH
B) When the signal rises, a current flows through the Pch transistor 2. A current also flows through the Pch transistor 3, which has a current mirror relationship with the Pch transistor 2, and the node SOUT becomes low.
Change from level to high level. When the sense amplifier output SOUTZ changes from the high level to the low level, Nc
h Transistor 5 turns off, cutting off DC current. At this time, since the Nch transistor 10 is on, a DC current flows through the Pch transistor 3. Here, it is possible to sufficiently reduce the DC current by increasing the mirror ratio of the Nch transistor 6 and the Nch transistor 10 (for example, 5: 1).

(Third Embodiment) FIG. 4 is a circuit diagram showing a current-type sense amplifier circuit according to a third embodiment of the present invention. In the third embodiment shown in FIG.
Is replaced by a Pch transistor 11, and an inverter 12 is added between the sense amplifier output SOUTZ and the gate of the Pch transistor 11. In such a circuit configuration, the same operation as the circuit in FIG. 1 is realized by replacing the Nch transistor 5 in FIG. 1 with a Pch transistor 11 and connecting the inversion of the sense amplifier output SOUTZ to the gate of the Pch transistor 11. .

[0020]

As described above, according to the current-type sense amplifier circuit and the sensing method thereof according to the present invention and the current-type sense amplifier circuit having a low-current function, the pre-charge ( PRCHB) R
Since the DC current is cut after the OM data is read, the current consumption can be significantly reduced without changing the data reading time written in the ROM and the layout area of the circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a current-type sense amplifier circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the current-type sense amplifier circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the current-type sense amplifier circuit of the present invention.

FIG. 4 is a circuit diagram illustrating a current-type sense amplifier circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional sense amplifier circuit.

FIG. 6 is a time chart for explaining the operation of the sense amplifier circuit of FIG. 5;

FIG. 7 is a circuit diagram showing another example of a conventional sense amplifier circuit.

[Explanation of symbols]

 1,2,3,11 Pch transistor 4,5,6,10 Nch transistor 7,12 Inverter 8 2NAND 9 ROM cell

[Procedure amendment]

[Submission Date] July 16, 1999 (1999.7.1)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

[0008]

According to the present invention, the gate of the first Pch transistor is connected to a precharge (PRCHB) signal.
The source is connected to the power supply VDD, the drain of the first Pch transistor, the drain and gate of the second Pch transistor, the gate of the third Pch transistor, the drain of the fourth Nch transistor, and the second The source of the Pch transistor and the source of the third Pch transistor are connected to the power supply VDD, and the gate of the fourth Nch transistor is connected to the
1 is connected to the output of the inverter and one of the ROM cells is bit
Line output, the input of the first inverter and the source of the fourth Nch transistor, and the other of the ROM cells
Connected to GND, the drain of the third Pch transistor is connected to the drain of the fifth Nch transistor and one input of the NAND gate, and the source of the fifth Nch transistor is connected to the drain of the sixth Nch transistor. Connected, N
The other input of the AND gate is connected to the precharge (PRCHB) signal, the output of the NAND gate is connected to the output of the sense amplifier and the gate of the fifth Nch transistor, and the gate of the sixth Nch transistor is connected to the reference voltage. Along with
The source is connected to GND.
In addition, the tenth and tenth Nch transistors are connected in parallel to the tenth
Nch transistors are connected, and their gates are connected to a reference voltage.
Further, the fifth Nch transistor is replaced with an eleventh Pch transistor, and the sense amplifier output and the first
The second inverter may be interposed between the gate of one Pch transistor. A sense method for a current-type sense amplifier circuit according to claim 4, wherein
When the charge (PRCHB) signal is in the low period, the bit line of the ROM cell is held at the high level, the fifth Nch transistor is turned on by the high level output of the NAND gate , and the precharge (PRCHB) signal is set to the high level. When it rises to the level, the first Pch transistor is turned off and the second Pch transistor is turned off.
The third Pch that has a current mirror relationship with the channel transistor
A step of flowing a current through the transistor, and when the output node of the third Pch transistor goes high and exceeds the threshold voltage of the NAND gate, turns off the fifth Nch transistor and cuts the current flowing through the third Pch transistor And when the precharge (PRCHB) signal falls to a low level, the third Pch transistor is turned off, and at the same time, the fifth Nch transistor is turned on.
Lowering the output node to a low level. The current-type sense amplifier circuit having a low current function according to claim 5 is configured such that a precharge (PRCH)
B) a sense amplifier circuit that outputs a low or high level sense amplifier in accordance with a signal; and a current limiting circuit that supplies a current to the sense amplifier circuit only when the sense amplifier output of the sense amplifier circuit falls and rises. It is characterized by the following. In the current-type sense amplifier circuit, the sensing method thereof, and the current-type sense amplifier circuit having a low-current function according to the present invention, the low-level or high-level sense amplifier output corresponding to a precharge (PRCHB) signal falls and rises. A current is caused to flow through the sense amplifier circuit only at the time.

Claims (7)

[Claims] A first Pch transistor and a NAND gate for outputting a sense amplifier according to a precharge (PRCHB) signal; and a third gate only when the precharge (PRCHB) signal rises or falls. Fifth and sixth Nch transistors that supply current to the Pch transistor, a fourth Nch transistor and a first Nch transistor that hold the bit line potential of the ROM cell at a high level when the precharge (PRCHB) signal is at a low level. A current type sense amplifier circuit comprising an inverter. 2. A gate of the first Pch transistor is connected to a precharge (PRCHB) signal, a source thereof is connected to a power supply VDD, and a drain of the first Pch transistor and the second Pch transistor
A drain and a gate of the transistor, a gate of the third Pch transistor and a drain of the fourth Nch transistor are connected, and a source of the second Pch transistor and a source of the third Pch transistor are connected to the power supply VDD. The gate of the fourth Nch transistor is connected to the output of the first inverter, and one of the ROM cells is connected to the bit line output, the input of the first inverter, and the source of the fourth Nch transistor. And the other of the ROM cells is connected to GND, and the drain of the fifth Nch transistor and one input of the NAND gate are connected to the drain of the third Pch transistor. The source of the Nch transistor is connected to the drain of the sixth Nch transistor, and the other input of the NAND gate is connected to the precharge (P RCH
B) the output of the NAND gate is connected to the sense amplifier output and the fifth
The current-type sense amplifier according to claim 1, wherein a gate of the sixth Nch transistor is connected to a reference voltage, and a source of the sixth Nch transistor is connected to GND. circuit. 3. The device according to claim 2, wherein a tenth Nch transistor is connected in parallel with said fifth and sixth Nch transistors, and a gate thereof is connected to said reference voltage. Current type sense amplifier circuit. 4. The semiconductor device according to claim 1, wherein the fifth Nch transistor is an eleventh P-channel transistor.
3. The current-type sense amplifier circuit according to claim 2, wherein a second inverter is interposed between the output of the sense amplifier and the gate of the eleventh Pch transistor while being replaced with a channel transistor. 5. A low level according to a precharge (PRCHB) signal.
Or a first step of outputting a high-level sense amplifier output, a second step of flowing a current to the sense amplifier circuit only when the sense amplifier output falls and rises, and the precharge (PRCHB) signal is low. Above when level
And a third step of holding the bit line potential of the ROM cell at a high level. 6. The first to third steps, wherein when the precharge (PRCHB) signal is in a Low period,
While holding the bit line of the ROM cell at the high level,
Turning on the fifth Nch transistor by a high level output of a NAND gate; and turning off the first Pch transistor when the precharge (PRCHB) signal rises to a high level; Flowing a current through the third Pch transistor, which is in a current mirror relationship with the fifth Nch transistor, when the output node of the third Pch transistor goes to a high level and exceeds the threshold voltage of the NAND gate. Turning off the third Pch transistor to cut off a current flowing through the third Pch transistor; and when the precharge (PRCHB) signal falls to a low level, turning off the third Pch transistor. 5 turns on the Nch transistor, lowers the output node to the low level, and sets the bit of the ROM cell.
6. The method according to claim 5, further comprising the step of holding the line at a high level. 7. Low according to a precharge (PRCHB) signal.
Or, a sense amplifier circuit that outputs a high-level sense amplifier, a current limiting circuit that causes a current to flow through the sense amplifier circuit only when the sense amplifier output of the sense amplifier circuit falls and rises, and the precharge (PRCHB) signal ROM when is low level
A current sense amplifier circuit having a low current function, comprising: a potential holding circuit for holding a bit line potential of a cell at a high level.