JP2000082820A - Manufacture of thin film semiconductor device - Google Patents

Manufacture of thin film semiconductor device

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Publication number
JP2000082820A
JP2000082820A JP11235804A JP23580499A JP2000082820A JP 2000082820 A JP2000082820 A JP 2000082820A JP 11235804 A JP11235804 A JP 11235804A JP 23580499 A JP23580499 A JP 23580499A JP 2000082820 A JP2000082820 A JP 2000082820A
Authority
JP
Japan
Prior art keywords
film
thin film
silicon
substrate
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11235804A
Other languages
Japanese (ja)
Other versions
JP3055555B2 (en
Inventor
Mitsutoshi Miyasaka
光敏 宮坂
Kenichi Takahara
研一 高原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11235804A priority Critical patent/JP3055555B2/en
Publication of JP2000082820A publication Critical patent/JP2000082820A/en
Application granted granted Critical
Publication of JP3055555B2 publication Critical patent/JP3055555B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To form an excellent semiconductor device by a method wherein a silicon film is formed on a substrate to serve as a channel, a natural oxide film is removed from the silicon film, the silicon film is irradiated with oxygen plasma, a gate insulating film is formed on the silicon film, and a gate electrode is formed. SOLUTION: An SiO2 base film 102 is deposited on a quartz glass substrate 101, and an impurity-containing silicon thin film 103 is deposited. Resist is applied onto the silicon thin film 103 and patterned, and a source/drain region 104 is formed. A silicon thin film 105 and an amorphous silicon thin film 106 are successively deposited. The substrate is cleaned to remove a natural oxide film, whereby a clean silicon surface is exposed, and the clean surface of the silicon substrate is irradiated with oxygen plasma 109. An amorphous silicon thin film 108 is oxidized, whereby an SiO2 film 110 is obtained. Chromium is deposited for the formation of a gate electrode 113. By this setup, a thin film semiconductor device of excellent characteristics can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はアクティブマトリッ
クス液晶ディスプレイ等に応用される薄膜トランジスタ
や三次元LSIデバイスなど、絶縁性物質上に作成され
る薄膜半導体装置の製造方法に関するもので有り、詳し
くは製造工程の最高温度が600℃程度以下の低温プロ
セスで形成する薄膜半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device formed on an insulating material such as a thin film transistor and a three-dimensional LSI device applied to an active matrix liquid crystal display and the like. The present invention relates to a method for manufacturing a thin-film semiconductor device formed by a low-temperature process in which the maximum temperature is about 600 ° C. or less.

【0002】[0002]

【従来の技術】近年液晶ディスプレイの大画面化、高解
像度化に伴い、その駆動方式は単純マトリックス方式か
らアクティブマトリックス方式へと移行し、大容量の情
報を表示出来る様になりつつ有る。アクティブマトリッ
クス方式は数十万を超える画素を有する液晶ディスプレ
イが可能であり、名画素毎にスイッチングトランジスタ
を形成するもので有る。各種液晶ディスプレイの基板と
しては、透過型ディスプレイを可能ならしめる溶融石英
板やガラスなどの透明絶縁基板が使用されている。
2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving system has shifted from a simple matrix system to an active matrix system, and large-capacity information can be displayed. The active matrix method enables a liquid crystal display having more than hundreds of thousands of pixels, and forms a switching transistor for each name pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmission type display is used.

【0003】しかしながら、表示画面の拡大化や低価格
化を進める場合には絶縁基板として安価な通常ガラスを
使用するのが必要不可欠で有る。従って、この経済性を
維持して尚、アクティブマトリックス方式の液晶ディス
プレイを動作させる薄膜トランジスタを安価なガラス基
板上に安定した性能で形成する事が可能な技術が望まれ
ていた。
However, in order to increase the size of the display screen and reduce the cost, it is essential to use inexpensive ordinary glass as the insulating substrate. Accordingly, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining this economic efficiency.

【0004】従来この様な薄膜トランジスタを作成する
場合、チャンネル部シリコン層を形成した後、ゲート絶
縁層を形成するには、基板を酸素(O)、笑気ガス
(NO)、水蒸気(HO)などを含む酸化性雰囲気
下に挿入し、その温度を800℃から1100℃程度の
高温として、チャンネル部シリコン層の一部を酸化し、
ゲート絶縁層を形成する熱酸化法が用いられていた。或
いは、チャンネル部シリコン層形成後、モノシラン(S
iH)、酸素(O)などを原料ガスとして常圧気相
化学堆積法(APCVD法)等の気相成長法で二酸化硅
素膜(SiO膜)を堆積し、ゲート絶縁層としてい
た。
Conventionally, when such a thin film transistor is formed, a substrate is formed of oxygen (O 2 ), laughing gas (N 2 O), water vapor ( H 2 O) and the like, and the temperature is raised to a high temperature of about 800 ° C. to 1100 ° C. to oxidize a part of the channel portion silicon layer,
A thermal oxidation method for forming a gate insulating layer has been used. Alternatively, after forming the channel silicon layer, monosilane (S
A silicon dioxide film (SiO 2 film) was deposited by a gas phase growth method such as an atmospheric pressure chemical vapor deposition (APCVD method) using iH 4 ), oxygen (O 2 ), or the like as a source gas to form a gate insulating layer.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、先に述
べた従来の方法に於いては、数多くの問題が指摘されて
いる。まず第一に熱酸化法に依るSiO膜の形成で
は、その形成に少なくとも800℃以上の高温熱処理が
伴う為、酸化膜より下部に位置する薄膜層や基板などの
耐熱性が問題となる。例えば大面積液晶ディスプレイの
スイッチング・トランジスタを作成する場合、基板とし
ては非常に高価な溶融石英板以外は斯様な高温に耐え得
ない。又、三次元LSI素子に於いても下層部トランジ
スタが高温で劣下する為、この熱酸化法は事実上使用不
可能となっている。
However, a number of problems have been pointed out in the above-mentioned conventional method. First, in the formation of an SiO 2 film by a thermal oxidation method, a high-temperature heat treatment of at least 800 ° C. or more is involved in the formation, and thus the heat resistance of the thin film layer and the substrate located below the oxide film becomes a problem. For example, when producing a switching transistor for a large-area liquid crystal display, a substrate other than a very expensive fused silica plate cannot withstand such high temperatures. Also, in a three-dimensional LSI device, the thermal oxidation method is practically unusable because the lower layer transistor deteriorates at high temperatures.

【0006】一方APCVD法など気相反応を利用した
絶縁膜堆積方法では基板温度が750℃程度以下とした
低温に依る絶縁膜堆積が可能である。これに依り酸化膜
下の薄膜層の保護や耐熱性の低い安価なガラス基板の使
用が可能となる。しかしながら、気相成長方に依り形成
された絶縁層は一般に膜質が悪く、しかもチャンネル部
シリコン半導体層と絶縁層との界面を清浄に保つ事が困
難な為、動作特性の優れたMIS型薄膜半導体装置を低
温で形成するのは困難であった。
On the other hand, in an insulating film deposition method utilizing a gas phase reaction such as the APCVD method, it is possible to deposit an insulating film at a low temperature of about 750 ° C. or less. This makes it possible to protect the thin film layer below the oxide film and use an inexpensive glass substrate with low heat resistance. However, the insulating layer formed by vapor phase growth generally has poor film quality, and it is difficult to keep the interface between the channel silicon semiconductor layer and the insulating layer clean. It was difficult to form the device at low temperatures.

【0007】従って高温熱処理と同等もしくはそれ以上
の効果をもたらし得る良質なSiO膜の低温製造方法
の開発が期待されていた。
[0007] Therefore, development of a low-temperature method for producing a high-quality SiO 2 film capable of providing an effect equal to or higher than the high-temperature heat treatment has been expected.

【0008】本発明は上記の事情に鑑みてなされたもの
で、その目的とする所はシリコン層をチャンネル部とす
るMIS型薄膜半導体装置に於いて、低温工程で良好な
半導体装置特性を有する界面及び絶縁層を形成すること
に有る。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an MIS type thin film semiconductor device having a silicon layer as a channel portion, the interface having good semiconductor device characteristics in a low temperature process. And forming an insulating layer.

【0009】[0009]

【課題を解決するための手段】本発明は、少なくとも表
面が絶縁性物質である基板の一方面上にチャンネル部シ
リコン膜半導体層を形成し、該半導体層上にゲート絶縁
層、ゲート電極を形成したMIS型電界効果トランジス
タを構成する薄膜半導体装置に於いて、絶縁性物質上に
減圧下で気相化学堆積法(CVD法)を用いて該チャン
ネル部シリコン膜を形成する際、該チャンネル部シリコ
ン膜堆積後、不活性又は環元性減圧零囲気を破る事なく
連続して該チャンネル部シリコン膜上にアモルファス・
シリコン膜を堆積する工程と、前記アモルファス・シリ
コン膜上にゲート絶縁層を形成する前に、前記アモルフ
ァス・シリコン膜上に酸素プラズマを照射する工程を含
む事を特徴とする薄膜半導体装置の製造方法で有る。
According to the present invention, a channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material, and a gate insulating layer and a gate electrode are formed on the semiconductor layer. In the thin film semiconductor device constituting the MIS type field effect transistor described above, when the channel silicon film is formed on an insulating material under reduced pressure by using a chemical vapor deposition method (CVD method), After the film is deposited, an amorphous film is continuously formed on the channel silicon film without breaking the inert or reducing atmosphere.
Depositing a silicon film and, prior to forming a gate insulating layer on the amorphous silicon film, irradiating the amorphous silicon film with oxygen plasma. It is.

【0010】〔作用〕本発明は表層部がアモルファス・
シリコンから成るチャンネル部シリコン層に酸素プラズ
マを照射する事に依り、前記アモルファス・シリコンを
酸化し、ゲート絶縁層の一部位を低温で形成し、しかも
半導体層と絶縁層との界面を清浄化させる事に依り薄膜
半導体装置の特性を向上させた物で有る。
[Action] In the present invention, the surface layer is amorphous.
The amorphous silicon is oxidized by irradiating oxygen plasma to the silicon layer of the channel portion made of silicon to form one portion of the gate insulating layer at a low temperature and to clean the interface between the semiconductor layer and the insulating layer. Therefore, the characteristics of the thin-film semiconductor device are improved.

【0011】[0011]

【実施例】〔実施例1〕以下本発明の実施例を図面を用
いて詳述するが、本発明が以下の実施例に限定されるも
のではない。
[Embodiment 1] An embodiment of the present invention will be described below in detail with reference to the drawings, but the present invention is not limited to the following embodiment.

【0012】図1a〜hはMIS型電界効果トランジス
タを形成するシリコン薄膜半導体装置の製造工程を断面
で示した図である。
FIGS. 1A to 1H are sectional views showing the steps of manufacturing a silicon thin film semiconductor device for forming a MIS field effect transistor.

【0013】本実施例では絶縁基板101として235
mm□の石英ガラスを用いたが、600℃の温度に耐え
得る基板又は下地物質で有るならば、その種類や大きさ
は無論問われない。例えばシリコンウェハー上に形成さ
れた三次元LSIなども下地基板として可能で有る。ま
ず有機洗浄及び酸洗浄した石英ガラス基板101上面に
下地SiO膜102をAPCVD法で堆積する。下地
SiO膜102の形成は基板温度300℃シラン流量
120SCCM、酸素840SCCM、窒素約140S
LM堆積速度3.9オングストローム/Secの条件で
行ない、堆積された膜厚は2000オングストロームで
有る。次にドナー又はアクセプターとなる不純物を含ん
だシリコン薄膜103を減圧気相化学堆積法(LPCV
D法)にて堆積した。(図1a)本実施例1では不純物
としてリンを選び、フォスフィン(PH)0.03S
CCM、モノシラン(SiH)200SCCMを原料
ガスとして堆積温度600℃で1500オングストロー
ム堆積した。この時の堆積速度は30オングストローム
/minで成膜直後のシー卜抵抗値は1951Ω/□で
有った。次に前記シリコン薄膜103上にレジストを形
成し、四弗化炭素(SF)、酸素(O)、窒素(N
)等の混合プラズマでパターニングを行ない、ソース
・ドレイン領域104を形成した。続いて該領域104
表面上の汚物・自然酸化膜を取り除いた後、直ちに、い
ずれチャンネル部を構成する事になるシリコン薄膜10
5といずれプラズマ照射されるアモルファス・シリコン
薄膜106を減圧CVD法で連続して堆積した。(図1
b)本実施例に於ける減圧CVD装置は容積184.5
lで反応室側壁及び天井は石英ガラスから成っている。
石英ガラスで作成された反応室の外側には3ゾーンに分
かれたヒーターが設置されており、それらを独立に調整
する事で反応室内中央部付近に所望の温度で等温領域を
形成する。基板はこの等温領域内に水平に設置して、シ
リコン薄膜1055及びアモルファス・シリコン薄膜1
06を堆積した。シリコン薄膜105は原料ガスとして
モノシラン(SiH)11.25SCCMを用い堆積
温度600℃で、20分39秒間堆積した。希釈ガスは
用いず、この時の反応室内圧力は7.9mTorrで有
った。予備実験に依ると、この条件での堆積速度は、1
2.105オングストローム/minでシリコン薄膜1
05は約250オングストローム堆積されたはずで有
る。続いて、基板を減圧CVD装置から取り出す事なく
連続してアモルファス・シリコン薄膜106を堆積し
た。アモルファス・シリコン薄膜106の堆積温度は5
50℃で有った。シリコン薄膜105は600℃で堆積
された為、アモルファス・シリコン膜106を堆積する
のに約1時間程度の降温期間が必要で有る。この降温期
間中、本実施例ではメカニカル・ブースター・ポンプと
ロータリー・ポンプを運転状態に保ち、反応室には97
%アルゴンと3%水素の混合ガスを1SLM流し続け
た。この時の反応室の圧力は186.5mTorrで有
った。本実施例1ではシリコン薄膜105とアモルファ
ス・シリコン薄膜106との間に酸化膜が介さず、連続
したシリコン界面が形成される様、環元性減圧雰囲気で
降温を行ったが、充分純度の高い不活性ガスで、この条
件を満たし得るならば不活性減圧雰囲気でも可能で有
る。この様にしてシリコン薄膜105の表面を清浄に維
持したまま反応室温度を550℃迄下げて、連続してア
モルファス・シリコン薄膜106を堆積した。原料ガス
としてモノシラン(SiH)30SCCMを用い、5
分22秒間推積した。希釈ガスは用いなかったが、排気
系に付属しているコンダクタンス・バルブの開閉を調整
する事で反応室内の圧力を282mTorrに保った。
予備実験に依ると、この同じ条件で堆積速度は、14.
907オングストローム/minで、アモルファス・シ
リコン薄膜106は約80オングストローム堆積された
はずで有る。次にこうして作成されたシリコン薄膜10
5とアモルファス・シリコン薄膜106上にレジストを
形成し、四弗化炭素(CF)、酸素(O)、窒化
(N)等の混合プラズマでパターニングを行った。
(図1c)。この時、チャンネル部シリコン薄膜107
とアモルファス・シリコン薄膜108の合算膜厚を表面
粗さ計で測った所310オングストロームで有った。
In this embodiment, 235 is used as the insulating substrate 101.
Although mm mm quartz glass was used, its type and size are of course not limited as long as the substrate or base material can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer can be used as a base substrate. First, a base SiO 2 film 102 is deposited on the upper surface of a quartz glass substrate 101 that has been subjected to organic cleaning and acid cleaning by APCVD. The base SiO 2 film 102 is formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM, and nitrogen of about 140 S.
The LM deposition rate was 3.9 angstroms / Sec, and the deposited film thickness was 2000 angstroms. Next, a silicon thin film 103 containing an impurity serving as a donor or an acceptor is formed by a low pressure chemical vapor deposition (LPCV) method.
D method). (FIG. 1a) In the first embodiment, phosphorus is selected as an impurity, and phosphine (PH 3 ) 0.03S
The deposition was performed at 1500 Å at a deposition temperature of 600 ° C. using CCM and 200 SCCM of monosilane (SiH 4 ) as a source gas. At this time, the deposition rate was 30 angstroms / min, and the sheet resistance immediately after the film formation was 1951 Ω / □. Next, a resist is formed on the silicon thin film 103, and carbon tetrafluoride (SF 4 ), oxygen (O 2 ), nitrogen (N
The source / drain regions 104 were formed by performing patterning using a mixed plasma such as 2 ). Subsequently, the area 104
Immediately after removing the dirt and the natural oxide film on the surface, the silicon thin film 10 which will soon constitute the channel portion
5 and an amorphous silicon thin film 106 to be irradiated with plasma were eventually deposited by a low pressure CVD method. (Figure 1
b) The reduced pressure CVD apparatus in this embodiment has a capacity of 184.5.
At 1, the side wall and ceiling of the reaction chamber are made of quartz glass.
Outside the reaction chamber made of quartz glass, heaters divided into three zones are installed, and by independently adjusting them, an isothermal region is formed at a desired temperature near the center of the reaction chamber. The substrate is placed horizontally in this isothermal region, and the silicon thin film 1055 and the amorphous silicon thin film 1 are placed.
06 was deposited. The silicon thin film 105 was deposited at a deposition temperature of 600 ° C. for 20 minutes and 39 seconds using monosilane (SiH 4 ) 11.25 SCCM as a source gas. No diluent gas was used, and the reaction chamber pressure at this time was 7.9 mTorr. According to preliminary experiments, the deposition rate under these conditions was 1
Silicon thin film 1 at 2.105 Å / min
05 should have been deposited about 250 angstroms. Subsequently, an amorphous silicon thin film 106 was continuously deposited without removing the substrate from the low pressure CVD apparatus. The deposition temperature of the amorphous silicon thin film 106 is 5
It was 50 ° C. Since the silicon thin film 105 is deposited at 600 ° C., a temperature reduction period of about one hour is required for depositing the amorphous silicon film 106. During this cooling period, in this embodiment, the mechanical booster pump and the rotary pump are kept in operation and 97
The mixture gas of 3% hydrogen and 3% hydrogen was continuously supplied at 1 SLM. At this time, the pressure in the reaction chamber was 186.5 mTorr. In the first embodiment, the temperature was reduced in a reduced-pressure reducing atmosphere so that a continuous silicon interface was formed without an oxide film between the silicon thin film 105 and the amorphous silicon thin film 106, but the purity was sufficiently high. As long as this condition can be satisfied with an inert gas, an inert reduced pressure atmosphere is also possible. In this manner, the temperature of the reaction chamber was lowered to 550 ° C. while the surface of the silicon thin film 105 was kept clean, and the amorphous silicon thin film 106 was continuously deposited. Using monosilane (SiH 4 ) 30 SCCM as a source gas,
Min 22 seconds. No diluent gas was used, but the pressure in the reaction chamber was maintained at 282 mTorr by adjusting the opening and closing of a conductance valve attached to the exhaust system.
According to preliminary experiments, the deposition rate was 14.
At 907 angstroms / min, the amorphous silicon thin film 106 should have been deposited at about 80 angstroms. Next, the silicon thin film 10 thus prepared
5 and an amorphous silicon thin film 106, a resist was formed, and patterning was performed using a mixed plasma of carbon tetrafluoride (CF 4 ), oxygen (O 2 ), nitride (N 2 ), and the like.
(FIG. 1c). At this time, the channel portion silicon thin film 107
The total film thickness of the amorphous silicon thin film 108 and that measured by a surface roughness meter was 310 Å.

【0014】次に、この基板を沸騰している60%濃度
の硝酸にて洗浄し、更に1.67%弗化水素酸水溶液に
20秒間浸してソース・ドレイン領域104上とアモル
ファス・シリコン薄膜108上の自然酸化膜を取り除い
て清浄なシリコン表面が現われた後、直ちに電子サイク
ロトロン共鳴プラズマCVD装置(ECR−PECVD
装置)にて酵素プラズマ109を照射した。(図1d)
本実施例1で用いたECR−PECVD装置の概要を図
2に示す。酸素プラズマは2.45GHzのマイクロ波
を導波管201を通じて反応室202に導き、100S
CCMの酸素をガス導入管203から導入して酸素プラ
ズマを立てた。この時、反応室内の圧力は1.80mT
orrで、マイクロ波の出力は2500Wで有った。反
応室の外側には外部コイル204が設けられて居り、酸
素プラズマに875Gaussの磁場を掛けてプラズマ
中の電子にECR条件を満足せしめている。基板205
はプラズマに対して垂直に置かれ、ヒーター206に依
り基板温度が300℃となる様保たれている。この条件
で酸素プラズマ109を8分20秒間照射して、アモル
ファス・シリコン薄膜108の酸化を行ない、ゲート絶
縁層の一部位となるSiO膜110を得た。(図1
e)更に真空を破る事なく連続して、ゲート絶縁層とな
るSiO膜111を該基板上に堆積した。(図1f)
このSiO膜はマイクロ波出力2,250W、シラン
流量60SCCM、酸素流量100SCCM、基板温度
300℃で18.75秒間堆積した。堆積中に於ける反
応室内圧力は2.65mTorrで有った。こうして形
成した多層膜を多波長分散型偏光解折法(多波長分光エ
リプソメトリー:ソープラ社MOSS−ES4G)を用
いて、残留しているチャンネル部シリコン膜112の膜
厚と、アモルファス・シリコン膜を酸化して形成したS
iO膜110及びECR−PECVD法で堆積したS
iO膜111の合算SiO膜の膜厚を測定した所、
其々219オングストロームと1480オングストロー
ムで有った。
Next, the substrate is washed with boiling 60% nitric acid and further immersed in a 1.67% aqueous hydrofluoric acid solution for 20 seconds to form a film on the source / drain region 104 and the amorphous silicon thin film 108. Immediately after removing the natural oxide film on the top and a clean silicon surface appears, an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD) is used.
(Device) to irradiate the enzyme plasma 109. (FIG. 1d)
FIG. 2 shows an outline of the ECR-PECVD apparatus used in the first embodiment. The oxygen plasma guides the microwave of 2.45 GHz to the reaction chamber 202 through the waveguide 201,
Oxygen of CCM was introduced from the gas introduction tube 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.80 mT
At orr, the microwave power was 2500 W. An external coil 204 is provided outside the reaction chamber, and a magnetic field of 875 Gauss is applied to the oxygen plasma so that electrons in the plasma satisfy the ECR condition. Substrate 205
Is placed perpendicular to the plasma, and the heater 206 keeps the substrate temperature at 300 ° C. Under this condition, the amorphous silicon thin film 108 was oxidized by irradiating oxygen plasma 109 for 8 minutes and 20 seconds, thereby obtaining a SiO 2 film 110 which would be a part of the gate insulating layer. (Figure 1
e) An SiO 2 film 111 serving as a gate insulating layer was continuously deposited on the substrate without breaking vacuum. (FIG. 1f)
This SiO 2 film was deposited at a microwave output of 2,250 W, a silane flow rate of 60 SCCM, an oxygen flow rate of 100 SCCM, and a substrate temperature of 300 ° C. for 18.75 seconds. The pressure in the reaction chamber during the deposition was 2.65 mTorr. The multilayer film thus formed is subjected to multi-wavelength dispersion-type polarization analysis (multi-wavelength spectroscopic ellipsometry: MOSS-ES4G manufactured by Sopra) to remove the remaining film thickness of the channel portion silicon film 112 and the amorphous silicon film. S formed by oxidation
iO 2 film 110 and S deposited by ECR-PECVD
When the thickness of the total SiO 2 film of the iO 2 film 111 was measured,
They were 219 angstroms and 1480 angstroms, respectively.

【0015】次にクロムをスパッター法で1500オン
グストローム堆積し、パターニングに依りゲート電極1
13を形成した。(図1g)この時シート抵抗値は1.
36Ω/□で有った。その後、ゲート絶縁順にコンタク
トホールを開け、ソース・ドレイン取り出し電極114
をスパッター法などで形成し、パターニングを行なう事
でトランジスタは完成する(図1h)。本実施例1で
は、ソース・ドレイン取り出し電極材料として、膜厚
8,000オングストロームのアルミニウムを用いた。
この時のアルミニウムのシート抵抗値は42mΩ/□で
有った。
Next, chromium is deposited in a thickness of 1500 angstroms by sputtering, and the gate electrode 1 is formed by patterning.
13 was formed. (FIG. 1g) At this time, the sheet resistance value is 1.
It was 36Ω / □. Then, a contact hole is opened in the order of gate insulation, and the source / drain extraction electrode 114 is formed.
Is formed by sputtering or the like, and patterning is performed to complete the transistor (FIG. 1h). In the first embodiment, aluminum having a thickness of 8,000 angstroms was used as a source / drain extraction electrode material.
At this time, the sheet resistance value of aluminum was 42 mΩ / □.

【0016】この様にして試作した薄膜トランジスタ
(TFT)の特性の一例Vgs−Ids曲線を図3、3
−aに示した。ここでIdsはソース・ドレイン電流、
gsはゲート電圧で、ソース・ドレイン電圧Vds
4V、温度25℃で測定した。トランジスタ・サイズは
チャンネル部の長さL=10μm、幅W=100μmで
有った。Vds=4V、Vgs=10Vでトランジスタ
をオンさせた時のオン電流はIds=7.1μA、I
dsが最小となるオフ電流はVds=4V、Vgs=0
VでIds=0.33PAとなり、オン・オフ比は7桁
以上の良好なトランジスタ特性を有する薄膜トランジス
タが得られた。又、このトランジスタの飽和電流領域よ
り求めた電界効果易動度は5.07cm/V・Sec
で有った。図3、3−bには比較の為に、アモルファス
・シリコン薄膜を堆積せず、かつ酸素プラズマ照射も行
なわない他は総て前記工程と同一で作成したと云う、従
来のTFTの特性を示した。この従来のTFTのオン電
流はIds=4.5μA、オフ電流Ids=0.87P
Aで、電界効果易動度は、4.34cm/V・Sec
で有った。
[0016] An example V gs -I ds curve of the characteristics of the thin film transistor was fabricated in this way (TFT) Figure 3,3
-A. Where I ds is the source / drain current,
V gs is a gate voltage, and a source / drain voltage V ds =
The measurement was performed at 4 V and a temperature of 25 ° C. The transistor size was such that the length L of the channel portion was 10 μm and the width W was 100 μm. When the transistor is turned on at V ds = 4 V and V gs = 10 V, the on current is I ds = 7.1 μA,
The off current at which ds is minimized is V ds = 4 V, V gs = 0
At Vs, I ds = 0.33 PA, and a thin film transistor having an on / off ratio of 7 digits or more and excellent transistor characteristics was obtained. The field effect mobility obtained from the saturation current region of this transistor is 5.07 cm 2 / V · Sec.
It was. FIGS. 3 and 3b show, for comparison, the characteristics of a conventional TFT which was prepared in the same manner as the above-mentioned process except that no amorphous silicon thin film was deposited and oxygen plasma irradiation was not performed. Was. The on current of this conventional TFT is I ds = 4.5 μA, and the off current I ds = 0.87 P
At A, the field effect mobility is 4.34 cm 2 / V · Sec
It was.

【0017】こうした結果から、従来例に比べて、本発
明に依って薄膜半導体装置の特性が向上している事が分
かる。
From these results, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention as compared with the conventional example.

【0018】これはMIS型電界効果トランジスタでそ
の卜ランジスタ特性に多大な影響を及ぼす半導体層と絶
縁層の界面をアモルファス・シリコン薄膜の酸素プラズ
マ照射酸化と云う方法で形成した為、清浄な半導体層絶
縁層界面が得られた結果で有る。この事は図3に於いて
本発明の実施例3−aが従来例3−bよりも、ゲート電
圧0V付近での立上がりが急峻になっている事からも裏
付けられる。
This is a MIS type field effect transistor. Since the interface between the semiconductor layer and the insulating layer, which greatly affects the transistor characteristics, is formed by a method called oxygen plasma irradiation oxidation of an amorphous silicon thin film, a clean semiconductor layer is formed. This is the result of obtaining the insulating layer interface. This is supported by the fact that the embodiment 3-a of the present invention has a steeper rise near the gate voltage of 0 V in FIG. 3 than the conventional example 3-b in FIG.

【0019】〔実施例2〕ECR−PECVD装置にて
酸素プラズマを照射する時間を除いて、その他の工程は
総て実施例1と同じ工程で薄膜トランジスタを作成し
た。本実施例2では、アモルファス・シリコン薄膜をE
CR−プラズマ酸化させる為の酸素プラズマ照射時間は
4分10秒間で有った。これ以外は総て実施例1と全く
同じ条件で工程を進めた所、本実施例2では残留してい
るチャンネル部シリコン膜の膜厚は249オングストロ
ームで有り、アモルファス・シリコン膜を酸化して形成
したSiO膜及びECR・PECVD法で堆積したS
iO膜の合算SiO膜の膜厚は1,431オングス
トロームで有った。こうして作成したTFTのオン電流
はIds=7.6μA、オフ電流Ids=0.32PA
で電界効果易動度は5.15cm/V・Secで有っ
た。
Example 2 A thin film transistor was manufactured in the same manner as in Example 1 except for the time of irradiating oxygen plasma with an ECR-PECVD apparatus. In the second embodiment, the amorphous silicon thin film is
The oxygen plasma irradiation time for CR-plasma oxidation was 4 minutes and 10 seconds. Except for this, all the steps were carried out under exactly the same conditions as in Example 1. In Example 2, the thickness of the remaining channel silicon film was 249 angstroms, and was formed by oxidizing the amorphous silicon film. SiO 2 film and S deposited by ECR / PECVD method
The total thickness of the SiO 2 film of the iO 2 film was 1,431 Å. The on current of the TFT thus formed is I ds = 7.6 μA, and the off current I ds = 0.32 PA
And the field effect mobility was 5.15 cm 2 / V · Sec.

【0020】本実施例2に於いても、本発明に依り薄膜
半導体装置の特性が向上する事が分る。
Also in the second embodiment, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention.

【0021】[0021]

【発明の効果】以上述べて来た様に、本発明に依れば、
表面が絶縁性物質で有る基板上への薄膜半導体装置の形
成に於いて、チャンネル部シリコン膜堆積後不活性又は
環元性減圧雰囲気を破る事なく連続して該チャネル部シ
リコン膜上にアモルファス・シリコン膜を堆積し、更に
前記アモルファス・シリコン膜上にゲート絶縁層を形成
する前に、前記アモルファス・シリコン膜上に酸素プラ
ズマを照射する事により、良好なトランジスタ特性を有
する薄膜半導体装置を製造する事が可能となり、LSI
の多層化や薄膜トランジスタを用いたアクティブマトリ
ックス液晶ディスプレイの高性能化を実現すると云う多
大な効果を有する。
As described above, according to the present invention,
In forming a thin film semiconductor device on a substrate having a surface made of an insulating material, after depositing a channel silicon film, an amorphous film is continuously formed on the channel silicon film without breaking an inert or reduced pressure atmosphere. By depositing a silicon film and further irradiating the amorphous silicon film with oxygen plasma before forming a gate insulating layer on the amorphous silicon film, a thin film semiconductor device having good transistor characteristics is manufactured. Things become possible, LSI
This has a great effect of realizing high performance of an active matrix liquid crystal display using multiple layers and thin film transistors.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(h)は本発明の一実施例を示すシリ
コン薄膜半導体装置製造の各工程に於ける素子断面図。
1 (a) to 1 (h) are cross-sectional views of an element in each step of manufacturing a silicon thin-film semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施例に於いて酸素プラズマ照射及び
ゲート絶縁層の一部位となるSiO膜堆積に用いた電
子サイクロトロン共鳴プラズマCVD装置の概要を示す
図。
FIG. 2 is a view showing an outline of an electron cyclotron resonance plasma CVD apparatus used for oxygen plasma irradiation and deposition of a SiO 2 film which is a part of a gate insulating layer in an embodiment of the present invention.

【図3】本発明の効果を示す図。FIG. 3 is a diagram showing the effect of the present invention.

【符号の説明】[Explanation of symbols]

101…絶縁基板 102…下地SiO膜 103…不純物を含んだシリコン薄膜 104…ソース・ドレイン領域 105…シリコン薄膜 106…アモルファス・シリコン薄膜 107…チャンネル部シリコン薄膜 108…アモルファス・シリコン薄膜 109…酸素プラズマ 110…アモルファス・シリコン薄膜を酸化して形成し
たSiO膜 111…ECR・PECVD法で堆積したSiO膜 112…残留しているチャンネル部シリコン膜 113…ゲート電極 114…ソース・ドレイン取り出し電極 201…導波管 202…反応室 203…ガス導入管 204…外部コイル 205…基板 206…ヒーター
101 ... insulating substrate 102 ... base SiO 2 film 103 ... silicon thin film 104 containing an impurity ... source and drain regions 105 ... silicon thin film 106 ... amorphous silicon thin film 107 ... channel portion silicon film 108 ... amorphous silicon thin film 109 ... oxygen plasma 110 ... amorphous · SiO a silicon thin film was formed by oxidizing 2 film 111 ... ECR · SiO 2 film 112 ... channel portion silicon film remaining deposited by a PECVD method 113 ... gate electrode 114 ... source-drain extraction electrodes 201 ... Waveguide 202 ... Reaction chamber 203 ... Gas introduction tube 204 ... External coil 205 ... Substrate 206 ... Heater

【手続補正書】[Procedure amendment]

【提出日】平成11年9月6日(1999.9.6)[Submission Date] September 6, 1999 (September 9, 1999)

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0001[Correction target item name] 0001

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0001】[0001]

【発明の属する技術分野】本発明はアクティブマトリッ
クス液晶ディスプレイ等に応用される薄膜トランジスタ
などの薄膜半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a thin film semiconductor device such as a thin film transistor applied to an active matrix liquid crystal display or the like.

【手続補正3】[Procedure amendment 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0009[Correction target item name] 0009

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0009】[0009]

【課題を解決するための手段】本発明の薄膜半導体装置
の製造方法は、基板上にチャネルとなるシリコン膜を形
成する工程と、前記シリコン膜上の自然酸化膜を除去す
る工程と、前記除去する工程の後に、前記シリコン膜に
酸素プラズマを照射する工程と、前記酸素プラズマを照
射する工程の後に前記シリコン膜上にゲート絶縁膜を形
成する工程と、前記ゲート絶縁膜上にゲート電極を形成
する工程とを有することを特徴とする。
According to a method of manufacturing a thin film semiconductor device of the present invention, a step of forming a silicon film serving as a channel on a substrate; a step of removing a natural oxide film on the silicon film; Performing a step of irradiating the silicon film with oxygen plasma, a step of forming a gate insulating film on the silicon film after the step of irradiating oxygen plasma, and forming a gate electrode on the gate insulating film. And a step of performing

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0010[Correction target item name] 0010

【補正方法】削除[Correction method] Deleted

【手続補正5】[Procedure amendment 5]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0021[Correction target item name] 0021

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0021】[0021]

【発明の効果】以上述べたように、本発明によれば、シ
リコン膜上の自然酸化膜を除去した後に酸素プラズマを
照射することにより、シリコン膜とゲート絶縁膜との界
面を清浄にすることができ、良好な特性の薄膜半導体装
置を製造することが可能となる。LSIの多層化や薄膜
トランジスタを用いたアクティブマトリックス液晶ディ
スプレイの高性能化を実現することが可能である。
As described above, according to the present invention, the interface between the silicon film and the gate insulating film is cleaned by irradiating oxygen plasma after removing the natural oxide film on the silicon film. Thus, a thin film semiconductor device having good characteristics can be manufactured. It is possible to realize multi-layered LSIs and high-performance active matrix liquid crystal displays using thin film transistors.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】少なくとも表面が絶縁性物質である基板の
一方面上にチャンネル部シリコン膜半導体層を形成し、
該半導体層上にゲート絶縁層、ゲート電極を形成したM
IS型電界効果トランジスタを構成する薄膜半導体装置
に於いて、下記工程を含む事を特徴とする薄膜半導体装
置の製造方法。 a)絶縁性物質上に減圧下で気相化学堆積法(CVD
法)を用いて該チャンネル部シリコン膜を形成する際、
該チャンネル部シリコン膜堆積後、不活性又は環元性減
圧雰囲気を破る事なく連続して該チャンネル部シリコン
膜上にアモルファス・シリコン膜を推積する工程。 b)前記アモルファス・シリコン膜上にゲート絶縁層を
形成する前に、前記アモルファス・シリコン膜上に酸素
プラズマを照射する工程。
A channel silicon semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
A gate insulating layer and a gate electrode formed on the semiconductor layer;
A method of manufacturing a thin film semiconductor device comprising a thin film semiconductor device constituting an IS type field effect transistor, comprising the following steps. a) Vapor phase chemical vapor deposition (CVD) on insulating material under reduced pressure
When forming the channel portion silicon film using
A step of continuously depositing an amorphous silicon film on the channel portion silicon film after the channel portion silicon film is deposited without breaking an inert or reducing reduced pressure atmosphere. b) irradiating the amorphous silicon film with oxygen plasma before forming a gate insulating layer on the amorphous silicon film.
JP11235804A 1999-08-23 1999-08-23 Method for manufacturing thin film semiconductor device Expired - Fee Related JP3055555B2 (en)

Priority Applications (1)

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Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2310475A Division JP3038898B2 (en) 1990-11-16 1990-11-16 Method for manufacturing thin film semiconductor device

Publications (2)

Publication Number Publication Date
JP2000082820A true JP2000082820A (en) 2000-03-21
JP3055555B2 JP3055555B2 (en) 2000-06-26

Family

ID=16991509

Family Applications (1)

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Country Link
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