JP3008486B2 - Method for manufacturing thin film semiconductor device - Google Patents

Method for manufacturing thin film semiconductor device

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Publication number
JP3008486B2
JP3008486B2 JP2310476A JP31047690A JP3008486B2 JP 3008486 B2 JP3008486 B2 JP 3008486B2 JP 2310476 A JP2310476 A JP 2310476A JP 31047690 A JP31047690 A JP 31047690A JP 3008486 B2 JP3008486 B2 JP 3008486B2
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Japan
Prior art keywords
film
silicon
thin film
substrate
deposited
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Expired - Fee Related
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JP2310476A
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Japanese (ja)
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JPH04181740A (en
Inventor
光敏 宮坂
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Seiko Epson Corp
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Seiko Epson Corp
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアクティブマトリックス液晶ディスプレイ等
に応用される薄膜トランジスタや三次元LSIデバイスな
ど、絶縁性物質上に作成される薄膜半導体装置の製造方
法に関するもので有り、詳しくは製造工程の最高温度が
600℃程度以下の低温プロセスで形成する薄膜半導体装
置の製造方法に関する。
The present invention relates to a method for manufacturing a thin film semiconductor device formed on an insulating material such as a thin film transistor and a three-dimensional LSI device applied to an active matrix liquid crystal display and the like. In detail, the maximum temperature of the manufacturing process
The present invention relates to a method for manufacturing a thin film semiconductor device formed by a low-temperature process of about 600 ° C. or less.

〔従来の技術〕[Conventional technology]

近年液晶ディスプレイの大画面化、高解像度化に伴
い、その駆動方式は単純マトリックス方式からアクティ
ブマトリックス方式へと移行し、大容量の情報を表示出
来る様になりつつ有る。アクティブマトリックス方式は
数十万を超える画素を有する液晶ディスプレイが可能で
あり、各画素毎にスイッチングトランジスタを形成する
もので有る。各種液晶ディスプレイの基板としては、透
過型ディスプレイを可能ならしめる溶融石英板やガラス
などの透明絶縁基板が使用されている。
In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving system has shifted from a simple matrix system to an active matrix system, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmission type display is used.

しかしながら、表示画面の拡大化や低価格化を進める
場合には絶縁基板として安価な通常ガラスを使用するの
が必要不可欠で有る。従って、この経済性を維持して
尚、アクティブマトリックス方式の液晶ディスプレイを
動作させる薄膜トランジスタを安価なガラス基板上に安
定した性能で形成する事が可能な技術が望まれていた。
However, in order to increase the size of the display screen and reduce the cost, it is essential to use inexpensive ordinary glass as the insulating substrate. Accordingly, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining this economic efficiency.

従来この様な薄膜トランジスタを作成する場合、チャ
ンネル部シリコン層を形成した後、ゲート絶縁層を形成
するには、基板を酸素(O2)、笑気ガス(N2O)、水蒸
気(H2O)などを含む酸化性雰囲気下に插入し、その温
度を800℃から1100℃程度の高温として、チャンネル部
シリコン層の一部を酸化し、ゲート絶縁層を形成する熱
酸化法が用いられていた。或いは、チャンネル部シリコ
ン層形成後、モノシラン(SiH4)、酸素(O2)などを原
料ガスとして常圧気相化学堆積法(APCVD法)等の気相
成長法で二酸化硅素膜(SiO2膜)を堆積し、ゲート絶縁
層としていた。
Conventionally, when such a thin film transistor is formed, after forming a channel portion silicon layer and then forming a gate insulating layer, the substrate is formed of oxygen (O 2 ), laughing gas (N 2 O), water vapor (H 2 O). The thermal oxidation method was used in which the gate insulating layer was formed by oxidizing a part of the silicon layer in the channel section by inserting the film in an oxidizing atmosphere containing) and raising the temperature to about 800 ° C to 1100 ° C. . Alternatively, after the silicon layer in the channel is formed, a silicon dioxide film (SiO 2 film) is formed by a vapor phase growth method such as atmospheric pressure chemical vapor deposition (APCVD) using monosilane (SiH 4 ), oxygen (O 2 ) or the like as a source gas. Was deposited to form a gate insulating layer.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら、先に述べた従来の方法に於いては、数
多くの問題が指摘されている。まず第一に熱酸化法に依
るSiO2膜の形成では、その形成に少なくとも800℃以上
の高温熱処理が伴う為、酸化膜より下部に位置する薄膜
層や基板などの耐熱性が問題となる。例えば大面積液晶
ディスプレイのスイッチング・トランジスタを作成する
場合、基板としては非常に高価な溶融石英板以外は斯様
な高温に耐え得ない。又、三次元LSI素子に於いても下
層部トランジスタが高温で劣下する為、この熱酸化法は
事実上使用不可能となっている。
However, a number of problems have been pointed out in the conventional method described above. First, in the formation of a SiO 2 film by a thermal oxidation method, a high-temperature heat treatment of at least 800 ° C. or more is involved in the formation, and thus the heat resistance of the thin film layer and the substrate located below the oxide film becomes a problem. For example, when producing a switching transistor for a large-area liquid crystal display, a substrate other than a very expensive fused silica plate cannot withstand such high temperatures. Further, even in a three-dimensional LSI device, the thermal oxidation method is practically unusable because the lower layer transistor deteriorates at high temperatures.

一方APCVD法など気相反応を利用した絶縁膜堆積方法
では基板温度が750℃程度以下とした低温に依る絶縁膜
堆積が可能である。これに依り酸化膜下の薄膜層の保護
や耐熱性の低い安価なガラス基板の使用が可能となる。
しかしながら、気相成長方に依り形成された絶縁層は一
般に膜質が悪く、しかもチャンネル部シリコン半導体層
と絶縁層との界面を清浄に保つ事が困難な為、動作特性
の優れたMIS型薄膜半導体装置を低温で形成するのは困
難であった。
On the other hand, an insulating film deposition method using a gas phase reaction such as the APCVD method can deposit an insulating film at a low temperature of about 750 ° C. or less. This makes it possible to protect the thin film layer below the oxide film and use an inexpensive glass substrate with low heat resistance.
However, the insulating layer formed by vapor phase growth generally has poor film quality, and it is difficult to keep the interface between the channel silicon semiconductor layer and the insulating layer clean. It was difficult to form the device at low temperatures.

従って高温熱処理と同等もしくはそれ以上の効果をも
たらし得るなSiO2膜の低温製造方法の開発が期待されて
いた。
Therefore, development of a low-temperature manufacturing method of an SiO 2 film that can provide the same or better effect as the high-temperature heat treatment has been expected.

本発明は上記の事情に鑑みてなされたもので、その目
的とする所はシリコン層をチャンネル部とするMIS型薄
膜半導体装置に於いて、低温工程で良好な半導体装置特
性を有する界面及び絶縁層を形成することに有る。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an interface and an insulating layer having good semiconductor device characteristics in a low-temperature process in an MIS type thin film semiconductor device having a silicon layer as a channel portion. Is formed.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の薄膜半導体装置の製造方法は、基板上にチャ
ネルとなる第1シリコン膜を形成する工程と、前記第1
シリコン膜上に空隙を有する第2シリコン膜を形成する
工程と、前記第2シリコン膜上に酸素プラズマを照射す
る工程と、前記酸素プラズマを照射する工程の後に、前
記第2シリコン膜上にゲート絶縁膜とゲート電極とを形
成する工程を有することを特徴とする。
In the method of manufacturing a thin film semiconductor device according to the present invention, a step of forming a first silicon film serving as a channel on a substrate;
Forming a second silicon film having a void on the silicon film, irradiating the second silicon film with oxygen plasma, and irradiating the oxygen plasma with a gate. A step of forming an insulating film and a gate electrode.

〔作 用〕(Operation)

本発明は表層部が空隙を含むシリコンから成るチャン
ネル部シリコン層に酸素プラズマを照射する事に依り、
前記空隙を含むシリコンを酸化し、ゲート絶縁層の一部
位を低温で形成し、しかも半導体層と絶縁層との界面を
清浄化させる事に依り、薄膜半導体装置の特性を向上さ
せた物で有る。
The present invention is based on irradiating oxygen plasma to a channel portion silicon layer whose surface layer portion is made of silicon including voids,
This is a material in which the characteristics of the thin film semiconductor device are improved by oxidizing the silicon including the voids, forming one portion of the gate insulating layer at a low temperature, and cleaning the interface between the semiconductor layer and the insulating layer. .

〔実 施 例1〕 以下本発明の実施例を図面を用いて詳述するが、本発
明が以下の実施例に限定されるものではない。
Embodiment 1 Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following embodiment.

第1図a〜hはMIS型電界効果トランジスタを形成す
るシリコン薄膜半導体装置の製造工程を断面で示した図
である。
1a to 1h are cross-sectional views showing the steps of manufacturing a silicon thin film semiconductor device for forming an MIS field effect transistor.

本実施例では絶縁基板101として235mm□の石英ガラス
を用いたが、600℃の温度に耐え得る基板又は下地物質
で有るならば、その種類や大きさは無論問われない。例
えばシリコンウェハー上に形成された三次元LSIなども
下地基板として可能で有る。まず有機洗浄及び酸洗浄し
た石英ガラス基板101上面に下地SiO2膜102をAPCVD法で
堆積する。下地SiO2膜102の形成は基板温度300℃シラン
流量120SCCM、酸素840SCCM、窒素約140SLM堆積速度3.9
Å/Secの条件で行ない、堆積された膜厚は2000Åで有
る。次にドナー又はアクセプターとなる不純物を含んだ
シリコン薄膜103を減圧気相化学堆積法(LPCVD法)にて
堆積した。(第1図a)本実施例1では不純物としてリ
ンを選び、フォスフィン(PH3)0.03SCCM、モノシラン
(SiH4)200SCCMを原料ガスとして堆積温度600℃で1500
Å堆積した。この時の堆積速度は30Å/minで成膜直後の
シート抵抗値は1951Ω/□で有った。次に前記シリコン
薄膜103上にレジストを形成し、四弗化炭素(SF4)、酸
素(O2)、窒素(N2)等の混合プラズマでパターニング
を行ない、ソース・ドレイン領域104を形成した。続い
て該領域104表面上の汚物・自然酸化膜を取り除いた
後、直ちに、いずれチャンネル部を構成する事になるシ
リコン薄膜105といずれプラズマ照射される空隙を含ん
だシリコン薄膜106を減圧CVD法で連続して堆積した。
(第1図b)本実施例に於ける減圧CVD装置は容積184.5
で反応室側壁及び天井は石英ガラスから成っている。
石英ガラスで作成された反応室の外側には3ゾーンに分
かれたヒーターが設置されており、それらを独立に調整
する事で反応室内中央部付近に所望の温度で等温領域を
形成する。基板はこの等温領域内に水平に設置して、シ
リコン薄膜105及び空隙を含んだシリコン薄膜106を堆積
した。
In this embodiment, 235 mm square quartz glass is used as the insulating substrate 101. However, the type and size of the substrate or the base material are not limited as long as the substrate or the base material can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer can be used as a base substrate. First, a base SiO 2 film 102 is deposited on an upper surface of a quartz glass substrate 101 that has been subjected to organic cleaning and acid cleaning by an APCVD method. The base SiO 2 film 102 is formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM, and nitrogen of about 140 SLM.
Performed under the condition of Å / Sec, the deposited film thickness is 2000 Å. Next, a silicon thin film 103 containing an impurity serving as a donor or an acceptor was deposited by a low pressure chemical vapor deposition (LPCVD) method. (FIG. 1a) In Example 1, phosphorus was selected as an impurity, and phosphine (PH 3 ) 0.03 SCCM and monosilane (SiH 4 ) 200 SCCM were used as source gases at a deposition temperature of 600 ° C. and 1500 ° C.
Å Deposited. At this time, the deposition rate was 30 ° / min, and the sheet resistance immediately after film formation was 1951 Ω / □. Next, a resist was formed on the silicon thin film 103, and patterning was performed with a mixed plasma of carbon tetrafluoride (SF 4 ), oxygen (O 2 ), nitrogen (N 2 ), etc., to form source / drain regions 104. . Then, immediately after removing the dirt / natural oxide film on the surface of the region 104, the silicon thin film 105 which will eventually constitute a channel portion and the silicon thin film 106 including a void to be plasma-irradiated will be formed by a low pressure CVD method. Deposited continuously.
(FIG. 1b) The reduced pressure CVD apparatus in this embodiment has a capacity of 184.5
The reaction chamber side walls and ceiling are made of quartz glass.
Outside the reaction chamber made of quartz glass, heaters divided into three zones are installed, and by independently adjusting them, an isothermal region is formed at a desired temperature near the center of the reaction chamber. The substrate was placed horizontally in this isothermal region, and a silicon thin film 105 and a silicon thin film 106 including voids were deposited.

シリコン薄膜105は原料ガスとしてモノシラン(Si
H4)11.25SCCMを用い堆積温度600℃で、14分52秒間堆積
した。希釈ガスは用いず、この時の反応室内圧力は7.78
mTorrで有った。予備実験に依ると、この条件での堆積
速度は、12.105Å/minでシリコン薄膜105は約180Å堆積
されたはずで有る。この条件でシリコン薄膜105堆積後
直ちにモノシラン流量を2.25SCCMに落とし、引き続いて
堆積温度600℃で空隙を含んだシリコン薄膜106を9分49
秒間堆積した。希釈ガスは用いず、この時の反応室内圧
力は1.55mTorrで有った。予備実験に依ると、この条件
での堆積速度は8.15Å/minで、空隙を含んだシリコン薄
膜106は約80Å堆積されたはずで有る。
The silicon thin film 105 is made of monosilane (Si
H 4 ) Deposition was performed using 11.25 SCCM at a deposition temperature of 600 ° C. for 14 minutes and 52 seconds. No diluent gas was used, and the reaction chamber pressure at this time was 7.78.
mTorr. According to preliminary experiments, the deposition rate under these conditions should be 12.105 ° / min, and the silicon thin film 105 should have been deposited at about 180 °. Immediately after depositing the silicon thin film 105 under these conditions, the flow rate of monosilane was reduced to 2.25 SCCM, and then the silicon thin film 106 including voids was deposited at 600 ° C. for 9 minutes 49
Deposited for seconds. No diluent gas was used, and the pressure in the reaction chamber at this time was 1.55 mTorr. According to preliminary experiments, the deposition rate under these conditions was 8.15 ° / min, and the silicon thin film 106 including the voids should have been deposited at about 80 °.

本実施例1に示した空隙を含んだシリコン膜とは、多
波長分散型偏光偏光解析法(多波長分光エリプソメトリ
ー:ソープラ社MOSS−ES4G)にて確認された。シリコン
膜が空隙を含んだシリコン膜か否かは以下の手順で調べ
られた。まず、結晶面方位として<100>を有し、リン
がドープされている為に型半導体となり、その抵抗率が
3.0Ωcmの単結晶シリコン・ウェハーを準備した。この
基板を沸騰している温度60%の硝酸中に5分間浸して基
板表面の汚れを取り、更に5%弗化水素酸水溶液に10秒
間浸して基板表面の自然酸化膜を除去した後、直ちにAP
CVD法で2000Åの下地SiO2膜を堆積した。この堆積条件
は本実施例1の下地SiO2膜102を堆積する条件と厳密に
一致している。続いて沸騰硝酸中に基板を5分間浸し、
更に1.67%弗化水素酸水溶液に15秒から25秒浸した後、
シリコン膜を前記SiO2上に200Åから400Å程度の厚さで
形成する。本実施例では減圧CVD法にて堆積温度600℃、
モノシラン流量2.25SCCM、堆積時間42分56秒、反応室内
圧力1.63mTorrで350Åの厚さに堆積した試料を用いた
が、シリコン膜が空隙を含むか否かを確認する目的で有
るから、シリコン膜の形成方法は、無論どんな方法で有
ってもかまわない。この様にしてして得られた試料を多
波長分散型偏光解析法で調べて、空隙の有無を確認す
る。多波長分光エリプソメトリーは回転偏光子を用い、
波長領域250nmから850nm迄走査した。入射光角は75.10
゜で有った。得られたtanΨとcosΔのスペクトルは、予
め測定されて有った空隙のスペクトルやアモルファス・
シリコンのスペクトル及び結晶シリコンのスペクトルを
複素屈折率に関するBRUGGEMANの公式(D.A.G.BRUGGEMA
N、Ann.Phys.(Leipzig)24,636(1935)に従って合成
した合成スペクトルと比較された。この際、各成分の体
積混合比を任意の割合に設定し得る為、それらの割合の
内、最も測定スペクトルと良く一致する体積混合比から
空隙の有無を判定出来る。減圧CVD法にて堆積温度600
℃、モノシラン流量2.25SCCM・堆積時間42分56秒、反応
室内圧力1.63mTorrで350Åの厚さに堆積したシリコン膜
では、シリコン膜中に49%の空隙が認められた。又、矢
張減圧CVD法にて堆積温度600℃、モノシラン流量4.50SC
CM、堆積時間36分45秒、反応室内圧力3.5mTorrで310Å
の厚さに堆積したシリコン膜では、シリコン膜中に30%
の空隙が認められた。他方、減圧CVD法で堆積温度600
℃、モノシラン流量が6.75SCCM以上、反応室内圧力が4.
6mTorr以上で堆積したシリコン膜中には、空隙の存在は
認められなかった。以上の手法でシリコン膜中に空隙の
有無を判定し得る。
The silicon film including voids shown in Example 1 was confirmed by multi-wavelength dispersion-type polarization ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSS-ES4G by Sopra). The following procedure was used to determine whether the silicon film was a silicon film containing voids. First, it has a crystal plane orientation of <100> and becomes a type semiconductor because it is doped with phosphorus.
A 3.0 Ωcm single crystal silicon wafer was prepared. The substrate is immersed in boiling nitric acid at a temperature of 60% for 5 minutes to remove dirt on the substrate surface, and further immersed in a 5% aqueous hydrofluoric acid solution for 10 seconds to remove a natural oxide film on the substrate surface. AP
A 2000 mm thick SiO 2 film was deposited by CVD. These deposition conditions exactly match the conditions for depositing the underlying SiO 2 film 102 of the first embodiment. Then immerse the substrate in boiling nitric acid for 5 minutes,
After immersing in a 1.67% hydrofluoric acid aqueous solution for 15 to 25 seconds,
A silicon film is formed on the SiO 2 with a thickness of about 200 ° to 400 °. In this embodiment, the deposition temperature is 600 ° C. by the low pressure CVD method,
A monosilane flow rate of 2.25 SCCM, a deposition time of 42 minutes and 56 seconds, and a reaction chamber pressure of 1.63 mTorr, and a sample deposited to a thickness of 350 mm with a thickness of 350 mm were used.Since the purpose is to check whether the silicon film contains voids, the silicon film Of course, any method may be used. The sample thus obtained is examined by multi-wavelength dispersion-type ellipsometry to confirm the presence or absence of voids. Multi-wavelength spectroscopic ellipsometry uses a rotating polarizer,
Scanning was performed from a wavelength region of 250 nm to 850 nm. The incident light angle is 75.10
It was ゜. The obtained tan Ψ and cos は spectra are obtained from the previously measured void spectra and amorphous
BRUGGEMAN formula (DAGBRUGGEMA) for complex refractive index of silicon spectrum and crystalline silicon spectrum
N, Ann.Phys. (Leipzig) were compared with synthesized composite spectrum according to 24, 636 (1935). At this time, since the volume mixing ratio of each component can be set to an arbitrary ratio, the presence or absence of voids can be determined from the volume mixing ratio that best matches the measured spectrum among those ratios. Deposition temperature 600 by low pressure CVD
In a silicon film deposited at 350 ° C. at a temperature of 125 ° C., a monosilane flow rate of 2.25 SCCM, a deposition time of 42 minutes and 56 seconds, and a reaction chamber pressure of 1.63 mTorr, 49% voids were observed in the silicon film. In addition, deposition temperature 600 ° C, flow rate of monosilane 4.50SC by Yabari low pressure CVD method
CM, deposition time 36 minutes 45 seconds, reaction chamber pressure 3.5 mTorr 310Å
Silicon film deposited to a thickness of 30% in the silicon film
Voids were observed. On the other hand, deposition temperature 600
° C, monosilane flow rate is 6.75 SCCM or more, reaction chamber pressure is 4.
No void was found in the silicon film deposited at 6 mTorr or more. The presence or absence of a void in the silicon film can be determined by the above method.

次に、こうして作成されたシリコン薄膜105と空隙を
含むシリコン薄膜106上にレジストを形成し、四弗化炭
素(CF4)、酸素(O2)、窒素(N2)等の混合プラズマ
でパターニングを行った。(第1図c)。この時、チャ
ンネル部シリコン薄膜107と空隙を含んだシリコン薄膜1
08の合算膜厚を表面粗さ計で測った所238Åで有った。
Next, a resist is formed on the silicon thin film 105 thus formed and the silicon thin film 106 including voids, and is patterned by a mixed plasma of carbon tetrafluoride (CF 4 ), oxygen (O 2 ), nitrogen (N 2 ) and the like. Was done. (FIG. 1c). At this time, the channel portion silicon thin film 107 and the silicon thin film
It was 238 mm when the total film thickness of 08 was measured with a surface roughness meter.

次に、この基板を沸騰している60%濃度の硝酸にて洗
浄し、更に1.67%弗化水素酸水溶液に20秒間浸してソー
ス・ドレイン領域104上と空隙を含んだシリコン薄膜108
上の自然酸化膜を取り除いて清浄なシリコン表面が現わ
れた後、直ちに電子サイクロトロン共鳴プラズマCVD装
置(ECR−PECVD装置)にて酸素プラズマ109を照射し
た。(第1図d)本実施例1で用いたECR−PECVD装置の
概要を第2図に示す。酸素プラズマは2.45GHzのマイク
ロ波を導波管201を通じて反応室202に導き、100SCCMの
酸素をガス導入管203から導入して酸素プラズマを立て
た。この時、反応室内の圧力は1.80mTorrで、マイクロ
波の出力は2,500Wで有った。反応室の外側には外部コイ
ル204が設けられて居り、酸素プラズマに875Gaussの磁
場を掛けてプラズマ中の電子にECR条件を満足せしめて
いる。基板205はプラズマに対して垂直に置かれ、ヒー
ター206に依り基板温度が300℃となる様保たれている。
この条件で酸素プラズマ109を8分20秒間照射して、空
隙を含んだシリコン薄膜108の酸化を行ない、ゲート絶
縁層の一部位となるSiO2膜110を得た。(第1図e)更
に真空を破る事なく連続して、ゲート絶縁層となるSiO2
膜111を該基板上に堆積した。(第1図f)このSiO2
はマイクロ波出力2,250W、シラン流量60SCCM、酸素流量
100SCCM、基板温度300℃で18.75秒間堆積した。堆積中
に於ける反応室内圧力は2.65mTorrで有った。こうして
形成した多層膜を多波長分散型偏光解析法(多波長分光
エリプソメトリー:ソープラ社MOSS−ES4G)を用いて、
残留しているチャンネル部シリコン膜112の膜厚と、空
隙を含んだシリコン膜を酸化して形成したSiO2膜110及
びECR−PECVD法で堆積したSiO2膜111の合算SiO2膜の膜
厚を測定した所、其々174Åと1432Åで有った。
Next, the substrate is washed with boiling 60% concentration nitric acid and further immersed in a 1.67% aqueous hydrofluoric acid solution for 20 seconds to form a silicon thin film 108 on the source / drain region 104 and including voids.
Immediately after the upper silicon oxide film was removed and a clean silicon surface appeared, oxygen plasma 109 was irradiated by an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 1d) The outline of the ECR-PECVD apparatus used in the first embodiment is shown in FIG. As the oxygen plasma, a microwave of 2.45 GHz was guided to the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen was introduced from the gas introduction tube 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.80 mTorr, and the microwave output was 2,500 W. An external coil 204 is provided outside the reaction chamber, and a magnetic field of 875 Gauss is applied to the oxygen plasma to satisfy the ECR condition for the electrons in the plasma. The substrate 205 is placed perpendicular to the plasma, and the temperature of the substrate is kept at 300 ° C. by the heater 206.
Under these conditions, oxygen plasma 109 was irradiated for 8 minutes and 20 seconds to oxidize the silicon thin film 108 including the voids, thereby obtaining an SiO 2 film 110 as one portion of the gate insulating layer. (FIG. 1e) SiO 2 to be a gate insulating layer continuously without breaking vacuum
A film 111 was deposited on the substrate. (Fig. 1f) This SiO 2 film has a microwave output of 2,250 W, a silane flow rate of 60 SCCM, and an oxygen flow rate.
Deposition was performed at 100 SCCM at a substrate temperature of 300 ° C. for 18.75 seconds. The pressure in the reaction chamber during deposition was 2.65 mTorr. The multilayer film thus formed is subjected to multi-wavelength dispersion-type ellipsometry (multi-wavelength spectroscopic ellipsometry: Sopra MOSS-ES4G).
And the film thickness of the residual to that channel portion silicon film 112, the thickness of the combined SiO 2 film of the SiO 2 film 111 which is deposited by the SiO 2 film 110 and the ECR-PECVD method was formed by oxidizing a silicon film containing voids The measured values were 174Å and 1432Å, respectively.

次にクロムをスパッター法で1500Å堆積し、パターニ
ングに依りゲート電極113を形成した。(第1図g)こ
の時シート抵抗値は1.36Ω/□で有った。その後、ゲー
ト絶縁膜にコンタクホールを開け、ソース・ドレイン取
り出し電極114をスパッター法などで形成し、パターニ
ングを行なう事でトランジスタは完成する。(第1図
h)本実施例1では、ソース・ドレイン取り出し電極材
料として、膜厚8000Åのアルミニウムを用いた。この時
のアルミニウムのシート抵抗値は42mΩ/□で有った。
Next, chromium was deposited at 1500 ° by a sputtering method, and a gate electrode 113 was formed by patterning. (FIG. 1g) At this time, the sheet resistance was 1.36 Ω / □. Thereafter, a contact hole is formed in the gate insulating film, a source / drain extraction electrode 114 is formed by a sputtering method or the like, and the transistor is completed by performing patterning. (FIG. 1h) In Example 1, aluminum having a film thickness of 8000 ° was used as a source / drain extraction electrode material. At this time, the sheet resistance value of aluminum was 42 mΩ / □.

この様にして試作した薄膜トランジスタ(TFT)の特
性の一例Vgs−Ids曲線を第3図3−aに示した。ここで
Idsはソース・ドレイン電流、Vgsはゲート電圧で、ソー
ス・ドレイン電圧Vds=4V、温度25℃で測定した。トラ
ンジスタ・サイズはチャンネル部の長さL=10μm、幅
W=100μmで有った。Vds=4V、Vgs=10Vでトランジス
タをオンさせた時のオン電流はIds=7.9μA、Idsが最
小となるオフ電流はVds=4V、Vgs=0VでIds=0.38PAと
なり、オン・オフ比は7桁以上の良好なトランジスタ特
性を有する薄膜トランジスタが得られた。又、このトラ
ンジスタの飽和電流領域より求めた電界効果易動度は6.
95cm2/V・Secで有った。第3図3−bには比較の為に、
空隙を含むシリコン薄膜を堆積せず、かつ酸素プラズマ
照射も行なわない他は総て前記工程と同一で作成したと
云う、従来のTFTの特性を示した。この従来のTFTのオン
電流はIds=5.1μA、オフ電流Ids=0.81PAで、電界効
果易動度は、4.45cm2/V・Secで有った。
An example V gs -I ds curve characteristics of the thin film transistor was fabricated in this way (TFT) as shown in FIG. 3 3-a. here
I ds is a source / drain current, V gs is a gate voltage, and measured at a source / drain voltage V ds = 4 V and a temperature of 25 ° C. The transistor size was such that the length L of the channel portion was 10 μm and the width W was 100 μm. V ds = 4V, V gs = 10V ON current when turn on the transistor in the I ds = 7.9μA, off-current is V ds = 4V which I ds is minimized, V gs = at 0V I ds = 0.38 Pa As a result, a thin film transistor having good transistor characteristics with an on / off ratio of 7 digits or more was obtained. The field effect mobility calculated from the saturation current region of this transistor is 6.
It was 95cm 2 / V · Sec. FIG. 3B shows, for comparison,
The characteristics of the conventional TFT were exhibited, except that the silicon thin film including voids was not deposited and oxygen plasma irradiation was not performed, and all the steps were performed in the same manner as in the above process. The on current of this conventional TFT was I ds = 5.1 μA, the off current I ds = 0.81 PA, and the field effect mobility was 4.45 cm 2 / V · Sec.

こうした結果から、従来例に比べて、本発明に依って
薄膜半導体装置の特性が向上している事が分かる。
From these results, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention as compared with the conventional example.

これはMIS型電界効果トランジスタでそのトランジス
タ特性に多大な影響を及ぼす半導体層と絶縁層の界面を
空隙を含んだシリコン薄膜の酸素プラズマ照射酸化と云
う方法で形成した為、清浄な半導体層絶縁層界面が得ら
れた結果で有る。この事は第3図に於いて本発明の実施
例3−aが従来例3−bよりも、ゲート電圧0V付近での
立上がりが急峻になっている事からも裏付けられる。
This is an MIS type field effect transistor. The interface between the semiconductor layer and the insulating layer, which greatly affects the transistor characteristics, is formed by a method called oxygen plasma irradiation oxidation of a silicon thin film containing voids. This is the result of obtaining an interface. This is supported by the fact that the embodiment 3-a of the present invention has a steeper rise near the gate voltage 0V than the conventional example 3-b in FIG.

〔実 施 例2〕 ECR−PECVD装置にて酸素プラズマを照射する時間を除
いて、その他の工程は総て実施例1と同じ工程で薄膜ト
ランジスタを作成した。本実施例2では、空隙を含んだ
シリコン薄膜をECR−プラズマ酸化させる為の酸素プラ
ズマ照射時間は4分10秒間で有った。これ以外は総て実
施例1と全く同じ条件で工程を進めた所、本実施例2で
は残留しているチャンネル部シリコン膜の膜厚は198Å
で有り、空隙を含んだシリコン膜を酸化して形成したSi
O2膜及びECR・PECVD法で堆積したSiO2膜の合算SiO2膜の
膜厚は1394Åで有った。こうして作成したTFTのオン電
流はIds=7.9μA、オフ電流Ids=0.36PAで電界効果易
動度は7.02cm2/V・Secで有った。
Example 2 A thin film transistor was formed in the same manner as in Example 1 except for the time of irradiating oxygen plasma with an ECR-PECVD apparatus. In Example 2, the oxygen plasma irradiation time for ECR-plasma oxidation of the silicon thin film including the void was 4 minutes and 10 seconds. Except for this, all the steps were carried out under the same conditions as in Example 1. In Example 2, the remaining channel portion silicon film had a thickness of 198 mm.
Si formed by oxidizing a silicon film containing voids
The film thickness of the combined SiO 2 film of SiO 2 film deposited by O 2 film and ECR · PECVD method was there at 1394A. The on current of the TFT thus prepared was I ds = 7.9 μA, the off current I ds = 0.36 PA, and the field effect mobility was 7.02 cm 2 / V · Sec.

本実施例2に於いても、本発明に依り薄膜半導体装置
の特性が向上する事が分る。
Also in the second embodiment, it can be seen that the characteristics of the thin film semiconductor device are improved according to the present invention.

〔発明の効果〕〔The invention's effect〕

以上述べて来た様に、本発明に依れば、表面が絶縁性
物質で有る基板上への薄膜半導体装置の形成に於いて、
チャンネル部シリコン膜堆積後、連続して該チャンネル
部シリコン膜上に空隙を含んだシリコン膜を堆積し、更
に前記空隙を含んだシリコン膜上にゲート絶縁層を形成
する前に、前記空隙を含んだシリコン膜上に酸素プラズ
マを照射する事により、良好なトランジスタ特性を有す
る薄膜半導体装置を製造する事が可能となり、LSIの多
層化や薄膜トランジスタを用いたアクティブマトリック
ス液晶ディスプレイの高性能化を実現すると云う多大な
効果を有する。
As described above, according to the present invention, in forming a thin-film semiconductor device on a substrate whose surface is an insulating material,
After the channel portion silicon film is deposited, a silicon film including a void is continuously deposited on the channel portion silicon film, and further including the void before forming a gate insulating layer on the silicon film including the void. By irradiating the silicon film with oxygen plasma, it becomes possible to manufacture a thin-film semiconductor device with good transistor characteristics, and to achieve multi-layer LSI and high performance of an active matrix liquid crystal display using thin film transistors. It has a great effect.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(h)は本発明の一実施例を示すシリコ
ン薄膜半導体装置製造の各工程に於ける素子断面図。 第2図は本発明の実施例に於いて酸素プラズマ照射及び
ゲート絶縁層の一部位となるSiO2膜堆積に用いた電子サ
イクロトロン共鳴プラズマCVD装置の概要を示す図。 第3図は本発明の効果を示す図。 101……絶縁基板 102……下地SiO2膜 103……不純物を含んだシリコン薄膜 104……ソース・ドレイン領域 105……シリコン薄膜 106……空隙を含んだシリコン薄膜 107……チャンネル部シリコン薄膜 108……空隙を含んだシリコン薄膜 109……酸素プラズマ 110……空隙を含んだシリコン薄膜を酸化して形成したS
iO2膜 111……ECR・PECVD法で堆積したSiO2膜 112……残留しているチャンネル部シリコン膜 113……ゲート電極 114……ソース・ドレイン取り出し電極 201……導波管 202……反応室 203……ガス導入管 204……外部コイル 205……基板 206……ヒーター
1 (a) to 1 (h) are cross-sectional views of an element in each step of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention. FIG. 2 is a view showing an outline of an electron cyclotron resonance plasma CVD apparatus used for oxygen plasma irradiation and deposition of a SiO 2 film which is a part of a gate insulating layer in an embodiment of the present invention. FIG. 3 is a view showing the effect of the present invention. 101: insulating substrate 102: base SiO 2 film 103: silicon thin film containing impurities 104: source / drain region 105: silicon thin film 106: silicon thin film including voids 107: channel silicon thin film 108 …… Silicon thin film containing voids 109 …… Oxygen plasma 110 …… S formed by oxidizing silicon thin film containing voids
iO 2 film 111 SiO 2 film deposited by ECR / PECVD method 112 Remaining channel silicon film 113 Gate electrode 114 Source / drain extraction electrode 201 Waveguide 202 Reaction Chamber 203: gas introduction tube 204: external coil 205: substrate 206: heater

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板上にチャネルとなる第1シリコン膜を
形成する工程と、前記第1シリコン膜上に空隙を有する
第2シリコン膜を形成する工程と、前記第2シリコン膜
上に酸素プラズマを照射する工程と、前記酸素プラズマ
を照射する工程の後に、前記第2シリコン膜上にゲート
絶縁膜とゲート電極とを形成する工程を有することを特
徴とする薄膜半導体装置の製造方法。
A step of forming a first silicon film serving as a channel on a substrate; a step of forming a second silicon film having a gap on the first silicon film; and an oxygen plasma on the second silicon film. And a step of forming a gate insulating film and a gate electrode on the second silicon film after the step of irradiating oxygen gas and the step of irradiating oxygen plasma.
JP2310476A 1990-11-16 1990-11-16 Method for manufacturing thin film semiconductor device Expired - Fee Related JP3008486B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2310476A JP3008486B2 (en) 1990-11-16 1990-11-16 Method for manufacturing thin film semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2310476A JP3008486B2 (en) 1990-11-16 1990-11-16 Method for manufacturing thin film semiconductor device

Publications (2)

Publication Number Publication Date
JPH04181740A JPH04181740A (en) 1992-06-29
JP3008486B2 true JP3008486B2 (en) 2000-02-14

Family

ID=18005702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2310476A Expired - Fee Related JP3008486B2 (en) 1990-11-16 1990-11-16 Method for manufacturing thin film semiconductor device

Country Status (1)

Country Link
JP (1) JP3008486B2 (en)

Also Published As

Publication number Publication date
JPH04181740A (en) 1992-06-29

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