JP2000078005A - Clock control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply a clock for a period between a reset signal is inputted and PLL is completed by selecting the inputted clock for a period till the phase of a PLL circuit is locked after a reset signal is inputted and selecting the clock outputted from the PLL circuit after the phase of the PLL circuit is locked. SOLUTION: An inputted original clock 14 is fed back to a PLL 11 via a clock driver 12 and a loop buffer 17. The PLL 11 automatically controls and outputs an output clock so as to secure synchronization between the inputted original clock 14 and a fed-back clock. A clock control means 16 controls every selector 15 to output the clock 14 before the clock synchronization is secured and then to output the clock that is outputted from the PLL 11 after the synchronization of the PLL 11 is secured. Since other peripheral circuits can be initialized by outputting the clock 14, the start-up time is shortened for a clock control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit, and more particularly to a circuit capable of effectively switching clocks in a device using a PLL (Phase Locked Loop).

[0002]

2. Description of the Related Art A PLL is used for a device that requires accurate synchronization between signals. In recent years, a digital phase locked loop (DPLL) circuit in which all circuits are digitized has been used in many digital devices such as a computer. Used in equipment.

[0003] These DPLL circuits are described in JP-A-4-252616, JP-A-5-75448, and JP-A-8-381184.

FIG. 7 is a block diagram of a conventional clock control circuit using a PLL. This circuit includes a PLL 71 having an input terminal to which a basic clock 74 is input, and a P
Clock driver 72 for distributing signals from LL to a plurality
In this embodiment, four FFs (flip-flops) 73
And a clock control means 76 for outputting a lock time measurement and hold release signal, and a loop buffer 77 for returning a signal from the clock driver to the PLL again.

[0005] The clock control circuit of this conventional example feeds back a basic clock 74 input from an input terminal to a PLL 71 via a clock driver 72 and a loop buffer 77. Waveform matches with synchronized clock (synchronous or locked)
The clock control means 76 measures the lock time until synchronization and outputs a hold release signal after the clocks are synchronized.

FIG. 8 is a block diagram showing the inside of the clock control means 76 of FIG. The clock control means 76 of the conventional example includes a counter 81 to which a reset signal and a hold release signal are input, and a comparator 82 which outputs a hold release signal when the output from the counter reaches a predetermined value.

FIG. 9 is a time chart from the input of the reset signal of the conventional clock control circuit to the start of operation. When the reset signal is input at the timing indicated by 91 in the figure, the counter 81 inside the clock control means 76 starts counting the cycles of the input clock, and the comparator 82 determines that the count number output from the counter is a clock. Number of cycles (x) obtained by adding a predetermined number of cycles (z) to the number of cycles (x) until the lock of
+ Z) (at timing 92 in the figure), a hold release signal is output, and supply of the locked clock to other circuits via each FF 73 is started.

[0008]

Since the conventional clock control circuit operates as described above, no clock is supplied to other circuits until the lock of the clock is completed after the reset signal is input.

Therefore, all the circuits operating based on the clock must stop their operations until the PLL shown by 93 in FIG. 9 completes the lock. There was a problem that it took.

A circuit capable of operating another circuit even when the PLL circuit deviates from the locked state is disclosed in
It is described in JP-A-3-044359. This circuit is configured to switch a switch and supply a reference clock signal input to the PLL to the counter circuit when the detection unit detects that the PLL circuit is no longer locked. Therefore, even if the PLL circuit is not locked, it is possible to generate a write address based on the reference clock signal.

However, in the circuit configured as described above, when the clock is switched between the clock output from the PLL and the reference clock, the clock waveform may be disturbed, which may cause a malfunction.

According to the present invention, in order to solve the above-mentioned inconveniences, a clock can be supplied even after a reset signal is input and a PLL is locked, and an operation based on the clock is performed. It is an object of the present invention to provide a clock control circuit capable of operating the above circuit correctly.

[0013]

A clock control circuit according to an aspect of the present invention includes a PLL circuit for synchronizing the phases of an input clock and an output clock, and a PLL circuit for synchronizing an input clock and an output clock from the PLL circuit. A selector for selecting and outputting any one of a clock and a selector for selecting and outputting the input clock until the PLL circuit synchronizes the phase after a reset signal is input;
Clock control means for switching the selector so as to select and output a clock output from the PLL circuit from the input clock after the PLL circuit synchronizes phases. .

In the clock control circuit according to the present invention, the input clock is output from when the reset signal is input until the PLL synchronizes the phases of the input clock and the output clock, and the PLL circuit synchronizes the phase. After that, the output clock is switched to the clock phase-locked by the PLL and output, so that other circuits can be operated even after the reset signal is input until the phase synchronization by the PLL is completed, The startup time of the entire circuit that operates based on the clock output from the clock control circuit can be reduced.

If the clock control means is configured to output a signal for stopping the operation of a circuit connected to the output terminal of the selector for a predetermined period before and after the selector switches the output, In this case, even if the clock waveform is disturbed, it is possible to prevent other circuits from malfunctioning, which is preferable.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock control circuit according to the present invention. This circuit uses the basic clock 14
PLL11 having an input terminal for receiving
A clock driver 12 for distributing a signal from one to a plurality
In this embodiment, four FFs (flip-flops) 13
And four selectors 15 each of which receives a basic clock and a clock output from the PLL 11 and switches an input signal to the FF 13, and a clock control unit 16 that measures lock time and outputs a signal to each selector 15.
And the signal from the clock driver 12
And a loop buffer 17 that feeds back to the loop.

The clock control circuit of this embodiment feeds back the basic clock 14 input from the input terminal to the PLL 11 via the clock driver 12 and the loop buffer 17, and the PLL 11 returns the basic clock 14 Waveform matches with synchronized clock (synchronous or locked)
The clock control means 16 outputs the basic clock 14 until the lock is synchronized, and outputs it from the PLL after the lock of the PLL is completed. Each selector 15 is controlled so as to output a clock.

FIG. 2 is a block diagram showing the inside of the clock control means 16 of FIG. The clock control unit 16 of the present embodiment includes a counter 21 to which a reset signal and a count stop signal are input, and one of three signals corresponding to when the output from the counter reaches one of three predetermined values. And a comparator 22 that outputs the same.

Hereinafter, how the clock is switched will be described with reference to FIGS. 2 and 3. FIG.

FIG. 3 is a time chart for explaining the operation of the clock control circuit of the present invention. When a reset signal is input at the timing indicated by 11 in the figure, the counter 11 inside the clock control means 16 starts counting cycles of the input clock. The comparator 22
When the count number output from the counter reaches the cycle number (x) corresponding to the time when the clock lock is completed (at timing 33 in FIG. 8), a set signal indicating clock switching is output, and the clock signal is output. When the number of cycles (x−y) corresponding to a predetermined time before the lock is completed reaches (the timing of 32 in FIG. 3), a function temporary stop signal is output to prevent malfunction at the time of clock switching. When the number of cycles (x + z) corresponding to a predetermined time after the clock lock is completed (3 in FIG. 3)
At timing 4), a function restart signal is output in order to restart the function temporarily stopped.

The clock output from the clock control circuit according to the present embodiment corresponds to the clock shown in FIG. 3 from the timing 31 when the reset signal is input to the time when the function temporary stop signal is output.
The period indicated by 5 is the basic clock input to the PLL, and the locked clock output from the PLL after the timing at which the function restart signal is output at 34.
Therefore, compared with the conventional clock control circuit, the basic clock is output and the other peripheral circuits are initialized during the period indicated by 35 in FIG. 3 from when the reset signal is input to when the function suspension signal is output. And so on, so that the entire time required for activation is reduced.

No clock is output during the period indicated by 36 in FIG. 3 from the timing of outputting the function suspending signal to the timing of outputting the function resuming signal. This prevents the waveform from being disturbed when switching from the basic clock to the locked clock, and prevents the malfunction due to the disturbance of the waveform.

Next, an example using the clock control circuit of the present invention will be described with reference to FIGS.

FIG. 4 is a block diagram showing the configuration of an LSI including a PLL circuit and peripheral circuits. Reference numeral 41 denotes an LSI incorporating a clock circuit 410 including a PLL circuit.
It is connected to the I bus 42, CPU 43, and boot ROM 44. The LSI 41 includes, in addition to the clock circuit 410, an interface circuit 414 with the PCI bus 42,
An interface circuit 413 for performing bidirectional data transfer with the CPU 43, an interface circuit 412 for controlling the boot ROM 44, a PCI configuration register 415, an internal RAM 416, and an internal RAM initialization circuit 417 for initializing the internal RAM 416 It has.

The LSI 41 shown in FIG. 4 initializes internal FFs and the like by a reset signal at the time of start-up, then executes a configuration cycle for operating PCI and performs L
Setting of the PCI configuration including setting of the PCI configuration register 415 of the SI, access of the boot ROM in which the CPU reads the contents of the boot ROM 44,
In order to determine the contents of the internal RAM 416, it is necessary to perform initialization such as initialization of the internal RAM for writing initialization data to all addresses.

FIG. 5 is a time chart showing the operation of the LSI shown in FIG. 4 at the time of startup when a conventional clock control circuit is used for the clock circuit 410. Since the conventional clock control circuit does not output the clock until the PLL lock is completed as described above, after the reset signal is input at the timing of 51, the initialization operation of the PLL is performed.
From the timing 52 when the initialization of the PLL is completed, the access of the boot ROM necessary for the initialization of the
CI configuration settings and internal RAM
Is performed, the initialization time of other circuits is required as the entire startup time in addition to the time required for PLL lock. In addition, while waiting for the completion of PLL lock, it is necessary to perform wait control by software or hardware so that other circuits wait.

FIG. 6 is a time chart showing the operation of the LSI shown in FIG. 4 at the time of startup when the clock control circuit of the present invention is used for the clock circuit 410. As described above, the clock control circuit of the present invention outputs the input basic clock until the PLL lock is completed,
After the locking of L is completed, the locked clock output from the PLL is output. Therefore, for example, after the reset signal is input at the timing 61, the PLL lock (PLL initialization) and the initialization operation of other circuits can be performed in parallel. Here, if the initialization of the other circuits ends at the timing 63 and is shorter than the time required for PLL lock, the timing of the PLL lock end 6
In 2, the initialization operation of all the circuits is completed, and the total start-up time is reduced by the time required for the initialization of other circuits as compared with the case where the conventional clock control circuit is used.

The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, the circuit configurations shown in FIGS. 1, 2, and 4 are examples, and any configuration can be adopted as long as the same functions as described above can be realized. Also,

[0030]

According to the clock control circuit according to the first aspect, another circuit can be operated even after the reset signal is input and until the phase synchronization by the PLL is completed. Can reduce the start-up time of the entire circuit that operates based on the clock output from.

According to the clock control circuit of the second aspect, even when the clock waveform is disturbed at the time of clock switching, malfunction of other circuits can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock control circuit according to the present invention.

FIG. 2 is a block diagram showing the inside of the clock control means of FIG. 1;

FIG. 3 is a time chart illustrating the operation of the clock control circuit of the present invention.

FIG. 4 is a block diagram showing a configuration of an LSI including a PLL circuit and peripheral circuits.

5 is a time chart showing an operation at the time of startup of the LSI of FIG. 4 when a conventional clock control circuit is used as a clock circuit.

6 is a time chart showing an operation at the time of starting the LSI of FIG. 4 when the clock control circuit of the present invention is used for the clock circuit.

FIG. 7 is a block diagram of a conventional clock control circuit using a PLL.

FIG. 8 is a block diagram showing the inside of the clock control means of FIG. 7;

FIG. 9 is a time chart of a conventional clock control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 PLL 12 Clock driver 13 Flip-flop 15 Selector 16 Clock control means 17 Loop buffer 21 Power counter 22 Comparator

Claims (2)

[Claims] 1. A PLL circuit for synchronizing the phases of an input clock and a clock to be output, a selector for selecting and outputting one of the input clock and a clock output from the PLL circuit, From the time the reset signal is input to the time the PLL circuit synchronizes the phase, the selected clock is selected and output. After the PLL circuit synchronizes the phase, the PLL circuit synchronizes the phase with the input clock. Clock control means for switching and controlling the selector so as to select and output a clock output from the circuit. 2. The apparatus according to claim 1, wherein said clock control means outputs a signal for stopping an operation of a circuit connected to an output terminal of said selector during a predetermined period before and after said selector switches output. 2. The clock control circuit according to claim 1.