JP2000077617A - Self-destructive semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably prevent juggling memory contents of a semiconductor integrated circuit. SOLUTION: An external connecting electrode pad and a power supply source connecting electrode pad are provided in an IC chip 12a and an electrode base 32, and the IC chip 12a is flip-chip-mounted on the electrode base 32. A plus polarity connection lead 28a is provided in a power supply source 6, which is mounted on a rear face of the IC chip 12a. A connection lead 28a is jointed to an electrode pad 64, and a metal thin film 29 is jointed to an electrode pad 64b, and an electric connection between the power supply source 6a and the electrode base 32 is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a physical security technique for falsifying memory contents of a semiconductor integrated circuit having a function of storing and processing important information with high confidentiality, and more particularly to an IC (Integrated Circuit) card. The present invention relates to a thin power supply source having a structure suitable for mounting on a thin semiconductor device such as the above, and a semiconductor device equipped with this power supply source.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (Integrated Circuit; I)
C) is conventionally provided in a semiconductor device as shown in FIG. 17 in order to analyze the function, operation method, circuit system, circuit pattern, stored data, etc. of the integrated circuit of the semiconductor device in which the device is formed. Electrode pad 7 for external connection (7
-1 to 7-8), there is a method of connecting an exploration power supply, supplying an electric signal, and measuring an input / output signal of a terminal signal with an IC tester or the like.

In order to analyze them, the circuit block configuration and the circuit pattern itself are observed using a shape recognition device such as an optical microscope from the surface of the semiconductor device, and the process proceeds one step further using an electron beam tester or the like. Electrode pad 7
There is a method of observing a potential signal that does not appear on the wiring inside the integrated circuit. Therefore, in the current IC card 13, it is possible to open and dissect the IC module 11, read out the information inside the IC chip 12, analyze the contents of the memory, and falsify it, which is a problem from the viewpoint of security. .

For example, a contact-type IC card currently used has the following configuration. That is, the card body 13 is made of a plastic material having the same size as a cash card or a credit card, and the IC module 11 has a built-in central processing unit and a memory. Electric signals are exchanged with the outside of the card through the upper external connection electrode pads 7. In this IC card, as a replacement for the conventional magnetic card, it is indispensable to accommodate the IC chip and the contact terminals in a thickness of 0.76 mm.

FIG. 17 shows a contact type I which is currently used.
3A and 3B show a schematic configuration example of the C card 13, in which FIG. 3A is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on the IC card 13, FIG. () Is a sectional view showing an example of mounting an IC module. As shown in FIG. 17C, an IC card 1 having a card thickness of 0.76 mm is used as a replacement for a conventional magnetic card.
3 includes an IC module 11 composed of an IC chip 12 and a contact electrode base, and a hot melt adhesive 34.
Powered by. The contact electrode base is formed by printing a copper foil of a contact pattern 35 corresponding to an electrode of the contact type IC card 13 on a glass epoxy substrate 36.

The IC module 11 has a glass epoxy substrate 36 on which a contact pattern 35 is formed,
The C chip 12 is die-bonded, the external connection electrode pad 7 and each of the contact patterns 35 are wire-bonded with gold wires 37, and then sealed with a mold resin 38.

[0007] As shown in FIG.
2 is a data memory (EEPROM or ferroelectric memory) which is composed of a nonvolatile memory capable of electrically writing and simultaneously erasing a plurality of bits of data, which stores particularly important information such as an encryption code and an authentication code. A peripheral circuit 15 including a voltage booster circuit for writing / erasing the same, a read-only program memory (configured with a ROM or the like) 16 storing a predetermined control program, A central processing unit (CPU) that reads a control program stored in the program memory 16, performs processing according to the control program, and controls operations such as calculation and rewriting of data stored in the nonvolatile memory.
17, a random access memory (RAM) 18 composed of a volatile memory for temporarily storing data, and a security authentication microprocessor (MPU) 19 are formed. A data bus and power supply electrode wiring (not shown) are provided around these components.

A reader / writer separate from the IC card 13
In order to supply an electric signal and a driving voltage from the writer to the IC chip 12, a total of eight external connection electrode pads 7 made of a metal such as aluminum are formed near two opposite ends of the IC chip 12. Have been. Therefore, the external connection electrode pads 7 on the IC chip 12 exchange electric signals with the outside of the chip via the contact patterns 35 on the card surface. Note that when reading or writing an electric signal from the outside, encryption processing of the electric signal is performed by the microprocessor 19 for authentication or encryption to enhance security.

The data memory 14 in the IC chip 12 stores important data such as a protocol required for communication, a number code for authentication, and a password required for security. Therefore, these codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, are prevented from being read by a third party from the viewpoint of preventing forgery or falsification of the IC card. There is a need.

However, in the semiconductor device as shown in FIG. 17, the circuit configuration blocks are started by optical observation from above, the functional element circuits, the data memory 14 and the program memory 16 and the authentication microprocessor 1
9 can be seen, and furthermore, the probing measurement using an electron beam can easily read the contents of the memory element, cause the authentication microprocessor 19 to run out of control and malfunction, thereby skipping the authentication process itself. Was possible.

In order to reduce the thickness of the IC module and prevent optical observation from above, the recent high-density mounting technology employs the IC chip 12 on the element surface side where the semiconductor integrated circuit is formed. A mounting substrate (electrode base) on which bump electrodes for obtaining electrical connection are formed, and the IC chip is turned over and contact electrodes for external connection are formed.
Flip-chip mounting for connecting to a semiconductor device is frequently employed.

FIG. 18A is a sectional view of an IC module on which flip-chip mounting has been performed, and FIG. 18B is a bottom view of the IC chip alone. The electrode base 32 is formed by printing a copper foil of a contact pattern 35 on a glass epoxy substrate. In the IC chip 12, the electrode pads of the electrode base 32 and the electrode pads 7-1 to 7-8 are connected via bumps 27 to the IC chip mounting surface of the electrode base 32 to which the anisotropic conductive adhesive resin 61 is applied. It will be mounted to be. The IC chip 12 mounted on the electrode substrate 32 has a molding resin 38.
Sealed. Thereby, the IC chip 12
The front, rear, left, right, top and bottom are the electrode base 32 and the mold resin
Protected from being easily removed.

However, a technique for observing a circuit near the front surface of the semiconductor substrate from the back surface of the semiconductor substrate on which the semiconductor integrated circuit is formed has been developed in response to a demand for a failure analysis technique or the like. In this method, the transparency of the semiconductor substrate is enhanced by using infrared light having a wavelength that is hardly absorbed by the semiconductor substrate as an observation light source, and a wiring pattern or the like mainly made of metal is observed from the back side of the semiconductor substrate. Thus, the pattern of the lowermost transistor and the wiring pattern of the first layer can be observed nondestructively.

In the flip chip mounting method, since the back surface of the chip is exposed to the outside, it is easy to observe the pattern from the back surface side of the IC chip 12 rather than the element surface side. Of course,
In the case of flip-chip mounting, a mold resin 38 for protecting the chip is coated on the back surface of the IC chip. However, since such a resin can be easily removed by using a chemical, it is difficult to prevent the pattern observation from the back side by the mold resin 38.

Therefore, as one method for solving the above problem, the present inventors have built in a thin power supply source and mounted the thin power supply source on the back surface of the IC chip, thereby performing optical observation from the back surface. A self-destructive semiconductor device for blocking is proposed (Japanese Patent Application No. 10-110527). FIG. 19 shows a basic circuit block diagram of the self-destructive semiconductor device. As shown in FIG. 17, the semiconductor integrated circuit 1 on the semiconductor substrate 9 has a data memory 14, a program memory 16, a central processing unit 17, a random access memory 18, an authentication Although a microprocessor 19 is formed, it is omitted here.

In this configuration, in addition to the above configuration, a destruction circuit for destructing memory information or a destruction circuit having a fuse / anti-fuse provided in a signal wiring path is added as the destruction circuit 2. On 9, a destruction capacitor 3, a control circuit or element 4, and a voltage change detection circuit 5 are formed. The terminal 10 whose terminal voltage is constantly monitored by the voltage change detection circuit 5
, A thin power supply source 6 is connected and arranged. As a power supply for driving the destruction circuit 2, electric charges accumulated in a large-capacity destruction capacitor 3 formed on the semiconductor substrate 9 are used. A power supply 6 is connected to the capacitor 3 via a control circuit or an element 4 in a normal operation state, and the output voltage of the power supply 6 is monitored by the voltage change detection circuit 5 as needed. I have.

FIGS. 20A and 20B show the basic structure of the self-destructive semiconductor device, wherein FIG. 20A is a plan view and FIG. 20B is a sectional view. The semiconductor substrate 9 on which the self-destructive IC chip 12 is formed has two electrode pads 10 for connecting to the power supply source 6 in addition to the eight electrode pads 7 necessary for the operation as the IC card 13. (Contact pairs) have been added. As shown in FIG. 20B, the thin power supply source 6 is formed by a laminated structure of a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector / terminal plate 25. The periphery is thermally sealed by a sealing material 26. Further, the outer dimensions of the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25 are designed differently so that even if the battery end face comes in contact with a conductive material such as a metal, a short circuit is prevented. . In addition, usually, the positive electrode current collector / terminal plate 21
Is smaller than the area of the negative electrode current collector / terminal plate 25. The connection lead 28 of the power supply source and the power supply connection electrode pad 10 are connected by a bump 27.

FIG. 20 shows a method for mounting the power supply source 6.
As shown in (a), it is also possible to arrange the IC chip 12 in parallel. However, when performing face-down flip-chip mounting in which the front side is shielded by an electrode substrate, in order to prevent back side observation, the back side is mounted via an adhesive film 20 as shown in FIG. Is preferred. Thereby, the back side can be optically shielded.

The connection lead 28 of the power supply 6 and the power supply connection electrode pad 10 on the semiconductor substrate 9 are
Although electrically connected by the bumps 27, it is also possible to electrically connect by spot welding by an ultrasonic wire bonding method or laser welding, that is, by locally heating to 250 ° C. for several seconds. According to the above configuration, when a third party removes the power supply source 6 for the purpose of falsification of the IC chip 12, the voltage change detection circuit 5 detects the voltage change, and the voltage change detection circuit 5 The power of the destruction capacitor 3 is applied to the destruction circuit 2 via the control circuit or the element 4 that has been turned on by the detection signal from. Therefore, the memory information of the semiconductor integrated circuit 1 to be falsified is destroyed.

However, in the case of the mounting method of the power supply source 6 as shown in FIG. 20, the two power supply sources of the self-destruction circuit are connected via the positive electrode lead and the negative electrode lead 28 of the thin power supply source 6. It is connected to the electrode pad 10. Therefore, in such a connection method, the power supply source connection electrode pad 10 and the connection lead 28 can be easily understood by a third party. The third party naturally connects another power supply that generates the same voltage as the power supply 6 in parallel with the power supply 6, and then optically shields the back surface of the IC chip 12. 6 will be removed. When dissected by such a method, the power supply source 6 is removed without a voltage change being detected by the voltage change detection circuit 5, so that
There is a problem that the self-destruction mechanism does not operate.

[0021]

As described above, FIG.
In the conventional self-destructive semiconductor device shown in FIG. 20, an IC is connected via a positive electrode lead and a negative electrode lead 28 of the power supply source 6.
It is connected to the power supply connection electrode pad 10 of the chip 12. However, in such a connection method, when another power supply that generates the same voltage as the power supply 6 is connected in parallel with the power supply 6 and the power supply 6 is removed, the self-destructive mechanism operates. Therefore, there is a problem that the analysis of the IC chip 12 cannot be stopped.

Therefore, when mounting the power supply source 6 on the back surface of the IC chip 12, it is necessary to make the connection lead 28 and the power supply source connection electrode pad 10 invisible from the outside. For this purpose, the connection lead 28 is not drawn out of the planes of the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25, and the power supply source connection electrode pad 1
It is necessary to make a connection with 0. However, the power supply source connection electrode pad 10 and the positive electrode current collector / terminal plate 21 or the negative electrode current collector / terminal plate 25 are connected by ultrasonic wire bonding (locally at 200 ° C. or higher) or solder. It is not possible. This is because the power supply source connection electrode pad 10 is on the element forming surface side of the IC chip 12 and not on the back surface. Further, even if the power supply connection electrode pad is formed on the back surface of the chip by any method, the solid electrolyte 23 made of the polymer in the current power supply 6 is decomposed when exposed to a high temperature exceeding 100 ° C. Therefore, a connection method in which the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25 constituting the power supply source 6 are directly heated cannot be adopted. Also, I
Due to the harsh operating environment of the C card, the connection method of non-heating processing by "insertion" or "sandwich"
Mechanical strength is weak, and electrical connection reliability cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and when heating an important part of a semiconductor integrated circuit optically with a power supply source, the power supply source is heated to deteriorate the battery life. The electrical connection between the power supply source and the semiconductor integrated circuit can be realized without any problem, and the electrical connection between the power supply source and the semiconductor integrated circuit can be optically shielded to prevent the memory contents of the semiconductor integrated circuit from being tampered with. It is an object of the present invention to provide a self-destructive semiconductor device that can be reliably prevented.

[0024]

According to the present invention, a semiconductor memory device and a central processing unit for processing data stored in the memory device are formed on the same semiconductor substrate. Having a semiconductor integrated circuit, a power supply source (6a) for self-destruction, an electrode substrate (32) for mounting a semiconductor substrate, and a metal thin film (29) for covering the power supply source. In the destructive semiconductor device, the semiconductor substrate (9a) has a first external connection terminal (7-1 to 7-8) and first and second power supply source connection terminals (10a , 10b), and the electrode base is provided with a second external connection terminal (62) on the mounting surface of the semiconductor substrate.
-1 to 62-8), third and fourth power supply source connection terminals (63a and 63b), and fifth and sixth power supply source connection terminals connected to the power supply source connection terminals ( 64a, 6
4b), in the semiconductor substrate, the element surface and the electrode base face each other, and the first and second external connection terminals are connected, and the first and second power supply source connection terminals and the second Third, the power supply source is mounted on the electrode base so as to be connected to the fourth power supply source connection terminal, and the power supply source is one of a positive electrode current collector and a negative electrode current collector. First current collector (2
The first current collector is mounted on the semiconductor substrate so as to face the back surface of the semiconductor substrate, and formed on the connection lead and the electrode base; Fifth connected power supply terminal (64a)
And a second current collector (2
5) A metal thin film (2)
9) is joined to a sixth power supply source connection terminal (64b) formed in a peripheral portion including two opposing sides of the electrode base, and an electrical connection is made between the power supply and the electrode base; The semiconductor substrate is fixed by sandwiching the semiconductor substrate between the power supply source and the electrode base. As described above, in the present invention, the semiconductor substrate (9a) is flip-chip mounted on the electrode base (32), and the power supply source (6a) is connected to the power supply source connection terminals (63a, 63b, 64a, 64b) of the electrode base. And the semiconductor integrated circuit (12a). This activates the self-destructive mechanism regardless of whether the metal thin film (29), the power supply (6a) or the electrode substrate (32) is removed. Further, not only the optical shielding by the power supply source (6a) but also the back surface of the semiconductor substrate can be optically shielded by the metal thin film (29) covering the entire power supply source (6a). Moreover, by sandwiching the connection lead (28a) of the power supply source between the semiconductor substrate and the power supply source mounted thereon, the formation position of the connection lead can be made optically invisible.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit in which a semiconductor memory device and a central processing unit for processing data stored in the memory device are formed on the same semiconductor substrate. Power supply source (6a, 6b) for performing the power supply, an electrode substrate (32b) for mounting the semiconductor substrate, and first and second metal thin films (29a, 29b) for covering the power supply source. A semiconductor substrate (9b) having first external connection terminals (7-1 to 7-8) and first, second, and third power supply sources on an element surface. Connection terminals (10a, 10b, 1
0c), wherein the electrode base is provided on the mounting surface of the semiconductor substrate with second external connection terminals (62-1 to 62-8),
Fifth and sixth power supply source connection terminals (63a, 63b,
63c), the seventh, eighth, and ninth power supply connection terminals (64a, 64) connected to the power supply connection terminals.
b, 64c), wherein the semiconductor substrate has the element surface and the electrode substrate facing each other, and the first and second external connection terminals are connected, and the first, second, and third power supply sources are provided. The power supply source is mounted on the electrode base so that the connection terminal is connected to the fourth, fifth, and sixth power supply source connection terminals. A power supply source (6a);
A second power supply (6b) for detecting a voltage change, wherein the first power supply is a first current collector (21) of one of a positive electrode current collector and a negative electrode current collector; The first current collector is mounted on the semiconductor substrate so as to face the back surface of the semiconductor substrate, and has a connection lead (28a) on the surface of the first power supply source. A seventh power supply source connection terminal (64a) formed on the electrode substrate is joined to the second power collector (2) of the first power supply source.
5) a first metal thin film (29a) covering the first power supply source and an eighth power supply source connection terminal formed on a peripheral portion including two opposing sides of the electrode base ( 64b)
And a first power supply source is electrically connected to the electrode base, and the second power supply source is the first current collector of the positive electrode current collector and the negative electrode current collector. The first metal thin film (2) with the third current collector (21) having the same polarity as
9a), the fourth current collector (25) of the second power supply and the first metal thin film (29a) are brought into contact with each other, and the fourth power supply of the second power supply is A second metal thin film (29b) covering the second power supply source on the current collector of No. 3 and a ninth power supply source connection formed in a peripheral portion including two opposing sides of the electrode base; And the second power supply source and the electrode base are electrically connected to each other, and the semiconductor substrate is fixed between the first and second power supply sources and the electrode base. It is something to do. As described above, in the present invention, the semiconductor substrate (9b) is flip-chip mounted on the electrode base (32b), and the second power supply source (6b) is connected to the power supply source connection terminal (6) of the electrode base.
3c, 63b, 64c, 64b) to the semiconductor integrated circuit (12b). This activates the self-destructive mechanism regardless of whether the second metal thin film (29b), the second power supply source (6b) or the electrode base (32b) is removed. Further, not only the optical shielding by the first power supply source (6a), but also the optical shielding by the coating metal thin film (29a) covering the entire first power supply source, and further the second shielding layer The power supply source (6b) is mounted, and the back surface of the semiconductor substrate can be optically shielded by the coating metal thin film (29b) that covers the entire second power supply source. Moreover, the connection lead (28a) of the first power supply source is sandwiched between the electrode base (32b) and the first power supply source mounted thereon, and is placed on the eighth power supply source connection terminal (64b). By joining the first metal thin film (29a) and joining the second metal thin film (29b) on the ninth power supply source connection terminal (64c), the connection lead of the first power supply source and The seventh to ninth power supply source connection terminals can be optically shielded.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate. Power supply source (6a, 6b) for performing the power supply, an electrode substrate (32c) for mounting a semiconductor substrate, and an insulating film (30a) having a metal layer formed on one surface and covering the power supply source And a metal thin film (30b) for covering a power supply source, wherein the semiconductor substrate (9c) has first external connection terminals (7-1 to 7-7) on an element surface. -8) and the first, second, third, and fourth power supply source connection terminals (10
c, 10d, 10a, 10b), and the electrode base is provided on the mounting surface of the semiconductor substrate with a second external connection terminal (62).
-1 to 62-8), fifth, sixth, seventh, and eighth power supply source connection terminals (63c, 63d, 63a, 63b), and a ninth power supply source connection terminal. Tenth, eleventh, and twelfth power supply connection terminals (64c, 64
d, 64a, 64b), wherein the semiconductor substrate has the element surface and the electrode substrate facing each other, and the first and second external connection terminals are connected to the semiconductor substrate. The power supply source is mounted on the electrode base such that the power supply source connection terminal of No. 4 is connected to the fifth, sixth, seventh, and eighth power supply source connection terminals. Comprises a first power supply source (6a) for self-destruction and a second power supply source (6b) for detecting a voltage change. The first power supply source includes a positive electrode current collector and a negative electrode current collector. One of the first current collectors (2
The first current collector is mounted on the semiconductor substrate so as to face the back surface of the semiconductor substrate, and has a connection lead (28a) on the surface of (1). A form in which the lead and the eleventh power supply source connection terminal (64a) formed on the electrode substrate are joined, and the metal layer contacts the second current collector (25) of the first power supply source. And a twelfth power supply source connection terminal (64b) formed on the periphery of the insulating film (30a) covering the first power supply source and including the two sides of the metal substrate and the electrode substrate facing each other. ) To perform electrical connection between the first power supply source and the electrode base, and the second power supply source is provided with a third current collector of one of the positive electrode current collector and the negative electrode current collector. Connection lead (28b) on the surface of the current collector (21), and the third current collector is an insulating filter. And a ninth power supply source connection terminal (64c) formed on the insulating film (30a) so as to face the second power supply source and the electrode base. ) And a metal thin film (30) covered on the fourth current collector (25) of the second power supply so as to cover the second power supply.
b) and a tenth power supply source connection terminal (64d) formed at a peripheral portion including two opposing sides of the electrode substrate, thereby electrically connecting the second power supply source to the electrode substrate. And fixing the semiconductor substrate so as to sandwich the semiconductor substrate between the first and second power supply sources and the electrode base.
As described above, in the present invention, the semiconductor substrate (9c) is flip-chip mounted on the electrode base (32c), and the second power supply source (6b) is connected to the power supply source connection terminal (63) of the electrode base.
c, 63d, 64c, 64d) to the semiconductor integrated circuit (12c). Thereby, the metal thin film (30
b), the second power supply source (6b) or the electrode substrate (3
Whichever of 2c) is removed, the self-destruct mechanism is activated. In addition, not only the optical shielding by the first power supply source (6a) but also the optical shielding by the insulating film (30a) covering the entire first power supply source, and the second power supply The back surface of the semiconductor substrate can be optically shielded by the metal thin film (30b) that mounts the power source (6b) and covers the entire second power source. Moreover, the connection lead (28a) of the first power supply source is sandwiched between the electrode base (32c) and the first power supply source mounted thereon, and the twelfth power supply source connection terminal (64
b) bonding a metal layer of an insulating film thereon, sandwiching the connection lead (28b) of the second power supply between the electrode base (32c) and the second power supply mounted thereon;
By joining the metal thin film (30b) on the tenth power supply source connection terminal (64d), the connection leads of the first and second power supply sources and the ninth to twelfth power supply source connection terminals Can be optically shielded.

According to a fourth aspect of the present invention, there is provided a destruction circuit (2) for destructing at least a part of the memory information of the semiconductor integrated circuit or performing a self-destruction by breaking at least a part of a signal wiring. This destruction circuit monitors a destruction capacitor (3) for storing charges for self-destruction and a voltage between the first power supply source connection terminal and the second power supply source connection terminal. A voltage change detection circuit (5) that outputs a detection signal according to the voltage drop;
During normal operation, the power supply source and the destruction capacitor are connected via the power supply source connection terminal. When a detection signal is output from the voltage change detection circuit, the connection is cut off and the destruction capacitor is connected to the destruction capacitor. Control circuits or elements (4, 4a) for connecting circuits are respectively provided on the semiconductor substrate. The destruction circuit (2) erases some data bits stored in the nonvolatile memory element and destroys the memory contents by applying the electric charge stored in the destruction capacitor to at least one word line. The destruction circuit (2) is formed by providing a fuse or an anti-fuse in a part of the signal wiring path of the semiconductor integrated circuit.
By applying the charge stored in the destruction capacitor to the fuse or antifuse, a part of the signal wiring path is broken. The voltage change detection circuit (5) includes a series connection of a first capacitor, a second capacitor, and a first resistor, and connects a connection terminal voltage applied to both ends to a connection point of the first and second capacitors. A voltage-dividing section for dividing the voltage from the voltage-dividing section, a field-effect transistor in which the divided voltage output of the voltage-dividing section is connected to a gate electrode and a destruction capacitor or a driving capacitor is connected to a source electrode, and And a voltage change detection unit comprising a second resistor connected to the drain electrode of the effect type transistor. In a steady state, a voltage at which the field effect transistor is turned off is output from the voltage division unit in a divided state. The voltage at which the field-effect transistor is turned on is divided from the voltage-divided output according to the voltage drop. The charge from Yapashita supplied to the second resistor, and outputs a detection signal in response to an increase in the second voltage across the resistor. When any of the metal thin film, the power supply source, and the electrode substrate is removed in order to falsify the memory contents of the semiconductor integrated circuit, a voltage drop is detected by the voltage change detection circuit (5). The control circuit or element (4) is turned on by this detection signal, and the destruction circuit (2) is connected to the destruction capacitor (3). Thereby, the electric charge accumulated in the capacitor (3) is applied to the destruction circuit (2). As a result, some wirings or essential memory data of the integrated circuit to be falsified are destroyed, so that falsification becomes impossible.

According to a fifth aspect of the present invention, the electrode substrate (32a, 32d) includes a first layer on which the external connection terminal and the power supply source connection terminal are formed, and a thickness of the semiconductor substrate. And a third layer having an opening having a size of the semiconductor substrate and a third layer having a thickness of the power supply source and having an opening having the size of the power supply source. Are sequentially laminated.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit block diagram of a self-destructive semiconductor device according to a first embodiment of the present invention. FIG. 2A is a plan view showing an example of the arrangement of the self-destructive semiconductor device in FIG.
2B is a sectional view taken along line AA of FIG. 2A, FIG. 2C is a sectional view taken along line BB of FIG. 2A, and FIG. 3A is a self-destructive semiconductor device of FIG. Bottom view of the IC chip alone, FIG. 3 (b)
FIG. 20 is a plan view of an electrode substrate of the self-destructive semiconductor device of FIG. 1, and the same reference numerals are given to components equivalent to those in FIGS. 17 to 20.

On the semiconductor substrate 9a, as a semiconductor integrated circuit 1 necessary for an original IC card function, a nonvolatile data memory (EEPROM or ferroelectric memory) storing particularly important information such as an encryption code and an authentication code is stored. , A peripheral circuit 15 such as a voltage booster circuit for writing and erasing the same, a read-only program memory (comprising a ROM or the like) 16, a central processing unit for performing calculations and controls Unit (CPU) 17, random access memory (RAM) 1 as a memory for temporary storage
8. Security authentication microprocessor (MP
U) 19 are formed.

In the present invention, in addition to the above structure, a destruction circuit for destructing memory information or a destruction circuit provided with a fuse / anti-fuse in a signal wiring path is added to the semiconductor substrate 9a as the destruction circuit 2. Further, a destruction capacitor 3, a control circuit or element 4 and a voltage change detection circuit 5 are added. Thus, a self-destructive IC chip 12a is formed.

In the present invention, electric charges stored in a large-capacity destruction capacitor 3 formed on a semiconductor substrate 9a are used as a power supply source for driving the destruction circuit 2. It is desirable that the destruction capacitor 3 has a structure in which a thermal oxide film (SiO ₂ ) formed on the semiconductor substrate 9a is used as an insulating film and has a large capacity. I mean,
In the case of a thermal oxide film, characteristics such as a very small leak current can be used, and a large amount of electric charges can be stored in the capacitor 3 by the thin power supply source 6a having a small energy density.
Moreover, energy consumption due to leakage can be reduced.

FIG. 4A is a plan view of the power supply source 6a, FIG. 4B is a cross-sectional view taken along the line AA of FIG. 4A, and FIG. It is a B sectional view. As shown in FIG. 4, a thin power supply source 6 a for accumulating charges in the destruction capacitor 3 includes a positive electrode current collector / terminal plate 21, a positive electrode 22,
It is formed by a laminated structure of a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector / terminal plate 25, and the periphery thereof is thermally sealed by a sealing material 26.

In this power supply source 6a, there is no connection lead 28 extending outside the plane of the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25, and the positive electrode current collector / terminal plate is not provided. 20 is different from the case of FIG. 20 in that a connection lead 28a made of a metal foil or a metal thin film is joined to the connection 21.

As can be seen from FIG. 4, the size of the positive electrode current collector / terminal plate 21 is made smaller in the vertical and horizontal dimensions than the negative electrode current collector / terminal plate 25, and the end face of the power supply source 6a is made of a metal sheet. It is devised so that short circuit accidents, etc., do not occur even if they come into contact with the device. In this embodiment, a positive electrode current collector and terminal plate (first current collector) whose area is reduced to prevent short circuit
A connection lead 28a is provided on the 21 side.

The connection lead 28a can be pulled out from an arbitrary position on the positive electrode current collector / terminal plate 21. However, it is necessary to take the position so as to match the position of a power supply source connection electrode pad 64a described later on the electrode base 32 on which the IC chip 12a and the power supply source 6a are mounted.

Further, as described later, by sandwiching the connection lead 28a between the electrode base 32 and the power supply source 6a mounted thereon, the formation position of the connection lead 28a is made optically invisible. This connection lead 28
Horizontal direction of a (direction parallel to the paper surface in FIG. 4A)
Must not protrude out of the plane of the positive electrode current collector / terminal plate 21.

The power supply source 6a supplies power to the destruction circuit 2, the destruction capacitor 3, the control circuit or element 4, and the voltage change detection circuit 5, and the semiconductor integrated circuit 1 excluding the destruction circuit 2 Has an external connection electrode pad 7-1
Power is supplied from outside through a power supply terminal among the power supply terminals 7 to 8.

With respect to the power supply source 6a as described above, I
The semiconductor substrate 9a on which the C chip 12a is formed has a structure shown in FIG.
As shown in (a), in addition to eight external connection electrode pads 7-1 to 7-8 required for operation as an IC card, an electrode pad 10a for connection to the positive electrode of the power supply source 6a
Are added, and a plurality of electrode pads 10b for connecting to the negative electrode of the power supply source 6a are added in two rows facing each other.

The power supply source connection electrode pad 10b
Are formed in a row because the IC chip 12a must be firmly fixed when flip-chip mounted on the electrode base 32. Therefore, only one of the electrode pads 10b formed on the IC chip 12a needs to be a true electrode pad connected to the voltage change detection circuit 5, the destruction capacitor 3, and the destruction circuit 2 by wiring. May be a dummy pad. This allows
It is possible to make it difficult for a third party aiming at falsification of the IC chip 12a to find out the true electrode pad.

On the other hand, an electrode substrate 3 made of glass epoxy
As shown in FIG. 3B, on the IC chip mounting surface of No. 2,
External connection electrode pads 7-1 to 7- of IC chip 12a
8 corresponding to the external connection electrode pads 62-1 to 62-8
Are formed, a power supply connection electrode pad 63a corresponding to the power supply connection electrode pad 10a is formed, and the power supply connection electrode pad 63b corresponding to the power supply connection electrode pad 10b faces 2 A plurality of power supply connection electrode pads 64a for connecting to the positive electrode of the power supply source 6a are formed, and a plurality of power supply connection electrode electrodes for connecting to the negative electrode of the power supply source 6a. A plurality of pads 64b are formed in two opposing rows.

On the surface of the electrode base 32 facing the IC chip mounting surface, eight contact patterns 35 corresponding to the electrode terminals of the IC card are formed. The electrode pads 62-1 to 62-8 are respectively connected to the corresponding contact patterns 35 by through holes or the like. The electrode pad 63a is wired and connected to the electrode pad 64a, and each of the electrode pads 63b is wired and connected to the corresponding electrode pad 64b.

The voltage change detection circuit 5 monitors the voltage between the power supply connection electrode pads 10a and 10b, that is, the output voltage of the power supply 6a as needed. The control circuit or the element 4 has a switch that uses a detection signal output from the voltage change detection circuit 5 as a control input. This switch operates in a normal operation when there is no detection signal output from the voltage change detection circuit 5. In the state, the NC side shown in FIG. 1 is selected.

Thus, in the normal operation state, the positive electrode of the power supply source 6a is connected to the connection lead 28a and the electrode base 32.
Are connected to one end of the destruction capacitor 3 via the power supply connection electrode pads 64a and 63a, the power supply connection electrode pad 10a, and the switch of the control circuit or the element 4. Further, the negative electrode of the power supply source 6a includes a metal thin film 29 for coating described later, power supply connection electrode pads 64b and 63b of the electrode base 32, and a power supply connection electrode pad 10b.
Is connected to the other end of the destruction capacitor 3.

Here, a method for mounting the self-destructive semiconductor device of the present embodiment will be described. First, bumps 27 made of gold (Au) or the like are formed on the external connection electrode pads 7-1 to 7-8 and the power supply connection electrode pads 10a and 10b on the IC chip 12a. To perform flip chip mounting, an anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of the electrode base 32. Anisotropic conductive adhesive resin 61
Is about 1/2 to 1/3 of the volume of the IC chip 12a. This amount is preferably such that the resin 61 is blown up on the chip side surface in the final mounting shape.

When the area of the IC chip 12a is small, it may be applied to the element surface of the IC chip 12a.
Next, the element surface of the IC chip 12a (the paper surface of FIG. 3A) and the IC chip mounting surface of the electrode base 32 (the paper surface of FIG. 3B) face each other, and the external connection electrode pads 7 of the IC chip 12a are provided. -1 to 7-8 and the external connection electrode pads 62-1 to 62-8 of the electrode base 32 are connected, the power supply connection electrode pad 10a and the power supply connection electrode pad 63a are connected, Power supply source connection electrode pad 10
Positioning of each electrode pad is performed so that b and the power supply source connection electrode pad 63b are connected, and pressure is applied from the back surface of the IC chip 12a.

Pressing has two purposes. The first object is to align the element surface of the IC chip 12a and the IC chip mounting surface of the electrode base 32, and to crush the bump 27 by applying pressure (plastic deformation), thereby absorbing a variation in the height of the bump 27. That is.

The second object is to set a gap between the electrode pads 62-1 to 62-8 formed on the electrode base 32 and the bumps 27 formed on the electrode pads 7-1 to 7-8 of the IC chip 12a. Extruding the anisotropic conductive adhesive resin 61 existing between the electrode pad 63a and the bump 27 formed on the electrode pad 10a and between the electrode pad 63b and the bump 27 formed on the electrode pad 10b; That is, each electrode pad is electrically connected via the bump 27.

Next, with the above-mentioned pressure applied,
The anisotropic conductive adhesive resin 61 is cured. The anisotropic conductive adhesive resin 61 causes the electrode pads 62-1 to 62-8, 63a, 6a formed on the electrode base 32 to contract due to shrinkage during curing.
3b and the electrode pads 7-1 to 7- of the IC chip 12a.
The bumps 27 formed on 8, 10a and 10b are brought into pressure contact with each other. For this purpose, the anisotropic conductive adhesive resin 61 needs to have such characteristics as to satisfy the following condition.

Α, β>ω> ρ (1) where α is the IC chip 12 a and the anisotropic conductive adhesive resin 6.
1, β is the adhesive force between the electrode substrate 32 and the anisotropic conductive adhesive resin 61, ω is the shrinkage of the anisotropic conductive adhesive resin 61 during curing, and ρ is the anisotropic conductive adhesive resin 61 itself. Represents the thermal stress of

When the anisotropic conductive adhesive resin 61 has photocurability, the resin 61 is cured by irradiating ultraviolet rays.
When the photo-curable resin 61 is used, since the electrode base 32 is opaque, ultraviolet rays are irradiated from the side surface of the IC chip 12a to be cured from the resin 61 on the chip side surface, and the resin 61 in the unexposed area is naturally cured. (Curing at room temperature).

If the photo-curing anisotropic conductive adhesive resin 61 is used, it is not necessary to apply heat during connection to perform thermosetting.
It is not necessary to apply excessive thermal stress to the IC chip 12a and the electrode base 32. When the anisotropic conductive adhesive resin 61 has thermosetting properties, the resin 61 is cured by heating.

When the curing of the anisotropic conductive adhesive resin 61 is completed, the pressurization is stopped. Thus, the electrical connection between the external connection electrode pads 7-1 to 7-8 of the IC chip 12a and the contact pattern 35, the power supply connection electrode pads 10a and 10b of the IC chip 12a, and the power supply connection electrode The electrical connection with the pads 63a and 63b and the mechanical holding of the IC chip 12a by the electrode base 32 are completed.

Next, the power supply source connection electrode pad 64a on the electrode base 32 and the connection lead 28a of the power supply source 6a are electrically connected by spot welding such as ultrasonic wire bonding or laser welding. . In order to realize such an electrical connection, the power supply source connection electrode pad 64a and the connection lead 28a are placed with the back surface of the IC chip 12a facing the positive electrode current collector / terminal plate 21 of the power supply source 6a. Then, by irradiating the contact point with a laser beam, the power supply connection electrode pad 64a and the connection lead 28a are spot-welded.

As described above, since the connection lead 28a is made of a metal foil or a metal thin film, it has flexibility. Therefore, the electrode pad 64a and the connection lead 28a can be brought into contact with the power supply source 6a slightly inclined from the horizontal so that the power supply source connection electrode pad 64a can be seen, and this contact point is visible. Irradiation may be performed in a proper state.

At this time, if the connection lead 28a is pressed from above with a metal rod serving as a heat sink and pressed against the electrode pad 64a only during the spot welding, high heat during spot welding is radiated from the heat sink and the power is It can be prevented from conducting to the supply source 6a. As a result, the conventional problem that the solid electrolyte 23 in the power supply source 6a causes a chemical reaction due to the heating during the connection processing and the battery life or the like is deteriorated can be avoided. After spot welding the power supply connection electrode pad 64a and the connection lead 28a, the power supply 6a is mounted on the back surface of the IC chip 12a by the adhesive film 20.

Next, the power supply source connection electrode pad 64b on the electrode base 32 and the negative electrode current collector / terminal plate 25 of the power supply source 6a are electrically connected. In order to realize such an electrical connection, first, it is formed on the electrode base 32,
Power supply source connection electrode pads 6 arranged in two rows
4b, the upper or lower row of electrode pads 64b and the coating metal thin film 29 made of aluminum foil or the like.
Are contacted with each other, and a laser beam is applied to these contact points to spot-weld one row of the electrode pads 64b and one end of the coating metal thin film 29.

Subsequently, the coating metal thin film 29 is stretched so as to cover the power supply source 6a, and the other end of the coating metal thin film 29 is brought into contact with the other row of the electrode pads 64b. Is irradiated with a laser beam, and the other row of the electrode pads 64b and the other end of the coating metal thin film 29 are spot-welded.

Thus, the coating metal thin film 29 is fixed to the electrode base 32. Since the negative electrode current collector / terminal plate 25 of the power supply source 6a is in contact with the coating metal thin film 29 over the entire area thereof, the power supply source connection electrode pad 64b and the negative electrode collector are connected via the coating metal thin film 29. The electric / cum-terminal plate 25 is electrically connected. Finally, the mounted IC module is sealed with a mold resin, and mounted on a plastic case of the IC card with a hot melt adhesive.

With the above mounting structure,
The electrical connection between the IC chip 12a and the power supply source 6a can be reliably performed, and mechanically weak and reliable, which is a concern in a conventional non-heating processing connection method by "insertion" or "sandwich". Low electrical connections can be avoided.

In addition to the optical shielding by the power supply source 6a, the back surface of the IC chip 12a can be optically shielded by the coating metal thin film 29 covering the entire power supply source 6a. In addition, the power supply source connection electrode pads 64a and 64b are optically shielded by the coating metal thin film 29.

Thus, a third party for the purpose of falsifying the IC chip 12a connects another power supply source that generates the same voltage as the power supply source 6a in parallel with the power supply source 6a.
It is possible to prevent the power supply source 6a for shielding from being removed from the IC chip 12a.

Next, a self-destructive mechanism of the self-destructive semiconductor device of the present embodiment will be described. A third party aiming at falsification of the IC chip 12a first removes the IC module from the plastic case, and then removes the mold resin using a chemical. And IC chip 1
The back surface of the IC chip 12a cannot be observed unless the power supply source 6a is removed, and the element surface of the IC chip 12a is not removed unless the electrode base 32 is removed. You can't even observe.

In order to remove the power supply source 6a, the metal thin film 29 for coating is completely removed from the electrode base 32 or
At least part of it must be removed. At this time,
The coating metal thin film 29 is completely removed from the electrode substrate 32 (or the connection between the coating metal thin film 29 and the original electrode pad 64b other than the dummy pad is removed), or the connection lead 28a is connected to the power supply source. When the connection with the electrode pad 64a is removed, the voltage change is detected by the voltage change detection circuit 5.

When the voltage change detection circuit 5 detects a voltage change and outputs a detection signal, the detection signal is given to a control circuit or a control input of a switch in the element 4. Thereby, the switch in the control circuit or the element 4 is switched to the NO side in FIG. 1 that connects the destruction capacitor 3 and the destruction circuit 2, and the power of the destruction capacitor 3 is applied to the destruction circuit 2. Thus, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1 is destroyed.

On the other hand, the power supply source 6a is connected to the electrode base 63 via the electrode pads 63a, 63b, 64a, and 64b.
Since it is connected to the C chip 12a, when the electrode substrate 32 is removed, it becomes electrically the same as when the power supply source 6a is removed, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1 is destroyed. You. That is, in the present embodiment, the self-destruction mechanism is activated regardless of whether the power supply source 6a or the electrode base 32 is removed.

[Second Embodiment] FIG. 5A is a sectional view of a self-destructive semiconductor device according to a second embodiment of the present invention, and FIG. 5B is a diagram showing an IC chip mounted on an electrode substrate. FIG. 5 is a diagram showing a state of flip-chip mounting, in which the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals. FIG.
FIG. 5A shows a self-destructive semiconductor device whose mounting has been completed.
The cross section is taken along the line AA shown in FIG.

In the mounting structure shown in the first embodiment, the IC
The size of the thin power supply 6a mounted on the back surface of the chip 12a needs to be substantially equal to the size of the IC chip 12a. In the case of such a mounting method, although the size of the power supply source 6a can be expanded up to the size of the electrode base 32, the thickness of the IC chip 12a mounted on the electrode base 32 is large. Electrode substrate 3 to protrude
If the size of the IC chip 12a sandwiched between the power supply source 2 and the power supply source 6a is small, local stress is generated at the protruding portion, and uneven stress is generated inside the power supply source 6a.

The power supply source 6a generates an electromotive force by moving the positive electrode active material and the negative electrode active material in the solid electrolyte. And the battery life is degraded. On the other hand, since the power capacity of the power supply source 6a is proportional to the area of the planar shape, when the power capacity is insufficient, it is necessary to increase the capacity.

Therefore, in the present embodiment, as shown in FIG. 5A, the power supply source 6a and the electrode base 32a on which the IC chip 12a is mounted are attached to the lower surface of the contact pattern 3a.
5-1 to 35-8 are formed, and the electrode pads 62-
A first layer on which 1 to 62-8, 63a, and 63b are formed;
A hole having the same thickness as the IC chip 12a and the size of the IC chip 12a is formed.
a having a thickness equal to that of the power supply source 6a and a size of the power supply source 6a;
It has a structure in which three layers of a third layer in which the electrode pad 64b is formed on the upper surface are stacked.

Also in this embodiment, the circuit block configuration of the self-destructive semiconductor device is the same as that of FIG. Electrode pads 62-1 to 62-8 corresponding to the electrode pads 7-1 to 7-8 of the IC chip 12a are formed on the IC chip mounting surface of the first layer of the electrode base 32a, and correspond to the electrode pads 10a. The electrode pad 63a is formed, and the electrode pad 10 is formed.
A plurality of electrode pads 63b corresponding to “b” are formed in two opposing rows.

The electrode pads 7-1 to 7-8 are respectively provided with contact patterns 35-1 to 35-3 by through holes or the like.
5-8. An electrode pad 64a for connecting to the positive electrode of the power supply source 6a is formed on the upper surface of the second layer of the electrode base 32a. The electrode pad 63a is connected to the electrode pad 64a via a printed wiring, a through hole, and the like. On the upper surface of the third layer of the electrode substrate 32a,
Electrode pad 64 for connecting to the negative electrode of power supply source 6a
b are formed in two opposing rows. Each of the electrode pads 63b is connected to the electrode pad 64b via a printed wiring, a through hole, or the like.

The IC chip 1 is mounted on the electrode base 32a.
2a is flip-chip mounted. The procedure is the same as in the first embodiment, and will not be described in detail. Subsequently, the power supply source connection electrode pad 64a on the electrode base 32a and the connection lead 28a of the power supply source 6a are electrically connected by spot welding such as an ultrasonic wire bonding method or a laser welding method.

After the power supply source connection electrode pad 64a and the connection lead 28a are spot-welded, the power supply source 6a
On the back surface of the IC chip 12a and the second
It is mounted on the layer with an adhesive film 20. Next, the power supply source connection electrode pad 64b on the electrode base 32a and the negative electrode current collector / terminal plate 25 of the power supply source 6a are electrically connected. In order to realize such an electrical connection, first, of the power supply source connection electrode pads 64b formed on the third layer of the electrode base 32a and arranged in two rows, the upper or lower side is used. The electrode pad 64b of one row is brought into contact with one end of the coating metal thin film 29 made of an aluminum foil or the like, and a laser beam is irradiated to these contact points to form one row of the electrode pad 64b with the coating. Metal thin film 2
9 is spot-welded to one end.

Subsequently, a coating metal thin film 29 is stretched so as to cover the power supply source 6a, and the other end of the coating metal thin film 29 is brought into contact with the other row of the electrode pads 64b. Is irradiated with a laser beam, and the other row of the electrode pads 64b and the other end of the coating metal thin film 29 are spot-welded.

In the present embodiment, the portion of the power supply source 6a protruding from the IC chip 12a is supported by the second layer having the same thickness as the IC chip 12a.
The stress corresponding to the thickness of 2a is not concentrated on a part of the power supply source 6a, and the battery life is not deteriorated. Further, the size of the power supply source 6a can be much larger than that of the IC chip 12a within a range allowed by the electrode base 32a, so that the power capacity can be increased.

Here, the physical thickness of the above structure will be discussed. The first layer of the electrode base 32a has contact patterns 35-1 to 35-8 made of a copper foil or the like having a thickness of 35 μm.
Is made of a 120 μm thick glass epoxy substrate formed on the lower surface. On the upper surface of the first layer, electrode pads and the like for making electrical connection with the IC chip 12a are formed together with wiring patterns, and each is made of a metal having a thickness of 1 μm or less.

Next, the second layer of the electrode substrate 32a must have a thickness obtained by adding the thickness of the IC chip 12a to about 50 to 100 μm and the height of the bump to 50 to 80 μm. The minimum is about 100 μm. Since the third layer of the electrode substrate 32a has a thickness equivalent to the thickness of the power supply source 6a, when the current lithium primary battery is used for the power supply source 6a, the thickness is 100 to 300 μm.

Therefore, the total thickness of the electrode substrate 32a composed of the above three layers is 635 μm (= 3
5 + 120 + 180 + 300 μm), lower limit 355 μm
(= 35 + 120 + 100 + 100 μm), and it is sufficiently possible to put the IC module in an IC card having a thickness of 0.76 mm.

[Embodiment 3] The battery capacity of the current 0.1 mm-thick lithium primary battery is about 1.5 mAh / cm ^2.
This is used as the first and second power supply sources 6a of the embodiment, and the area of the power supply source 6a is
When the size of the chip 12a is set to about the size (for example, 8 × 8 mm), it becomes difficult to supply all the driving power of the voltage change detection circuit 5, the control circuit, the element 4, and the destruction circuit 2 by one power supply source 6a. That is, the voltage change detection circuit 5
Must constantly monitor an attack by a third party, and the power supply source 6a must supply power for that purpose. Moreover, once an attack by a third party is detected, the destruction circuit 2 must be driven to erase the memory information.

As described above, the circuit configuration of the self-destructive semiconductor device shown in FIG. 1 requires a considerably large power capacity for the power supply source 6a, and has a chip size of about 5 × 5 to 8 × 8 mm and a thin power supply. There was a problem that the demand for a supply source could not be realized. Therefore, in the present embodiment, a self-destruction function of erasing information in the data memory when monitoring voltage fluctuation over a long period of time and detecting removal of the shielding power supply by a third party is provided by one system. Instead of being driven by a power supply source, the circuit is divided into two circuits to provide a margin for required power.

FIG. 6 is a circuit block diagram of a self-destructive semiconductor device according to a third embodiment of the present invention, and FIG.
FIG. 7B is a plan view showing an example of the arrangement configuration of the self-destructive semiconductor device of FIG. 6, FIG. 7B is a sectional view taken along the line AA of FIG.
7C is a sectional view taken along line BB of FIG. 7A, FIG. 8A is a bottom view of a single IC chip of the self-destructive semiconductor device of FIG.
FIG. 8B is a plan view of the electrode substrate of the self-destructive semiconductor device of FIG. 6, and the same components as those of FIGS. 1 to 4 are denoted by the same reference numerals.

In the present embodiment, the semiconductor substrate 9b
On the upper side, a data memory 14, a peripheral circuit 15, a program memory 16, a central processing unit 17, a random access memory 18, and a security authentication microprocessor 19 are formed as the semiconductor integrated circuit 1 necessary for the original IC card function. Further, a destruction circuit 2, a destruction capacitor 3, a control circuit or element 4a, and a voltage change detection circuit 5 are added on the semiconductor substrate 9b.

In this embodiment, two power supply sources, ie, a first power supply source 6a for destruction and a second power supply source 6b for monitoring are provided, but the power supply sources 6a and 6b Is similar to that of the first embodiment. The power supply source 6
a supplies power to the destruction circuit 2 and the destruction capacitor 3, and a power supply source 6 b supplies power to the control circuit or the element 4 a and the voltage change detection circuit 5. Power is supplied to the integrated circuit 1 from the outside via the power supply terminals of the external connection electrode pads 7-1 to 7-8.

For the power supply sources 6a and 6b, the semiconductor substrate 9b on which the IC chip 12b is formed has a structure shown in FIG.
As shown in FIG. 7, in addition to the eight external connection electrode pads 7-1 to 7-8 required for operation as an IC card, an electrode pad 10a for connection to the positive electrode of the first power supply source 6a
Is added, and a plurality of electrode pads 10c for connecting to the positive electrode of the second power supply source 6b are added in two opposing rows, and further, for connecting to the negative electrodes of the power supply sources 6a and 6b. A plurality of electrode pads 10b are added in two opposing rows.

The power supply source connection electrode pad 10
The b and 10c are formed in a row because the IC chip 12
This is because, when flip-chip b is mounted on the electrode base 32b by flip-chip mounting, it is necessary to strengthen the fixing. Therefore, the electrode pads 10b formed on the IC chip 12b
Only one of them may be a true electrode pad connected to the voltage change detection circuit 5, the destruction capacitor 3, and the destruction circuit 2, and the other may be a dummy pad.

Similarly, any one of the electrode pads 10c
Only one may be a true electrode pad connected to the voltage change detection circuit 5 by wiring, and the other may be a dummy pad. This makes it difficult for a third party aiming at falsification of the IC chip 12b to find out the true electrode pad.

On the other hand, the electrode substrate 3 made of glass epoxy
As shown in FIG. 8B, electrode pads 62-1 to 62-8 corresponding to the electrode pads 7-1 to 7-8 of the IC chip 12b are formed on the IC chip mounting surface 2b. An electrode pad 63a corresponding to 10a is formed,
A plurality of electrode pads 63b corresponding to the electrode pads 10b are formed in two rows facing each other, and a plurality of electrode pads 63c corresponding to the electrode pads 10c are formed in two rows facing each other. An electrode pad 64a for connecting to the positive electrode is formed, and a plurality of electrode pads 64c for connecting to the positive electrode of the power supply source 6b are formed in two opposing rows and connected to the negative electrodes of the power supply sources 6a and 6b. Electrode pads 64b are formed in two rows facing each other.

Further, eight contact patterns 35 are formed on the surface of the electrode base 32b facing the IC chip mounting surface. The electrode pads 62-1 to 62-8 are respectively connected to the corresponding contact patterns 35 by through holes or the like. The electrode pad 63a is an electrode pad 64
a, and each of the electrode pads 63b is wire-connected to the corresponding electrode pad 64b, and each of the electrode pads 63c is wire-connected to the corresponding electrode pad 64c.

The voltage change detecting circuit 5 monitors the voltage between the power supply connection electrode pads 10c and 10b, that is, the output voltage of the second power supply 6b as needed. The control circuit or the element 4a has a switch that receives a detection signal output from the voltage change detection circuit 5 as a control input. This switch operates in a normal operation without the detection signal output from the voltage change detection circuit 5. It is off in the state.

The positive electrode of the power supply source 6a is connected to the connection lead 28
a, power supply source connection electrode pad 64 of electrode base 32b
a, 63a and one end of the destruction capacitor 3 via the power supply source connection electrode pad 10a.
The positive electrode b receives the voltage change detection circuit 5 via the coating metal thin film 29b, the power supply connection electrode pads 64c and 63c of the electrode base 32b, and the power supply connection electrode pad 10c.
Is connected to The negative electrodes of the power supply sources 6a and 6b are connected to the metal thin film 29a for covering, the power supply connection electrode pads 64b and 63b of the electrode base 32b, and the power supply source connection electrode pad 10b and other components of the destruction capacitor 3. Connected to the end.

Here, a method for mounting the self-destructive semiconductor device of the present embodiment will be described. First, bumps 27 made of gold (Au) or the like are formed on the external connection electrode pads 7-1 to 7-8 and the power supply connection electrode pads 10a, 10b, and 10c on the IC chip 12b.

In order to perform flip chip mounting, as in the first embodiment, an anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of the electrode substrate 32b or the IC chip 12b. Next, the element surface of the IC chip 12b (the paper surface of FIG. 8A) and the IC chip mounting surface of the electrode base 32b (the paper surface of FIG. 8B) face each other, and the IC chip 1
The electrode pads 7-1 to 7-8 of the electrode base 2b and the electrode pads 62-1 to 62-8 of the electrode base 32b are connected, the electrode pad 10a and the electrode pad 63a are connected, and the electrode pad 1
0b and the electrode pad 63b are connected, and the electrode pad 10
Positioning of each electrode pad is performed so that c and the electrode pad 63c are connected, and pressure is applied from the back surface of the IC chip 12b.

In the state where such pressure is applied, the anisotropic conductive adhesive resin 61 is cured as in the first embodiment. Next, the power supply source connection electrode pad 64a on the electrode base 32b and the connection lead 28a of the power supply source 6a are electrically connected by spot welding such as ultrasonic wire bonding or laser welding.

In order to realize such electrical connection, the back surface of the IC chip 12b and the positive electrode current collector / terminal plate 21 of the power supply source 6a face each other, and the power supply source connection electrode pad 64a is connected to the power supply source connection electrode pad 64a. After contacting the connection lead 28a and irradiating the contact point with laser light,
Power supply connection electrode pad 64a and connection lead 28a
And spot welding.

As in the first embodiment, if a metal rod serving as a heat sink is used, high heat during spot welding can be radiated from the heat sink and not conducted to the power supply source 6a. Power supply source connection electrode pad 6
After spot welding the connection lead 4a and the connection lead 28a, the power supply source 6a is mounted on the back surface of the IC chip 12b by the adhesive film 20.

When two or more power supply sources 6a need to be connected in series, the required number of power supply sources 6a may be stacked as shown in FIG. In this case, the negative electrode current collector / terminal plate 25 of the lower power supply source 6a may be brought into contact with the positive electrode current collector / terminal plate 21 of the power supply source 6a stacked thereon.

Next, the negative electrode current collector / terminal plate 25 of the uppermost power supply source 6a is electrically connected to the power supply source connection electrode pad 64b on the electrode base 32b. In order to realize such electrical connection, first, of the power supply source connection electrode pads 64b formed on the electrode base 32b and arranged in two rows, After the electrode pad 64b is brought into contact with one end of the coating metal thin film 29a made of aluminum foil or the like, these contact points are irradiated with a laser beam, so that one row of the electrode pad 64b and the coating metal thin film 29a Spot welding with one end.

Subsequently, the coating metal thin film 29a is stretched so as to cover the power supply source 6a, and the other end of the coating metal thin film 29a is brought into contact with the other row of the electrode pads 64b.
These contact points are irradiated with laser light, and the electrode pads 64 are irradiated.
b is spot-welded to the other end of the coating metal thin film 29a.

Thus, the coating metal thin film 29a is fixed to the electrode base 32b. Since the negative electrode current collector / terminal plate 25 of the uppermost power supply source 6a is in contact with the coating metal thin film 29a over the entire area thereof, the coating metal thin film 29a
The power supply source connection electrode pad 64b and the negative electrode current collector / terminal plate 25 of the power supply source 6a are electrically connected through the power supply.

Next, a power supply source connection electrode pad 64c on the electrode base 32b and a positive electrode connection lead (not shown) joined to the positive electrode current collector / terminal plate 21 of the second power supply source 6b. And the power supply source connection electrode pad 64b is electrically connected to the negative electrode current collector / terminal plate 25 of the power supply source 6b.

In order to realize this electrical connection, first, the metal thin film 29a for covering and the negative electrode current collector / terminal plate 25 of the power supply source 6b are brought into contact with each other, that is, the positive electrode current collector / terminal plate 21 The power supply source 6b is placed on the metal thin film for coating 29a in such a manner that faces upward. Subsequently, 2 is placed on the electrode base 32b.
Power supply source connection electrode pads 64 arranged in two rows
c, one of the left or right electrode pad 6
4c and a coating metal thin film 29b made of aluminum foil or the like
And then irradiating a laser to these contact points to spot weld one row of the electrode pads 64c and one end of the coating metal thin film 29b.

Next, the power supply source 6b is formed by spot welding such as ultrasonic wire bonding or laser welding.
Connection lead (not shown) for the positive electrode and the metal thin film 29 for coating
b. In this case, the coating metal thin film 29b
Can serve as a heat sink to avoid heating the power supply source 6b.

Then, the coating metal thin film 29b is stretched so as to cover the power supply source 6b, and the other end of the coating metal thin film 29b is brought into contact with the other row of the electrode pads 64c.
A laser is irradiated to these contact points, and the electrode pads 64c
Is spot-welded to the other end of the coating metal thin film 29b.

Thus, the coating metal thin film 29b is fixed to the electrode base 32b, and the power supply source connection electrode pad 64c and the connection lead of the power supply source 6b are electrically connected via the coating metal thin film 29b. At the same time, the power supply source connection electrode pad 64b and the negative electrode current collector / terminal plate 25 of the power supply source 6b are electrically connected via the coating metal thin film 29a.

By adopting the above mounting structure,
The electrical connection between the IC chip 12b and the power supply sources 6a and 6b can be reliably performed, and is mechanically weak and reliable, which is a concern in the conventional connection method of non-heating processing by "insertion" or "sandwich". Poor electrical connection can be avoided.

In addition to the optical shielding by the power supply sources 6a and 6b, the back surface of the IC chip 12b can be optically shielded by the coating metal thin films 29a and 29b. Moreover, the power supply source connection electrode pads 64a, 64b, 64c are optically shielded by the coating metal thin films 29a, 29b.

Thus, a third party aiming at falsification of the IC chip 12b can use another power supply source that generates the same voltage as the power supply source 6a or 6b.
To prevent the power supply sources 6a and 6b for shielding from being removed from the IC chip 12b.

Next, a self-destruction mechanism of the self-destruction type semiconductor device of the present embodiment will be described. A third party aiming at falsification of the IC chip 12b first removes the IC module from the plastic case, and then removes the mold resin using a chemical. And IC chip 1
2b, the metal thin film for coating 2
9b and the power supply 6b.

At this time, the coating metal thin film 29b is completely removed from the electrode base 32b (or the coating metal thin film 29b and the true electrode pad 64 which is not a dummy pad).
b) or power supply 6
When the connection between the positive electrode connection lead b and the coating metal thin film 29b is disconnected, the voltage change detection circuit 5 detects the voltage change.

When the voltage change detection circuit 5 detects a voltage change and outputs a detection signal, the detection signal is given to a control circuit or a control input of a switch in the element 4a. As a result, the switch in the control circuit or the element 4a is turned on, the destruction capacitor 3 and the destruction circuit 2 are connected, and the power accumulated in the destruction capacitor 3 by the power supply source 6a is transmitted to the destruction circuit 2. Applied. Thus, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1 is destroyed.

On the other hand, the power supply source 6b is connected to the electrode base 32b.
Are connected to the IC chip 12b through the electrode pads 63b, 64b, 63c, 64c of the
When b is removed, it becomes electrically the same as when the power supply source 6b is removed, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1 is destroyed. Thus, similarly to the first embodiment, the power supply source 6b or the electrode substrate 3
When any of 2b is removed, the self-destruct mechanism is activated.

In this embodiment having two power supply sources, at least two power supply sources are required.
That is, there is a first power supply source 6a for destruction and a second power supply source 6b for monitoring. Second for monitoring
As for the power supply source 6b, there is no particular restriction on the required voltage, so that no problem arises even if it is constituted by one thin battery.

On the other hand, the first power supply source 6a for destruction
The required voltage differs depending on the form of the data memory 14 to be erased and the configuration of the destruction circuit 2, and one or more thin batteries may be required. Here, the destruction circuit 2 will be described with reference to a specific example. For example, when a flash EEPROM is used for the data memory 14, a voltage of 12 to 15 V is required to erase the memory information.

In a flash EEPROM, when such a high voltage of 12 to 15 V is applied in a pulsed manner to a word line consisting of a control gate made of two-layer polysilicon, a substrate is connected to a capacitively coupled floating gate electrode. , And all bits of one block are equally rewritten as “1” or “0” and erased. Thus, the memory information can be destroyed.

When a ferroelectric memory element is used for the data memory 14, a voltage of at least about 5 V is required to erase the memory. In any case, when a single lithium primary battery having an output voltage of about 3.6 V is mounted as the first power supply source 6a for destruction, it is necessary to boost the voltage to a required voltage. 2 requires a booster circuit.

However, it takes some time (about several tens of msec) to raise the power supply voltage from 3.6 V to about 15 V by a charge pump type booster circuit of about 20 stages or the like. Therefore, in the case of this configuration, important confidential information will be erased several tens of msec after detection of unauthorized decomposition by a third party.

In order to reliably erase the memory immediately after detecting an unauthorized decomposition by a third party with a simpler configuration that does not include a booster circuit in the destruction circuit 2, a thin lithium-ion battery must be used as the first power supply source 6a. A plurality of batteries may be connected in series by a required voltage. For example, when a current lithium primary battery is used as the first power supply source 6a, the thickness of each battery is 0.1 mm. Therefore, when four batteries are stacked to generate 14V, the power supply source 6a The total thickness is about 0.1 mm × 4 = 0.4 mm.

When a non-volatile ferroelectric memory element is used as the data memory 14, the write / erase time is 5 to
Since a voltage of 6 V is required, in the case without a booster circuit, it is sufficient to connect two devices in series. In this case, the thickness of the power supply source 6a is about 0.1 mm × 2 = 0.2 mm. .

However, stacking and mounting a number of thin power supply sources to obtain the required voltage is not always possible without limitation due to the thickness limitation. Thus, when two lithium primary batteries are connected in series, the output voltage is 7.2 V.
The starting method is to reduce the number of stages of the booster circuits in the destruction circuit 2 to shorten the boosting time, which is the most realistic configuration method of the first power supply source 6a for destruction and the destruction circuit 2. .

In this embodiment, the power supply source 6b
A connection lead (not shown) is provided on the positive electrode current collector / terminal plate 21 and is joined to the metal thin film 29b for coating. The metal thin film 29b for coating is the positive electrode current collector of the power supply source 6b. Since it is in contact with the entire surface of the terminal board 21, connection leads need not be provided.

[Embodiment 4] FIG. 9 is a circuit block diagram of a self-destructive semiconductor device according to a fourth embodiment of the present invention, and FIG. 10A is a circuit diagram of the self-destructive semiconductor device of FIG. FIG. 10B is a plan view showing an arrangement configuration example, and FIG.
10A is a cross-sectional view taken along the line AA of FIG.
FIG. 11A is a bottom view of a single IC chip of the self-destructive semiconductor device of FIG. 9, and FIG. 11B is a plan view of an electrode substrate of the self-destructive semiconductor device of FIG. Figure 1
The same components as those in FIG. 8 are denoted by the same reference numerals.

In the present embodiment, the semiconductor substrate 9c
On the upper side, a data memory 14, a peripheral circuit 15, a program memory 16, a central processing unit 17, a random access memory 18, and a security authentication microprocessor 19 are formed as the semiconductor integrated circuit 1 necessary for the original IC card function. Further, a destruction circuit 2, a destruction capacitor 3, a control circuit or element 4a, and a voltage change detection circuit 5 are added on the semiconductor substrate 9c. These configurations are the same as in the third embodiment.

In this embodiment, instead of the metal thin films 29a and 29b for coating of the third embodiment, the coating films 30a and 30b each having a metal coated on one surface of an insulating film.
1 shows the case where the first and second power supply sources 6a and 6b are mounted on the IC chip 12c. In this case, since the surface of the insulating film of the coating film 30a is in contact with the power supply source 6b, the coating film 30a and the power supply source 6b are electrically insulated. Therefore, the metal thin film 29a serving as a common negative electrode cannot be used as in the third embodiment, and it is necessary to separately provide electrode pads corresponding to the positive electrode and the negative electrode of the power supply sources 6a and 6b.

That is, as shown in FIG. 11A, eight external connection electrode pads 7-1 to 7-8 necessary for operation as an IC card are provided on the semiconductor substrate 9c on which the IC chip 12c is formed. In addition, one electrode pad 10a for connecting to the positive electrode of the first power supply source 6a is added.
Pad 1 for connecting to the positive electrode of power supply source 6b
0c is added, and a plurality of electrode pads 10b for connecting to the negative electrode of the power supply source 6a are added in two rows facing each other, and the electrode pads 10d for connecting to the negative electrode of the power supply source 6b are facing each other. Are added in two rows.

Further, only one of the electrode pads 10b may be a true electrode pad connected to the voltage change detection circuit 5, the destruction capacitor 3, and the destruction circuit 2, and the others may be dummy pads. You may. Similarly, only one of the electrode pads 10d needs to be a true electrode pad that is connected to the voltage change detection circuit 5, the destruction capacitor 3, and the destruction circuit 2 by wiring.

On the other hand, the electrode substrate 3 made of glass epoxy
As shown in FIG. 11B, electrode pads 62-1 to 62-8 corresponding to the electrode pads 7-1 to 7-8 of the IC chip 12c are formed on the IC chip mounting surface of 2c. An electrode pad 63a corresponding to 10a is formed,
A plurality of electrode pads 63b corresponding to the electrode pads 10b are formed in two opposing rows, and electrode pads 63c corresponding to the electrode pads 10c are formed.
Are formed in two rows facing each other, electrode pads 64a for connecting to the positive electrode of the power supply source 6a are formed, and electrodes for connecting to the positive electrode of the power supply source 6b are formed. A pad 64c is formed, and an electrode pad 64b for connecting to the negative electrode of the power supply source 6a
Are formed in two rows facing each other, and the power supply source 6
A plurality of electrode pads 64d for connection to the negative electrode b are formed in two opposing rows.

Further, eight contact patterns 35 are formed on the surface of the electrode base 32c facing the IC chip mounting surface. The electrode pads 62-1 to 62-8 are respectively connected to the corresponding contact patterns 35 by through holes or the like. The electrode pad 63a is an electrode pad 64
a, and each of the electrode pads 63b is connected to the corresponding electrode pad 64b, each of the electrode pads 63c is connected to the corresponding electrode pad 64c, and each of the electrode pads 63d is connected to the corresponding electrode pad 64d. Wiring is connected.

Here, a method of mounting the self-destructive semiconductor device of the present embodiment will be described. First, bumps 27 made of gold (Au) or the like are formed on the external connection electrode pads 7-1 to 7-8 and the power supply connection electrode pads 10a, 10b, 10c, and 10d on the IC chip 12c.

In order to perform flip chip mounting, anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of electrode base 32c or IC chip 12c, as in the first embodiment. Next, the element surface of the IC chip 12c (the paper surface of FIG. 11A) and the IC chip mounting surface of the electrode base 32c (the paper surface of FIG. 11B) face each other, and the electrode pads 7-1 to 7-1 of the IC chip 12c. 7-8 and electrode base 32c
The electrode pads 62-1 to 62-8 are connected, the electrode pad 10a and the electrode pad 63a are connected, the electrode pad 10b and the electrode pad 63b are connected, and the electrode pad 10c and the electrode pad 63c are connected. , Electrode pad 1
Positioning of each electrode pad is performed so that 0d and the electrode pad 63d are connected, and pressure is applied from the back surface of the IC chip 12c.

In the state where such pressure is applied, the anisotropic conductive adhesive resin 61 is cured as in the case of the first embodiment. Next, the power supply source connection electrode pad 64a on the electrode base 32c and the connection lead 28a of the power supply source 6a are electrically connected by spot welding such as ultrasonic wire bonding or laser welding.

As in the first embodiment, if a metal rod serving as a heat sink is used, high heat generated during spot welding can be radiated from the heat sink and not conducted to the power supply source 6a. Power supply source connection electrode pad 6
After spot welding the connection lead 4a and the connection lead 28a, the power supply source 6a is mounted on the back surface of the IC chip 12c by the adhesive film 20.

When it is necessary to connect two or more power supply sources 6a in series, as in the third embodiment, the necessary number of power supply sources 6a may be stacked. Next, the negative electrode current collector / terminal plate 25 of the uppermost power supply source 6a
And power supply source connection electrode pad 64 on electrode base 32c
b is electrically connected.

In order to realize such an electrical connection, first, of the power supply source connection electrode pads 64b formed on the electrode base 32c and arranged in two rows,
The electrode pads 64b in one row on the upper side or the lower side are brought into contact with the conductive surface (metal coated surface) of the coating film 30a, and a laser beam is applied to these contact points to form the electrode pads 64b. Is spot-welded to one end of the coating film 30a.

Subsequently, a coating film 30a is stretched so as to cover the power supply source 6a, and the other metal coating surface of the coating film 30a is brought into contact with the other row of the electrode pads 64b. The contact point is irradiated with laser light, and the electrode pad 64b
Is spot-welded to the other end of the coating film 30a.

In this manner, the coating film 30a is formed on the electrode base 32c.
Fixed to. Since the negative electrode current collector / terminal plate 25 of the uppermost power supply source 6a is in contact with the metal coating surface of the coating film 30a over the entire area thereof, the power supply source is provided via the metal thin film of the coating film 30a. The connection electrode pad 64b and the negative electrode current collector / terminal plate 25 of the power supply source 6a are electrically connected.

Next, the power supply source connection electrode pad 64c on the electrode base 32c and the connection lead 28b of the second power supply source 6b are electrically connected by spot welding such as ultrasonic wire bonding or laser welding. Connect to In order to realize such electrical connection, first, the coating film 30
a and the positive electrode current collector / terminal plate 21 of the power supply source 6b are opposed to each other, that is, the power supply source 6b is placed on the coating film 30a so that the positive electrode current collector / terminal plate 21 faces downward. . Here, since it is not necessary to electrically connect the positive electrode current collector / terminal plate 21 of the power supply source 6b and the coating film 30a, the coating film 30a and the power supply source are fixed for fixing the power supply source 6b. 6
An adhesive film may be provided between b.

Subsequently, after the power supply source connection electrode pad 64c of the electrode base 32c is brought into contact with the connection lead 28b, the contact point is irradiated with laser light,
Power supply connection electrode pad 64c and connection lead 28b
And spot welding. As in the first embodiment, if a metal rod serving as a heat sink is used, high heat during spot welding can be radiated from the heat sink and not conducted to the power supply source 6b.

Next, the power supply source connecting electrode pad 64d on the electrode base 32c is electrically connected to the negative electrode current collector / terminal plate 25 of the power supply source 6b. In order to realize such an electrical connection, of the power supply source connection electrode pads 64d arranged in two rows on the electrode base 32c,
After the electrode pad 64d in one row on the left side or the right side is brought into contact with the conductive surface (metal coated surface) of the coating film 30b, a laser is irradiated to these contact points, and one of the electrode pads 64d is irradiated. The row and one end of the coating film 30b are spot-welded.

Then, the coating film 30b is stretched so as to cover the power supply source 6b, and the metal coating surface at the other end of the coating film 30b is brought into contact with the other row of the electrode pads 64d. The spot is irradiated with laser, and the other row of the electrode pads 64d and the other end of the coating film 30b are spot-welded.

In this way, the coating film 30b is formed on the electrode base 32c.
Fixed to. Negative electrode current collector / terminal plate 25 of power supply source 6b
Is in contact with the metal coating surface of the coating film 30b over the entire area thereof, so that the electrode pad 64d and the negative electrode current collector / terminal plate 25 of the power supply source 6b are connected via the metal layer of the coating film 30b. Electrically connected.

The operation of the self-destruction mechanism of the self-destruction type semiconductor device of this embodiment is the same as that of the third embodiment. That is, the coating film 30b is completely removed from the electrode base 32c (or the connection between the coating film 30b and the true electrode pad 64d that is not a dummy pad is removed), or the connection between the connection lead 28b and the electrode pad 64c. When the connection is removed, a self-destruct mechanism is activated. Note that the coating metal thin film 29b may be used instead of the coating film 30b in the present embodiment.

[Fifth Embodiment] FIG. 12A is a cross-sectional view of a self-destructive semiconductor device showing a fifth embodiment of the present invention, and FIG. 12B is a diagram showing an IC chip mounted on an electrode substrate. FIG. 1 is a view showing a state of flip chip mounting.
Configurations equivalent to 1 are denoted by the same reference numerals. FIG. 12A shows a self-destructive semiconductor device after completion of mounting, cut along the line AA shown in FIG. 12B.

In the mounting structure shown in the third embodiment, if the size of the power supply source 6a is small, local stress is generated at a protruding portion of the power supply source 6b, and the power supply source 6b
Uneven stress is generated inside. Therefore, in the present embodiment, as shown in FIG.
b and the electrode base 32d on which the IC chip 12b is mounted,
Contact pattern 35 (35-1 to 35-8) on the lower surface
Are formed, and the power supply source connection electrode pad 62-
A first layer on which 1 to 62-8, 63a, 63b, and 63c are formed, and a thickness equal to that of the IC chip 12b;
A second layer in which a hole of the size of the C chip 12b is formed, and a power supply source connection electrode pad 64a is formed on the upper surface; and a second layer having the same thickness as the power supply source 6a, and
And a third layer of a third layer in which power supply source connection electrode pads 64b and 64c are formed on the upper surface.

The circuit block configuration of the self-destructive semiconductor device of the present embodiment is the same as that of FIG.
In the same manner as described above, an electrode configuration is used in which the negative electrodes of the power supply sources 6a and 6b are connected in common, but the pad array is arranged on all four sides of the electrode base 32d, as shown in FIG. An electrode pad is arranged.

On the IC chip mounting surface of the first layer of the electrode substrate 32d, the electrode pads 7-1 to 7-8 of the IC chip 12b are provided.
Are formed, and electrode pads 62-1 to 62-8 corresponding to
An electrode pad 63a corresponding to the electrode pad 10a is formed, and a plurality of electrode pads 63b corresponding to the electrode pad 10b are formed in two opposing rows.
Are formed in two rows facing each other. The electrode pads 7-1 to 7-8 are respectively connected to the contact patterns 35 by through holes or the like.
-1 to 35-8.

On the upper surface of the second layer of the electrode base 32d, a power supply connection electrode pad 64a for connecting to the positive electrode of the power supply 6a is formed. This electrode pad 64
a is connected to the electrode pad 63a via a printed wiring, a through hole, and the like. On the upper surface of the third layer of the electrode substrate 32d, a plurality of power supply source connection electrode pads 64c for connecting to the positive electrode of the power supply source 6b are formed in two opposing rows, and the power supply sources 6a and 6b The power supply source connection electrode pad 64b for connection to the negative electrode of
A plurality of rows are formed.

Each of the electrode pads 64b is connected to the electrode pad 63b via a printed wiring, a through hole, and the like.
Each of the electrode pads 64c is connected to the electrode pad 63c via a printed wiring, a through hole, and the like. The IC chip 12b is flip-chip mounted on the electrode base 32d. The procedure is the same as in the third embodiment, and will not be described in detail.

Subsequently, the electrode base 32d is formed by spot welding such as ultrasonic wire bonding or laser welding.
Power supply source connection electrode pad 64a and power supply source 6
a is electrically connected to the connection lead 28a. After the power supply connection electrode pad 64a and the connection lead 28a are spot-welded, the power supply 6a is attached to the adhesive film 2 on the back surface of the IC chip 12b and on the second layer of the electrode base 32d.
0 is mounted.

Next, the power supply source connection electrode pad 64b on the electrode base 32d is electrically connected to the negative electrode current collector / terminal plate 25 of the power supply source 6a. In order to realize such an electrical connection, first, of the power supply source connection electrode pads 64b formed on the third layer of the electrode base 32d and arranged in two rows, the upper or lower side is used. After contacting one end of the electrode pad 64b with one end of the coating metal thin film 29a, these contact points are irradiated with a laser beam, so that one row of the electrode pad 64b and the coating metal thin film 29a
spot welding with one end of a.

Subsequently, the coating metal thin film 29a is stretched so as to cover the power supply source 6a, and the other end of the coating metal thin film 29a is brought into contact with the other row of the electrode pads 64b.
These contact points are irradiated with laser light, and the electrode pads 64 are irradiated.
b is spot-welded to the other end of the coating metal thin film 29a. Next, the power supply source connection electrode pad 64c on the electrode base 32d and the connection lead 28b of the second power supply source 6b joined to the positive electrode current collector / terminal plate 21 are electrically connected, and the power supply is performed. Supply source connection electrode pad 64
b and the negative electrode current collector / terminal plate 25 of the power supply source 6b are electrically connected.

In order to realize this electrical connection, first, the metal thin film 29a for coating is brought into contact with the negative electrode current collector / terminal plate 25 of the power supply source 6b by contacting the metal thin film 29a for coating.
The power supply source 6b is placed on top. Subsequently, the electrode substrate 32d
Of the power supply source connection electrode pads 64c arranged in two rows above, the electrode pads 64c in one of the left or right rows are brought into contact with one end of the coating metal thin film 29b, and these are contacted. A laser is applied to the contact point, and one row of the electrode pads 64c and one end of the coating metal thin film 29b are spot-welded.

Next, the power supply source 6b is formed by spot welding such as ultrasonic wire bonding or laser welding.
The connection lead 28b and the coating metal thin film 29b are joined. Then, the coating metal thin film 29b is stretched so as to cover the power supply source 6b, and the other end of the coating metal thin film 29b is brought into contact with the other row of the electrode pads 64c, and then these contact points are irradiated with laser. Then, the other row of the electrode pads 64c and the other end of the coating metal thin film 29b are spot-welded.

In the present embodiment, the power supply source 6a protruding from the IC chip 12b is supported by the second layer having the same thickness as the IC chip 12b.
The stress corresponding to the thickness of 2b is not concentrated on a part of the power supply source 6a and the battery life is not deteriorated. Further, the size of the power supply source 6a can be much larger than that of the IC chip 12b within a range allowed by the electrode base 32d, so that the power capacity can be increased.

Similarly, on the surface on which the power supply source 6b is mounted, the third layer of the electrode base 32d reduces the step with the power supply source 6a. It is possible to mount a large power supply.

Finally, the physical thickness of the above structure will be discussed. The first layer of the electrode substrate 32d is formed of a contact pattern 35-1 to 35-8 made of a copper foil or the like having a thickness of 35 μm.
Is made of a 120 μm thick glass epoxy substrate formed on the lower surface. On the upper surface of the first layer, electrode pads and the like for making electrical connection with the IC chip 12b are formed together with a wiring pattern, and each is made of a metal having a thickness of 1 μm or less.

Next, the second layer of the electrode substrate 32d must have a thickness obtained by adding the thickness of the IC chip 12b to about 50 to 100 μm and the height of the bump to 50 to 80 μm. The minimum is about 100 μm. Since the third layer of the electrode base 32d has a thickness equivalent to the thickness of the power supply source 6a, when a current lithium primary battery is used for the power supply source 6a, the thickness is 100 μm per cell.
When they are stacked and mounted, the thickness becomes 200 μm.

Further, a lithium primary battery having a thickness of 100 μm is mounted thereon as a power supply source 6b. In addition,
The thickness of the two covering metal thin films 29a and 29b is about 20 μm from the viewpoint of strength and the like. Therefore, the total thickness including the electrode base 32d and the power supply source 6b is about 600 μm (= 35 + 120 + 100 + 200 + 100).
+ 20 × 2 μm), and it is sufficiently possible to put the IC module in an IC card having a thickness of 0.76 mm.

In the first to fifth embodiments, the connection leads 28a and 28b are joined to the positive electrode current collector / terminal plate 21 of the power supply sources 6a and 6b. Since the power supply is performed before assembling the power sources 6a and 6b, that is, when the current collector is used alone, there is no problem in heating the power sources 6a and 6b during processing.

[Sixth Embodiment] Next, a sixth embodiment of the present invention will be described with reference to FIG. In the present invention, the output voltage of the power supply source 6a or 6b must be constantly monitored by the voltage change detection circuit 5. However, when a thin lithium battery is mounted as the power supply sources 6a and 6b, the capacity density is 1.5 mA.
Since it is as small as about h / cm ² (single-stage cell, 0.1 mm), the battery life becomes extremely short in a circuit configuration in which a large current is continuously supplied.

Therefore, it is an essential condition for the configuration of the voltage change detection circuit 5 to have a capacitively coupled circuit configuration so that a leak path does not match a current path related to its operation. FIG. 13 shows an example of such a capacitively-coupled voltage change detection circuit. In this embodiment, a MOS field effect transistor is used as the voltage change detecting element.

[0162] The output voltage of the power supply 6b is divided by a voltage voltage-dividing capacitor C _1, C ₂ and the resistor R _1, a voltage voltage-dividing capacitor C _1, the connection point of the C ₂ of the voltage change detecting transistor 31 Input to the gate. Since the power consumption of the voltage change detection transistor 31 is very small, the voltage stored in the destruction capacitor 3 or a large-capacity drive capacitor provided separately from the destruction capacitor 3 should be used as the drive voltage. Can be.

When a third party for falsification of the IC card removes the connection between the power supply source 6a or 6b and the voltage change detection circuit 5 as described above, the voltage is set near the threshold voltage of the transistor 31. The capacitance-divided voltage fluctuates, whereby the transistor 31 is turned on. Accordingly, current flows between the source and the drain of the transistor 31, a voltage drop occurs between the resistor R ₂ terminals. This voltage drop is output as a detection signal to the control circuit or the element 4a via the post-amplifying circuit 33.

[Seventh Embodiment] Next, a seventh embodiment of the present invention will be described with reference to FIG. Since the capacity of the thin power supply sources 6a and 6b to be mounted is limited, switches in the control circuit or the element 4a include:
It is desirable that the power consumption be as low as possible. Usually, this switch is generally a semiconductor switch configured by combining transistors. In this case, however, it is a major problem to reduce power consumption due to sub-threshold current leakage when the switch is off.

In the present invention, as such a switch with low power consumption, it is possible to use a micromechanical switch which is a kind of micromechanical element having a movable portion and opens and closes contacts using electrostatic attraction. . FIG. 14 shows an example of a micro-mechanical switch that opens and closes contacts using such electrostatic attraction. In the figure, (a) is a sectional view,
(B) is a plan view.

As shown in FIG. 14A, in the micro mechanical switch, a movable suction electrode 47 is provided with a support beam 48.
And the connection electrode 49a. When no voltage is applied to the fixed suction electrode 50, the movable contact electrode 5
1 is pressed against the fixed contact electrodes 52b and 52c by the elastic force (upward) of the support beam 48.

As a result, the COMM input terminal 53 is electrically connected to the output 2 terminal 54b. The fixed contact electrode 52
The b and 52c are supported by the contact electrode support 55, and are electrically connected to the COMM input terminal 53 and the output 2 terminal 54b via the connection electrodes 49b and 49c, respectively. The movable contact electrode 51 is electrically insulated from the support beam 48 by the insulating film 57 and is mechanically fixed to the support beam 48.

When a voltage is applied to the fixed suction electrode 50 from the movable contact operating power supply terminal 56, the support beam 48 is generated by electrostatic attraction acting between the fixed suction electrode 50 and the movable suction electrode 47.
Goes down. Then, the movable contact electrode 51 becomes the fixed contact electrode 5
2b, 52c, the fixed contact electrode 52 on the opposite side
a, 52d. As a result, the COMM input terminal 53 becomes the output 1 terminal 5 via the movable contact electrode 51.
4a.

When the voltage application to the fixed suction electrode 50 is stopped, the movable contact electrode 51 moves upward by the elastic force of the support beam 48. As a result, the movable contact electrode 51 is again pressed against the fixed contact electrodes 52b and 52c, and the COMM
The input terminal 53 conducts with the output 2 terminal 54b. Thus, the current path is switched by the micro mechanical switch.

In connection with other circuits, the detection signal output of the voltage change detection circuit 5 is connected to the movable contact operating power supply terminal 56, and one end of the electrode pad 10a and one end of the destruction capacitor 3 are connected to the COMM input terminal 53. , And one end of the destruction circuit 2 may be connected to the output 1 terminal 54a.

[Eighth Embodiment] Next, an eighth embodiment of the present invention will be described with reference to FIG. In the present invention, the configuration of the destruction circuit 2 is based on the IC chips 12a to 12c.
It is important to avoid reuse of 12c. In the present invention, the function of the integrated circuit is reliably destroyed by destroying a partial circuit including a fuse or an anti-fuse by using the power stored in the breakdown capacitor 3.

As a circuit to be destroyed, as shown in FIG. 15, a read circuit of a ROM boot circuit, which is the most important in the operation of the IC chips 12a to 12c, can be considered as an example. In FIG. 15A, a decoder input / output line portion of an address signal of a read circuit, for example, signal lines C _A0 , C A
_A1, provided _{C A2, C A3, R A0} , R A1, R A2, antifuse 39 in a part of R _A3, constitute a breaking circuit 2.

FIG. 15B shows a plan pattern diagram of the cell configuration in each cell portion. Input / output of the row decoder 40 is performed via a polysilicon word line constituting a gate electrode of a cell transistor constituting each of the cells 100 to 133, and a bit line of the first layer Al is perpendicular to the word line. 43 (B ₀ , B ₁ , B ₂ , B ₃ ) is running.
Here, it is provided with antifuse 39 by a thin oxide film on the portion of the signal output line R _A1 of the gate G _R1 row decoder 40 (in the drawing "×" mark).

FIGS. 16A and 16B show the structure of the antifuse. FIG. 16A is a plan view, and FIG.
It is A 'sectional drawing. As shown in FIG.
An element isolation insulating film (LOCO) is formed on a P-type Si semiconductor substrate.
S) The polysilicon word line 42 runs while being insulated by 46. The anti-fuse 39 does not partially form the element isolation insulating film 46, and a thin gate oxide film 39a is formed there.
Is formed, an N + diffusion layer 45 is provided by implanting phosphorous at a high concentration, and this is used as a ground.

N + insulated by this gate oxide film 39a
When a voltage is applied to the polysilicon word line 42 running on the diffusion layer 45 from the large-capacity destruction capacitor 3 storing the electric charge from the power supply source 6a, the gate oxide film 39a is broken down and the word line 42 is broken. Short circuit with the board. As a result, all the cells addressed by the row decoder 40 using the word line 42 (cells 101, 111,
121, 131) cannot be read, and reading from the ROM is reliably prevented.

The gate oxide film 39a has a thickness of 8
nm, 20 MV / cm
A very high electric field is required. In this case, the voltage required for destruction is 16 V. When thin lithium primary batteries are used as the power supply sources 6 a and 6 b, 3.6 V × 5 stages = 18
Since the voltage is V, four to five stages are connected in series and stored, and this power is stored in the large-capacity destruction capacitor 3, so that sufficient destruction power can be obtained.

Alternatively, a portion of the polysilicon word line 42 operating as the signal input / output line R _A1 may be thinned to be used as a fuse.
That is, a large current is applied to the signal line from the large-capacity destruction capacitor 3 storing the electric charge, and the thinned portion of the polysilicon wiring is scattered by thermal melting. Thus,
It is to break the fuse portion provided in the middle of the signal output line R _A1, can also be destroyed the reading circuit of ROM boot circuit.

[0178]

According to the present invention, the semiconductor substrate is flip-chip mounted on the electrode base, and the first current collector of the power supply source is connected to the third and fifth electrodes of the electrode base. And the second current collector of the power supply is connected to the metal thin film and the fourth and sixth power supply connection terminals of the electrode substrate. Connect to a semiconductor integrated circuit. Thus, when any one of the metal thin film, the power supply source, and the electrode substrate is removed, the self-destruction mechanism is activated, and the falsification of the memory contents of the semiconductor integrated circuit can be reliably prevented. Also, the element surface of the semiconductor substrate is optically shielded by the electrode base, the back surface of the semiconductor substrate is optically shielded by the power supply source and the metal thin film, and the connection lead of the power supply source and the fifth and sixth power supply are provided. By optically shielding the power supply connection terminal, a third party for the purpose of falsifying the semiconductor device connects another power supply that generates the same voltage as the power supply in parallel with the power supply, Removal of the shielding power supply source from the semiconductor substrate can be prevented. Further, by covering the semiconductor substrate and the power supply source with a metal thin film, mechanical strength can be increased. Further, when connecting the connection lead to the fifth power supply source connection terminal, the connection lead may be pressed by a metal rod serving as a heat sink to be pressed against the fifth power supply source connection terminal. Heating to the source can be reduced, and deterioration of the battery life due to heating can be avoided.

Further, the semiconductor substrate is flip-chip mounted on the electrode base, and the first current collector of the second power supply source is connected to the second metal thin film and the sixth base of the electrode base. , A ninth power supply source connection terminal, and connecting the second current collector of the second power supply source to the first metal thin film and the fifth and eighth electrodes of the electrode base. It is connected to the semiconductor integrated circuit via the power supply source connection terminal. Thus, when any one of the second metal thin film, the second power supply source, and the electrode base is removed, a self-destruction mechanism is activated, and it is possible to reliably prevent the memory contents of the semiconductor integrated circuit from being falsified. . In addition, a self-destruction function that erases information in the data memory when detecting removal of the shielding power supply by a third party by monitoring voltage fluctuations over a long period of time is driven by a single power supply. Instead, a circuit configuration is provided in which two systems are provided to allow a margin for required power. That is, the voltage required by the destruction circuit is supplied from the first power supply source without using the booster circuit, or the voltage required by the destruction circuit is supplied from the first power supply source to the booster circuit. Is supplied from a booster circuit, and the second power supply is used only for voltage monitoring, so that the self-destructive function can be operated for a long time even with a chip-size, thin, and small power supply. Thus, the degree of freedom in circuit design can be increased. Further, the element surface of the semiconductor substrate is optically shielded by the electrode base, the back surface of the semiconductor substrate is optically shielded by the power supply source and the metal thin film, and the connection leads of the first power supply source and the seventh to seventh power supply sources
By optically shielding the ninth power supply source connection terminal, a third party aiming at falsification of the semiconductor device can connect another power supply that generates the same voltage as the power supply in parallel with the power supply. To prevent the power supply for shielding from being removed from the semiconductor substrate. Further, by covering the semiconductor substrate and the power supply source with a metal thin film, mechanical strength can be increased. Also, the connection lead and the seventh
When the connection lead is connected to the seventh power supply source connection terminal by pressing the connection lead with a metal rod serving as a heat sink, the heating to the power supply source is reduced. Thus, deterioration of the battery life due to heating can be avoided.

Further, the semiconductor substrate is flip-chip mounted on the electrode base, and the first current collector of the second power supply source is connected to the fifth and ninth power supplies of the electrode base. Connected to the semiconductor integrated circuit via the power supply connection terminal,
The second current collector of the second power supply is connected to the semiconductor integrated circuit via the metal thin film and the sixth and tenth power supply connection terminals of the electrode base. Thus, when any one of the metal thin film, the second power supply source, and the electrode substrate is removed, the self-destruction mechanism is activated, and the falsification of the memory content of the semiconductor integrated circuit can be reliably prevented.
In addition, the self-destruction function is not driven by a single power supply source, but is divided into two circuits to provide a margin for required power, thereby providing a chip-size and thin power supply source with a small power capacity. Accordingly, the self-destruction function can be operated for a long period of time, and the degree of freedom in circuit design can be increased. Further, by optically shielding the connection leads of the first and second power supply sources and the ninth to twelfth power supply source connection terminals, a third party aiming at falsification of the semiconductor device can supply power. Another power supply that produces the same voltage as the source can be connected in parallel with the power supply to prevent removal of the shielding power supply from the semiconductor substrate. Further, by covering the semiconductor substrate and the power supply source with a metal thin film, mechanical strength can be increased. Further, when connecting the connection lead to the ninth and eleventh power supply source connection terminals, the connection lead is pressed by a metal rod serving as a heat sink to be pressed against the ninth and eleventh power supply source connection terminals. Accordingly, heating to the power supply source can be reduced, and deterioration of the battery life due to heating can be avoided.

In addition, by providing a destruction circuit, a destruction capacitor, a voltage change detection circuit, and a control circuit or element on a semiconductor substrate, the contents of the memory of the semiconductor integrated circuit can be altered. Metal thin film,
When either the power supply or the electrode substrate is removed,
Since the self-destruction mechanism is activated and a part of the wiring or the memory information of the semiconductor integrated circuit is destroyed, it is possible to reliably prevent the memory contents of the semiconductor integrated circuit from being falsified.

Further, as described in claim 5, the electrode substrate is formed of a three-layer substrate, and the second substrate having the same thickness as the semiconductor substrate is formed.
The layer supports the power supply or the first power supply protruding from the semiconductor substrate, and the third layer having the same thickness as the first power supply supplies the second power protruding from the first power supply. Support power supply. As a result, the stress is not concentrated on a part of the power supply source and the battery life is not deteriorated, so that the power supply source can be increased to increase the power capacity as far as the electrode base allows. .

[Brief description of the drawings]

FIG. 1 is a circuit block configuration diagram of a self-destructive semiconductor device according to a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device of FIG.

3 is a bottom view of an IC chip alone and a plan view of an electrode base of the self-destructive semiconductor device of FIG. 1;

FIG. 4 is a plan view and a cross-sectional view of a power supply source of the self-destructive semiconductor device of FIG.

FIG. 5 is a cross-sectional view of a self-destructive semiconductor device according to a second embodiment of the present invention and a view showing a state of flip-chip mounting in which an IC chip is mounted on an electrode substrate.

FIG. 6 is a circuit block diagram of a self-destructive semiconductor device according to a third embodiment of the present invention.

7A and 7B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG.

8 is a bottom view of an IC chip alone and a plan view of an electrode base of the self-destructive semiconductor device of FIG. 8;

FIG. 9 is a circuit block diagram of a self-destructive semiconductor device according to a fourth embodiment of the present invention.

10A and 10B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG. 9;

11 is a bottom view of a single IC chip of the self-destructive semiconductor device of FIG. 9 and a plan view of an electrode substrate.

FIG. 12 is a cross-sectional view of a self-destructive semiconductor device according to a fifth embodiment of the present invention and a diagram illustrating a state of flip-chip mounting in which an IC chip is mounted on an electrode substrate.

FIG. 13 is a circuit diagram illustrating a configuration example of a voltage change detection circuit according to a sixth embodiment of the present invention.

14A and 14B are a cross-sectional view and a plan view illustrating a configuration example of a control circuit or an element according to a seventh embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a configuration example of a destruction circuit using an antifuse according to an eighth embodiment of the present invention.

FIG. 16 is an explanatory diagram showing a configuration example of an antifuse.

FIG. 17 is an explanatory diagram showing a configuration example of a general IC card.

FIG. 18 is a cross-sectional view of an IC module on which flip chip mounting has been performed and a bottom view of an IC chip alone.

FIG. 19 is a circuit block diagram of a conventional self-destructive semiconductor device.

20A and 20B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Destruction circuit, 3 ... Destruction capacitor, 4 and 4a ... Control circuit or element, 5 ... Voltage change detection circuit, 6a, 6b ... Power supply source, 7-1 to 7-8 ... External Connection electrode pads, 9a, 9b, 9c: semiconductor substrate, 1
0a, 10b, 10c, 10d: power supply source connection electrode pads, 12a, 12b, 12c: IC chip, 14:
Data memory, 15 peripheral circuits, 16 program memory, 17 central processing unit, 18 random access memory, 19 microprocessor for authentication, 20 adhesive film, 21 positive electrode current collector / terminal plate, 22 Positive electrode, 23
... Solid electrolyte, 24 ... Negative electrode, 25 ... Negative electrode current collector / terminal plate, 26 ... Sealant, 27 ... Bump, 28a, 28b ... Connection lead, 29, 29a, 29b ... Coating metal thin film, 3
0a, 30b ... Coating film. 32, 32a, 32b, 32
c, 32d: electrode base, 61: anisotropic conductive adhesive resin, 6
2-1 to 62-8: electrode pads for external connection, 63a, 6
3b, 63c, 63d, 64a, 64b, 64c, 64
d: Electrode pad for connecting the power supply source.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Katsuyuki Machida, Inventor F-term (reference) in Nippon Telegraph and Telephone Corporation 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo 5B035 AA05 AA15 BA03 BA05 BB02 BB09 CA08 CA12 CA38 5F083 GA30 ZA13 ZA29

Claims (5)

[Claims] A semiconductor integrated circuit in which a semiconductor memory element and a central processing unit for processing data stored in the memory element are formed on the same semiconductor substrate; a power supply for performing self-destruction; A self-destructive semiconductor device having an electrode substrate for mounting a semiconductor substrate and a metal thin film for covering a power supply source, wherein the semiconductor substrate has a first external connection terminal and a first external connection terminal on an element surface. And a second power supply source connection terminal, wherein the electrode base has a second external connection terminal, a third and fourth power supply source connection terminal on a mounting surface of the semiconductor substrate, and the power supply source. The semiconductor substrate has fifth and sixth power supply source connection terminals connected to the connection terminals, and the semiconductor substrate has the element surface and the electrode substrate facing each other, and the first and second external connection terminals have Connected to the first and second power supply connection terminals and the third The power supply source is mounted on the electrode base so as to be connected to a fourth power supply source connection terminal, wherein the power supply source is one of a positive electrode current collector and a negative electrode current collector. A connection lead on the surface of the first current collector, and the first current collector is mounted on the semiconductor substrate so as to face the back surface of the semiconductor substrate; And a metal thin film covered on the second current collector of the power supply so as to cover the power supply, and two opposing sides of the electrode base. The sixth power supply source connection terminal formed in the peripheral portion is joined to make an electrical connection between the power supply source and the electrode substrate, and the semiconductor substrate is sandwiched between the power supply source and the electrode substrate. A self-destructive semiconductor device characterized by being fixed. 2. A semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate; a power supply for performing self-destruction; A self-destructive semiconductor device having an electrode substrate for mounting a semiconductor substrate and first and second metal thin films for covering a power supply source, wherein the semiconductor substrate has a first external surface on an element surface. A connection terminal and first, second, and third power supply source connection terminals, wherein the electrode substrate has a second external connection terminal, a fourth, a fifth, and a sixth terminal on a mounting surface of the semiconductor substrate. A power supply source connection terminal, and seventh, eighth, and ninth power supply source connection terminals connected to the power supply source connection terminal. The semiconductor substrate has an element surface and an electrode substrate. The first and second external connection terminals are connected to each other, , The third power supply connection terminal and the fourth, fifth, and sixth power supply connection terminals are mounted on the electrode base so as to be connected to each other. A first power supply for self-destruction,
A second power supply for detecting a voltage change, wherein the first power supply is provided with a connection lead on a surface of one of the first current collector of the positive electrode current collector and the negative electrode current collector; And the first
Is mounted on the semiconductor substrate such that the current collector faces the back surface of the semiconductor substrate, and a connection lead of the first power supply source and a seventh power supply source connection terminal formed on the electrode substrate are provided. And the first
The first metal thin film and the electrode base facing each other on the second current collector of the first power supply source so as to cover the first power supply source;
An eighth power supply source connection terminal formed in a peripheral portion including a side is joined to perform an electrical connection between the first power supply source and the electrode base, and the second power supply source includes: A third current collector having the same polarity as the first current collector among the positive electrode current collector and the negative electrode current collector is mounted on the first metal thin film so as to face upward; The fourth current collector of the second power source is brought into contact with the first metal thin film, and the fourth power source is covered on the third current collector of the second power source so as to cover the second power source. The second metal thin film and the ninth power supply source connection terminal formed on the peripheral portion including the two opposing sides of the electrode substrate are joined to form an electrical connection between the second power supply source and the electrode substrate. A self-destructive semiconductor device, comprising: connecting and fixing a semiconductor substrate between first and second power supply sources and an electrode substrate so as to sandwich the semiconductor substrate. 3. A semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate; a power supply for performing self-destruction; A self-destructive semiconductor device having an electrode substrate for mounting a semiconductor substrate, an insulating film having a metal layer formed on one surface thereof for covering a power supply source, and a metal thin film for covering a power supply source. The semiconductor substrate has a first external connection terminal and first, second, third, and fourth power supply source connection terminals on an element surface, and the electrode substrate has a semiconductor substrate mounted thereon. A second external connection terminal, fifth, sixth, seventh, and eighth power supply source connection terminals on the surface, and a ninth, connected to the power supply source connection terminal,
Tenth, eleventh, and twelfth power supply source connection terminals are provided, and in the semiconductor substrate, the element surface and the electrode base face each other;
The first and second external connection terminals are connected, and the first, second, third, and fourth power supply source connection terminals are connected to fifth, sixth, and fifth terminals.
A power supply source for self-destruction, wherein the power supply source is mounted on the electrode base so as to be connected to seventh and eighth power supply source connection terminals;
A second power supply for detecting a voltage change, wherein the first power supply is provided with a connection lead on a surface of one of the first current collector of the positive electrode current collector and the negative electrode current collector; And the first
Is mounted on the semiconductor substrate so that the current collector faces the back surface of the semiconductor substrate, and a connection lead of the first power supply source and an eleventh power supply source connection terminal formed on the electrode substrate are provided. And bonding the metal layer of the insulating film and the electrode substrate so as to cover the first power supply so that the metal layer is in contact with the second current collector of the first power supply. A twelfth power supply source connection terminal formed at a peripheral portion including two opposing sides is joined to perform an electrical connection between the first power supply source and the electrode base; The source has a connection lead on a surface of a third current collector of one of the positive electrode current collector and the negative electrode current collector, and is insulated so that the third current collector faces the insulating film. Mounted on a conductive film, and connected to the connection lead of the second power supply source and the electrode substrate. With joining the ninth terminal of the power supply connection has been made, the second
And a tenth power supply source connection formed on a peripheral portion including two opposing sides of the metal thin film and the electrode base on the fourth current collector of the power supply source so as to cover the second power supply source. And the second power supply source and the electrode base are electrically connected, and the semiconductor substrate is fixed between the first and second power supply sources and the electrode base. Characteristic self-destructive semiconductor device. 4. The self-destructive semiconductor device according to claim 1, wherein at least a part of memory information of the semiconductor integrated circuit is destroyed or at least a part of a signal wiring is disconnected to perform a self-destruction. A destruction circuit, a destruction capacitor for storing electric charge for self-destruction by the destruction circuit, and a voltage between the first power supply source connection terminal and the second power supply source connection terminal. A voltage change detection circuit that outputs a detection signal in accordance with the voltage drop; and a power supply source and a destruction capacitor connected to the power supply source via the power supply source connection terminal during normal operation. When a signal is output, a control circuit or an element for disconnecting the connection and connecting the destruction capacitor and the destruction circuit is provided on the semiconductor substrate, respectively. Destruction type semiconductor device. 5. The self-destructive semiconductor device according to claim 1, wherein said electrode substrate has a first layer on which said external connection terminal and a power supply source connection terminal are formed, and said semiconductor substrate. Having an opening of a thickness of the semiconductor substrate and a size of the semiconductor substrate.
A self-destructive type wherein a three-layer substrate having a thickness of the power supply source and an opening having a size of the power supply source is sequentially laminated. Semiconductor device.