JP3725698B2 - Self-destructive semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor integrated circuit that stores and processes important information with high confidentiality, and more particularly to a security technique against alteration of memory contents of the semiconductor integrated circuit.
[0002]
[Prior art]
In order to analyze the function, operation method, circuit system, circuit pattern, storage data, etc. of the integrated circuit of a semiconductor device in which a semiconductor integrated circuit (Large-Scale Integrated Circuit; LSI) is formed, FIG. As described above, the power source for exploration is connected to the electrode pads 7 (7-1 to 7-8) for external connection provided in the semiconductor device, the electric signals are supplied, and the input / output of the signal at the terminal is performed by an LSI tester or the like. There is a way to measure.
[0003]
For these analyses, the circuit block configuration and the circuit pattern itself are observed from the surface of the semiconductor device using a shape recognition device such as an optical microscope, and the electrode pad 7 is further advanced using an electron beam tester or the like. There is a method of observing a potential signal that does not appear on the wiring inside the integrated circuit.
Therefore, in the current IC card 13, it is possible to open and dissect the IC module 11, read the information in the IC chip 12, analyze the contents of the memory, and tamper with it, which is a problem from the viewpoint of security. .
[0004]
FIG. 12 shows a configuration example of the IC module 11 in the current IC card 13, in which (a) is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on the IC card 13, (b) ) Is a sectional view, and (c) is a sectional view showing an example of mounting an IC module.
As shown in FIG. 12C, the IC module 11 is mounted on the IC card 13 having a card thickness of 0.76 mm by a hot melt adhesive 34. In this case, in the IC module 11, the IC chip 12 is die-bonded to the glass epoxy substrate 36 on which the contact pattern 35 corresponding to the electrode of the contact type IC card is formed, and the external connection electrode pad 7 and each contact pattern are connected by the gold wire 37. 35 is wire-bonded and then sealed with a mold resin 38.
[0005]
As shown in FIG. 12A, on the IC chip 12, a data memory (configured by an EEPROM or a ferroelectric memory element) 14 storing particularly important information such as an encryption code and an authentication code, And a peripheral circuit 15 including a voltage booster circuit for writing / erasing the same, a read-only program memory (composed of a ROM, etc.) 16, a central processing unit (CPU) 17 for performing calculation and control, for temporary storage A random access memory (RAM) 18 and a security authentication microprocessor (MPU) 19 are formed. In addition, a data bus and power supply electrode wiring (not shown) are provided around these.
[0006]
The data memory 14, the program memory 16 and the authentication microprocessor 19 mounted on the IC card 13 have various important functions such as a protocol necessary for communication, an authentication number code, a usage amount, and a remaining frequency. Data is stored.
Therefore, it is necessary to prevent these codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, from being read by a third party from the viewpoint of preventing counterfeiting / tampering of the IC card. is there.
[0007]
However, in the semiconductor device as shown in FIG. 12, the arrangement of the functional element circuit, the data memory 14, the program memory 16, and the authentication microprocessor 19 can be seen by observing from above, starting from the upper part, In addition, by probing measurement using an electron beam, it was possible to easily read out the contents of the memory element, or to cause the authentication microprocessor 19 to run out of control to cause a malfunction, thereby skipping the authentication process itself.
[0008]
Therefore, in order to prevent optical observation from above, in recent high-density mounting technology, bump electrodes for obtaining electrical connection on the element surface side of the semiconductor integrated circuit of the IC chip are formed. Flip chip mounting is often employed in which the IC chip is turned over and connected to a mounting substrate (electrode base) on which a contact electrode for external connection is formed.
[0009]
However, a technique for observing a circuit in the vicinity of the surface of the semiconductor substrate in a non-destructive manner from the back surface of the semiconductor substrate on which the semiconductor integrated circuit is formed has been developed in response to a request for failure analysis technology and the like.
In this technique, infrared light having a wavelength that is difficult to be absorbed by the semiconductor substrate is used as an observation light source, thereby increasing the transparency of the semiconductor substrate and observing a wiring pattern made mainly of metal from the back side of the semiconductor substrate. Thereby, the pattern of the lowermost transistor and the wiring pattern of the first layer can be observed nondestructively.
[0010]
In the flip chip mounting method, since the back surface of the chip is exposed to the outside, pattern observation from the back surface side rather than the element surface side of the IC chip 12 becomes easy. Of course, in the case of flip chip mounting, the back surface of the IC chip is coated with an epoxy resin film for chip protection. However, since these can be easily removed by using chemicals, it is difficult to prevent pattern observation from the back side by the protective film.
[0011]
Therefore, as one method for solving the above problem, the authors have self-blocking optical observation from the back surface by incorporating a thin power supply source and mounting the thin power supply source on the back surface of the IC chip. A destructive semiconductor device was proposed (Japanese Patent Application No. 10-110527).
FIG. 13 shows a basic circuit block diagram of the self-destructive semiconductor device. As shown in FIG. 12 described above, the semiconductor integrated circuit 1 on the semiconductor substrate 9 includes a data memory 14, a program memory 16, a central processing unit 17, a random access memory 18, an authentication memory necessary for the original IC card function. A microprocessor 19 is formed, but is omitted here.
[0012]
In this configuration, in addition to the above configuration, a destruction circuit that destroys memory information or a destruction circuit in which a fuse / antifuse is provided in the signal wiring path is added as the destruction circuit 2. Are formed with a destruction capacitor 3, a control circuit or element 4, and a voltage change detection circuit 5.
A thin power supply source 6 is connected to a terminal 10 whose terminal voltage is constantly monitored by the voltage change detection circuit 5.
[0013]
As a power source for driving the destruction circuit 2, charges accumulated in the large-capacity destruction capacitor 3 formed on the semiconductor substrate 9 are used. A power supply source 6 is connected to the capacitor 3 through a control circuit or an element 4 in a normal operation state, and an output voltage of the power supply source 6 is constantly changed by a capacitive coupling voltage change detection circuit 5. Being monitored.
When a third party takes off the power supply source 6 for the purpose of falsifying the IC chip 12, the voltage change is detected by the capacitive coupling voltage change detection circuit 5, and the detection from the voltage change detection circuit 5 is detected. The electric power of the destruction capacitor 3 is applied to the destruction circuit 2 through the control circuit or the element 4 which is turned on by the signal. For this reason, the memory information of the semiconductor integrated circuit 1 to be tampered with is destroyed.
[0014]
FIG. 14 shows the basic configuration of the self-destructive semiconductor device, wherein (a) is a plan view and (b) is a cross-sectional view.
The semiconductor substrate 9 on which the self-destructive IC chip 12 is formed has two electrode pads 10 for connecting to the power supply source 6 in addition to the eight electrode pads 7 necessary for the operation as the IC card 13. (Contact pair) has been added. The thin power supply source 6 is formed by a laminated structure of a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector / terminal plate 25 as shown in FIG. The periphery is thermally sealed by a sealing material 26.
The power supply source connection lead 28 and the power supply source connection electrode pad 10 are connected by a bump 27.
[0015]
As a method for mounting the power supply source 6, as shown in FIG. 14A, it can be arranged in parallel with the IC chip 12.
However, when face-down flip-chip mounting in which the front side is shielded by the electrode substrate is mounted on the back side via an adhesive film 20 as shown in FIG. It is preferable. Thereby, the back surface side can be optically shielded.
[0016]
[Problems to be solved by the invention]
In the case of the mounting method as shown in FIG. 14B, the thin power supply source 6 is connected to the two connection terminals 10 of the self-destructing circuit via the positive electrode lead and the negative electrode lead 28.
However, with such a connection method, the connection terminal 10 and the lead 28 can be easily clarified by a third party. A third party can expose the back surface of the IC chip 12 without disconnecting the power supply source 6 by chemically removing the adhesive film 20 and then bending the connection leads 28 of the power supply source 6. Is possible. In fact, when a thin lithium battery is used as the power supply source 6, the thickness of the battery is about 0.1 mm, the length and width of the battery are about 1 cm, and the thickness of the connection lead 28 is about 0.03 mm. Is possible. In this case, since the optical shielding by the power supply source 6 is removed without detecting the voltage change by the voltage change detection circuit 5, the self-destructive mechanism does not operate and important information is analyzed from the back surface of the IC chip. There was a problem of being done.
The present invention has been made to solve the above problems, and provides a self-destructive semiconductor device capable of optically shielding an important part of a semiconductor integrated circuit and reliably preventing tampering of memory contents of the semiconductor integrated circuit. The purpose is to provide.
[0017]
[Means for Solving the Problems]
  The self-destructive semiconductor device according to the present invention has a plurality of positive and negative connection leads 28 (n; n is2A destruction circuit 2 having power supply sources 6a and 6b each having an integer) and performing self-destruction by destroying at least part of memory information of the semiconductor integrated circuit 12a or disconnecting at least part of signal wiring. And a plurality of (n) destructive capacitors 3 for storing charges for self-destructing by the destructive circuit, and a plurality (n) for each of the positive and negative electrodes of the power supply source for accumulating charges in the destructive capacitors. Provided power supply source connection terminal 10 and positive and negative electrode terminalsA pair of terminals for connecting the power supply sourceA plurality of (n) voltage change detection circuits 5-1 to 5-n that monitor the voltage between the terminals of the terminal pair and output a detection signal in response to the voltage drop;SaidVia the power supply source connection terminalSaidPower supply andSaidConnect a destructive capacitor and at least oneSaidFrom voltage change detection circuitSaidIf a detection signal is output, disconnect the connection above.SaidDestruction capacitor andSaidA control circuit or element 4a for connecting a destruction circuit is provided on the semiconductor substrate 9a, and the back surface of the semiconductor integrated circuit is optically shielded.And when removing this optical shield, it is necessary to remove the connection lead of the power supply source from the power supply source connection terminal,The power supply sources 6a and 6b are arranged on the back side of the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed.
  The power supply sources 6a and 6b are thin power supply sources configured by stacking, for example, a positive electrode current collector, a positive electrode, a solid electrolyte, a negative electrode, and a negative electrode current collector.
  The destruction circuit 2 applies the electric charge accumulated in the destruction capacitor to at least one word line, thereby erasing a part of data bits stored in the nonvolatile memory element and destroying the memory contents. The breakdown circuit 2 is formed by providing a fuse or an antifuse in a part signal wiring path of the semiconductor integrated circuit, and applying a charge accumulated in the breakdown capacitor to the fuse or the antifuse. Destroy the signal wiring path.
  The control circuit or element 4a is composed of one or more semiconductor elements or micromechanical switches with capacitance termination.
  The voltage change detection circuits 5-1 to 5-n are composed of a first capacitor, a second capacitor, and a first resistor connected in series, and the connection terminal voltages applied to both ends of the first and second capacitors are connected to the first and second capacitors. A voltage divider that outputs a divided voltage from the connection point of the capacitor, and the divided output of the voltage divider is connected to the gate electrode and the source electrodeTo driveA field effect transistor to which a dynamic capacitor is connected; and a voltage change detection unit comprising a second resistor connected to the drain electrode of the field effect transistor. The voltage at which the transistor is turned off is divided and output, and the voltage at which the field-effect transistor is turned on is divided from the voltage-divided output and the field-effect transistor is turned on as the connection terminal voltage decreases.DesperateThe charge from the dynamic capacitor is supplied to the second resistor, and a detection signal is output in accordance with the increase in the voltage across the second resistor.
  In the present invention, the power supply sources 6a and 6b are each provided with a plurality of positive and negative connection leads 28, and the semiconductor integrated circuits 12a and 12b have the connection terminals 10 connected to the power supply source as positive and negative electrodes. A plurality of voltage change detection circuits 5-1 to 5-n are provided for each pair of positive and negative connection terminals to constantly monitor the voltage between the terminals. If the power supply sources 6a and 6b are to be removed in order to alter the memory contents of the semiconductor integrated circuit, it is necessary to remove a plurality of pairs (n pairs) of contacts. A voltage drop is detected by the voltage change detection circuit. The control circuit or the element 4a is turned on by this detection signal, and the destruction circuit 2 and the destruction capacitor 3 are connected. Thereby, the electric charge accumulated in the capacitor 3 is applied to the destruction circuit 2. For this reason, partial wiring or essential memory data of the integrated circuit to be tampered with is destroyed, so that tampering is impossible.
[0018]
  Further, as described in claim 2 (FIG. 7), a plurality of connection leads 28 for positive and negative electrodes (n; n is2A destruction circuit 2 having power supply sources 6a and 6b each including an integer) and performing self-destruction by destroying at least part of memory information of the semiconductor integrated circuit 12b or disconnecting at least part of signal wiring. And a plurality of (n) destructive capacitors 3 for storing charges for self-destructing by the destructive circuit, and a plurality (n) for each of the positive and negative electrodes of the power supply source for accumulating charges in the destructive capacitors. Provided power supply source connection terminal 10;Of these power supply source connection terminals,A voltage dividing circuit 8 for dividing a voltage between one power supply source connecting terminal for each of the positive electrode and the negative electrode;SaidProvided for each power supply source connection terminal and for negative electrodeSaidProvided for each power supply source connection terminal,SaidPower supply source connection terminalSaidVoltage between terminals of output terminal of voltage divider circuit or negative electrodeSaidPower supply source connection terminalSaidA plurality of (2n) voltage change detection circuits 5-1 to 5-2n that monitor the voltage between the output terminals of the voltage dividing circuit and output a detection signal in response to the voltage drop;SaidVia the power supply source connection terminalSaidPower supply andSaidConnect a destructive capacitor and at least oneSaidFrom voltage change detection circuitSaidIf a detection signal is output, disconnect the connection above.SaidDestruction capacitor andSaidA control circuit or element 4b for connecting a destruction circuit is provided on the semiconductor substrate 9b, and the back surface of the semiconductor integrated circuit is optically shielded.And when removing this optical shield, it is necessary to remove the connection lead of the power supply source from the power supply source connection terminal,The power supply sources 6a and 6b are arranged on the back side of the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed.
  As described above, the power supply sources 6a and 6b are each provided with a plurality of positive and negative connection leads 28, and the semiconductor integrated circuits 12a and 12b are provided with a plurality of power supply source connection terminals 10 for the positive and negative electrodes. The voltage change detection circuits 5-1 to 5-2n are provided for each of the positive power supply source connection terminals and the negative power supply source connection terminals, and the voltages between the terminals are constantly monitored. If the power supply sources 6a and 6b are to be removed in order to alter the memory contents of the semiconductor integrated circuit, it is necessary to remove a plurality of pairs (n pairs) of contacts. A voltage drop is detected by the voltage change detection circuit. The control circuit or the element 4b is turned on by this detection signal, and the destruction circuit 2 and the destruction capacitor 3 are connected. Thereby, the electric charge accumulated in the capacitor 3 is applied to the destruction circuit 2. For this reason, partial wiring or essential memory data of the integrated circuit to be tampered with is destroyed, so that tampering is impossible.
[0019]
  Further, as described in claim 3 (FIG. 6), the power supply sources 6a and 6b each including a plurality of (n + 1; n is an integer of 1 or more) connection leads 28 for positive and negative electrodes are provided, A destruction circuit 2 that self-destructs by destroying at least a part of memory information of the semiconductor integrated circuit 12b or disconnecting at least a part of signal wiring, and a charge for self-destruction by the destruction circuit are stored. A destruction capacitor 3, and a plurality of (n + 1) power supply source connection terminals 10 respectively provided for the positive electrode and the negative electrode of the power supply source for accumulating charges in the destruction capacitor;Of these power supply source connection terminals,One each for positive and negative electrodesFirstA voltage dividing circuit 8 for dividing a voltage between the power supply source connection terminals;Among the power supply source connection terminals provided for each of the positive electrode and the negative electrode,For positive electrode without voltage dividerSecondProvided for each power supply source connection terminalThe voltage divider circuit is not connectedFor negative electrodeSecondProvided for each power supply source connection terminal,The secondPower supply source connection terminalSaidVoltage between terminals of output terminal of voltage divider circuit or negative electrodeThe secondPower supply source connection terminalSaidA plurality of (2n) voltage change detection circuits 5-1 to 5-2n that monitor the voltage between the output terminals of the voltage dividing circuit and output a detection signal in response to the voltage drop;The secondVia the power supply source connection terminalSaidPower supply andSaidConnect a destructive capacitor and at least oneSaidFrom voltage change detection circuitSaidIf a detection signal is output, disconnect the connection above.SaidDestruction capacitor andSaidA control circuit or element 4b for connecting a destruction circuit is provided on the semiconductor substrate 9b, and the back surface of the semiconductor integrated circuit is optically shielded.And when removing this optical shield, it is necessary to remove the connection lead of the power supply source from the first and second power supply source connection terminals.The power supply sources 6a and 6b are arranged on the back side of the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed.
[0020]
  Further, as described in claim 4,In addition, the firstAn electrode base 32 for mounting the semiconductor substrate on which external connection terminals 62-1 to 62-8 are formed;The semiconductor substrate has a second external connection terminal formed on the element surface side,The power supply source 6a includes the connection leads 28 at the end portions in a plurality of directions including at least both opposing ends.SaidAround the edges of the semiconductor substrates 9a and 9bSaidConnected to the power supply source connection terminal 10 formed on the element surface side of the semiconductor substrates 9a, 9b;SaidThe element surfaces of the semiconductor substrates 9a and 9bSaidIn order to face the electrode base 32,SaidOf the semiconductor substrates 9a, 9bThe secondExternal connection terminals 7-1 to 7-8 andSaidOf the electrode substrate 32The firstThe external connection terminals 62-1 to 62-8 are connected.
  In this way, the semiconductor integrated circuits 12a and 12b (semiconductor substrates 9a and 9b) are flip-chip mounted on the electrode base 32. Moreover, since the power supply source 6a includes the connection leads 28 at the end portions in a plurality of directions including at least both opposing ends, the connection leads 28 are end portions in the plurality of directions including at least both ends of the semiconductor substrates 9a and 9b. Connected with the part. For this reason, it becomes difficult to bend the connection lead of the power supply source and remove the optical shielding by the power supply source as in the prior art.
[0021]
  Further, as described in claim 5,In addition, the firstExternal connection terminals 62-1 to 62-8 and,Multiple for each of positive electrode and negative electrode (2nN is an integer of 2 or more) Piece by pieceThirdPower supply source connection terminal 63And a plurality of fourth power supply source connection terminals for positive and negative electrodes connected to each of the third power supply source connection terminals.64, and an electrode base 32a for mounting the semiconductor substrate,The semiconductor substrate has a second external connection terminal formed on the element surface side,The element surfaces of the semiconductor substrates 9a and 9bSaidTo face the electrode base 32a,SaidOf the semiconductor substrates 9a, 9bThe secondExternal connection terminals 7-1 to 7-8 andSaidOf the electrode substrate 32aThe firstWhile connecting the external connection terminals 62-1 to 62-8,Said2 formed on the element surface side of the semiconductor substrates 9a and 9b.nofSaidPower supply source connection terminal 10 andSaid2 of electrode base 32anofThe thirdA power supply source connection terminal 63 is connected, and the power supply sources 6a and 6b are provided with the connection leads 28 at end portions in a plurality of directions including at least opposite ends.Said2 of electrode base 32anofThe fourthThe power supply source connection terminal 64 is connected.
  In this way, the semiconductor integrated circuits 12a and 12b (semiconductor substrates 9a and 9b) are flip-chip mounted on the electrode base 32a, and the power supply source 6b is connected to the semiconductor integrated circuits 12a and 12b via the electrode pads 63 and 64 of the electrode base 32a. (Semiconductor substrates 9a and 9b) are connected. As a result, the self-destruction mechanism is activated regardless of whether the power supply source 6b or the electrode base 32a is removed.
  The self-destructive semiconductor device according to the present invention further includes an electrode base for mounting the semiconductor substrate on which the first external connection terminal is formed, as defined in claim 6. The semiconductor substrate has a second external connection terminal formed on the element surface side, and the power supply source includes the connection lead at a plurality of end portions including at least opposite end portions. The lead is connected to the first and second power supply source connection terminals formed on the element surface side of the semiconductor substrate so as to go around the end of the semiconductor substrate, and the element surface of the semiconductor substrate and the electrode The second external connection terminal of the semiconductor substrate and the first external connection terminal of the electrode base are connected so that the base faces each other.
  The self-destructive semiconductor device according to the present invention is further characterized in that, as described in claim 7, the first external connection terminal and a plurality of positive and negative electrodes each (2 × (n + 1); n is 1 or more) (Integer) third power supply source connection terminals, and a plurality of (2 × (n + 1)) fourth positive and negative electrode fourth terminals connected to each of the third power supply source connection terminals. And an electrode base for mounting the semiconductor substrate, and the semiconductor substrate has a second external connection terminal formed on the element surface side. And connecting the second external connection terminal of the semiconductor substrate and the first external connection terminal of the electrode base so that the element surface of the semiconductor substrate and the electrode base face each other. For connecting the first and second power supply sources formed on the element surface side of the semiconductor substrate A terminal and the third power supply source connection terminal of the electrode base, wherein the power supply source includes the connection lead at a plurality of ends including at least opposite ends, the connection lead being The fourth power supply source connection terminal of the electrode base is connected.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block configuration diagram of a self-destructive semiconductor device showing a first embodiment of the present invention, FIG. 2A is a bottom view showing an arrangement configuration example of the self-destructive semiconductor device of FIG. 2B is a cross-sectional view taken along the line AA in FIG. 2A, and FIG. 2C is a side view of the self-destructive semiconductor device. The same reference numerals are given to the same components as those in FIGS. It is attached.
2A and 2B show a state before flip chip mounting described later, and in FIG. 2C, the mold resin 38, the anisotropic conductive adhesive resin 61, and the electrode substrate 32 are shown. See through.
[0023]
On the semiconductor substrate 9a, as a semiconductor integrated circuit 1 necessary for an original IC card function, a nonvolatile data memory (EEPROM or ferroelectric memory element) storing particularly important information such as an encryption code and an authentication code 14), a peripheral circuit 15 including a voltage booster circuit for writing / erasing the same, a read-only program memory (configured by ROM, etc.) 16, a central processing unit (CPU) for performing calculation and control ) 17, a random access memory (RAM) 18 as a temporary storage memory, and a security authentication microprocessor (MPU) 19 are formed.
[0024]
In the present invention, in addition to the above configuration, as the destruction circuit 2, a destruction circuit for destroying memory information or a destruction circuit provided with a fuse / antifuse in the signal wiring path is added on the semiconductor substrate 9a. , A destruction capacitor 3, a control circuit or element 4a, and voltage change detection circuits 5-1 to 5-n are added. Thus, the self-destructive IC chip 12a is configured.
[0025]
Here, the destruction circuit 2 will be described with reference to a specific example. For example, when a flash EEPROM is used for the data memory 14, a voltage of 12 to 15 V is required to erase the memory information, and an erasing booster circuit that generates such a high voltage is a data memory. 14 peripheral circuits 15 are formed.
[0026]
When the current lithium primary battery is used as the power supply source 6a, the output voltage is 3.6 V and the thickness is 0.1 mm. In this case, the power supply source 6a is connected in series and several layers are stacked to generate a required voltage, and the electric power is stored in the breakdown capacitor 3 by this power. Further, the power supply source 6a is not limited to a lithium battery, and may be a paper battery or the like.
[0027]
In a flash EEPROM, when a voltage of 12 to 15 V is applied in a pulse manner to a word line consisting of a control gate made of two-layer polysilicon, electrons are injected from the substrate into the capacitively coupled floating gate electrode, Bits are equally rewritten as “1” or “0”. Thus, the memory information can be destroyed.
[0028]
Further, when a ferroelectric memory element is used for the data memory 14, the erasing voltage is as low as about 5V. Therefore, a large-capacity electric charge is accumulated from two or more power supply sources 6a connected in series. It is also possible to configure the destruction circuit 2 more simply, for example, by directly connecting the destruction capacitor 3.
[0029]
In any case, in the present invention, the electric charge stored in the large-capacity destruction capacitor 3 formed on the semiconductor substrate 9a is used as a power supply source for driving the destruction circuit 2. The breakdown capacitor 3 includes a thermal oxide film (Si0) formed on the semiconductor substrate 9a.₂) Is used as an insulating film, and it is desirable to have a large capacity.
This is because, in the case of a thermal oxide film, features such as extremely low leakage current can be used, and a large amount of charge can be accumulated in the capacitor 3 by the thin power supply source 6a having a small energy density, and energy consumption due to leakage is reduced. This is because it can be reduced.
[0030]
  As shown in FIG. 2, a thin power supply source 6a for accumulating electric charge in the breakdown capacitor 3 includes a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector. It is formed by the laminated structure of the terminal board 25, and its periphery is thermally welded and sealed with a sealing material 26.
  The power supply source 6a has 2n connection leads 28 (n is2The above integer), that is, n positive leads connected to the terminal plate 21 and n negative leads connected to the terminal plate 25 are provided.
[0031]
On the other hand, the semiconductor substrate 9a on which the IC chip 12a is formed has a power supply source 6a in addition to the eight external connection electrode pads 7 (7-1 to 7-8) necessary for the operation as an IC card. 2n electrode pads 10 for connection to the power supply source 6a, that is, n for the positive lead of the power supply source 6a and n for the negative lead are added to realize multi-contact with the power supply source 6a.
[0032]
Capacitive coupling voltage change detection circuits 5-1 to 5-n are provided for each electrode pad pair including one electrode pad 10 for each of positive electrode and negative electrode, and at least n breakdown capacitors 3 are also provided. Yes. The voltage change detection circuits 5-1 to 5-n monitor the voltage of the corresponding electrode pad pair, that is, the output voltage of the power supply source 6a as needed.
[0033]
The control circuit or element 4a includes an OR logic circuit 29 that takes a logical sum of detection signals output from the voltage change detection circuits 5-1 to 5-n, and 2n pieces using the output of the OR logic circuit 29 as a control input. Switch 30.
[0034]
In the normal operation state, the positive electrode of the power supply source 6a is connected to one end of the destruction capacitor 3 via the positive electrode pad 10 and the switch 30. Similarly, the negative electrode of the power supply source 6a is connected to the negative electrode pad 10. The other end of the destruction capacitor 3 is connected via the switch 30.
[0035]
Here, the mounting method of the present embodiment will be briefly described.
First, bumps 27 made of gold (Au) or the like are formed on the external connection electrode pads 7-1 to 7-8 and the power supply source connection electrode pad 10 on the IC chip 12a.
The power supply source 6a is adhered to the back surface of the IC chip 12a opposite to the element surface (the paper surface in FIG. 2A, the bottom surface in FIG. 2C) by the adhesive film 20. The connection leads 28 of the power supply source 6 a and the power supply source connection electrode pads 10 of the IC chip 12 a are connected by the bumps 27.
[0036]
With the self-destruction mechanism activated, the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are formed on the electrode base 32 by the flip chip mounting technique. Is connected to the contact pattern 35 (35-1 to 35-8).
[0037]
FIG. 3 is a diagram showing a state of flip chip mounting in which the IC chip 12a is mounted on the electrode substrate 32. FIG.
External connection electrode pads 62-1 to 62-8 corresponding to the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are formed on the IC chip mounting surface of the electrode base 32 made of glass epoxy. Yes. The electrode pads 62-1 to 62-8 are connected to the contact patterns 35-1 to 35-8 through through holes or the like, respectively.
[0038]
In order to perform the flip chip mounting, first, the anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of the electrode base 32. The amount of the anisotropic conductive adhesive resin 61 is about 1/2 to 1/3 of the volume of the IC chip 12a. This amount is preferably in a state where the resin 61 is blown to the side surface of the chip in the final mounting shape.
[0039]
When the area of the IC chip 12a is small, it may be applied to the element surface of the IC chip 12a.
Next, the element surface of the IC chip 12a and the IC chip mounting surface of the electrode base 32 face each other, and the external connection electrode pads 7-1 to 7-8 of the IC chip 12a and the external connection electrode pad 62- of the electrode base 32 The electrode pads 7-1 to 7-8 and the electrode pads 62-1 to 62-8 are aligned so as to be connected to 1 to 62-8, and pressure is applied from the back surface of the IC chip 12a.
[0040]
Pressurization has two purposes. The first purpose is to align the element surface of the IC chip 12a and the IC chip mounting surface of the electrode base 32, and pressurize and crush the bumps 27 (plastic deformation) to absorb variations in the height of the bumps 27. That is.
[0041]
The second purpose exists between the electrode pads 62-1 to 62-8 formed on the electrode substrate 32 and the bumps 27 formed on the electrode pads 7-1 to 7-8 of the IC chip 12a. The anisotropic conductive adhesive resin 61 is extruded to electrically connect the electrode pads 62-1 to 62-8 and the electrode pads 7-1 to 7-8 via the bumps 27.
[0042]
Next, the anisotropic conductive adhesive resin 61 is cured in a state where the pressure is applied as described above.
The anisotropic conductive adhesive resin 61 is formed on the electrode pads 62-1 to 62-8 formed on the electrode base 32 and the electrode pads 7-1 to 7-8 of the IC chip 12a by shrinkage during curing. For this purpose, the anisotropic conductive adhesive resin 61 needs to have a characteristic that satisfies the following condition.
[0043]
α, β> ω> ρ (1)
Here, α is the adhesive force between the IC chip 12a and the anisotropic conductive adhesive resin 61, β is the adhesive force between the electrode substrate 32 and the anisotropic conductive adhesive resin 61, and ω is the curing of the anisotropic conductive adhesive resin 61. The shrinkage at time, ρ, represents the thermal stress of the anisotropic conductive adhesive resin 61 itself.
[0044]
When the anisotropic conductive adhesive resin 61 has photocurability, the resin 61 is cured by irradiating with ultraviolet rays.
When the photocurable resin 61 is used, since the electrode base 32 is opaque, the ultraviolet rays are irradiated from the side surfaces of the IC chip 12a and the power supply source 6a to be cured from the resin 61 on the side surface of the chip. The resin 61 is naturally cured (normal temperature curing).
[0045]
When the anisotropic conductive adhesive resin 61 has thermosetting properties, the resin 61 is cured by heating.
However, when a thin lithium battery in which conduction of lithium ions in the solid electrolyte 23 is an electromotive force is used as the power supply source 6a, if the heating is continued for a long time at a high temperature of 70 ° C. or higher, the power supply source 6a Since it causes deterioration, it is not preferable. That is, the specification of the thermosetting resin 61 that can be used in this case must have a property of curing at 70 ° C. or lower.
[0046]
Therefore, it is preferable for the present embodiment in which the power supply source 6a and the IC chip 12a are mounted as an integrated structure to use the photocurable resin 61 that is cured at room temperature by ultraviolet irradiation.
If the photo-curing anisotropic conductive adhesive resin 61 is used, it is not necessary to apply heat at the time of connection to cure it, and it is not necessary to apply excessive thermal stress to the IC chip 12a or the electrode substrate 32, and power generated by heating. The destruction of the supply source 6a can be avoided.
[0047]
When the anisotropic conductive adhesive resin 61 has been cured, the pressurization is stopped. Thus, the electrical connection between the IC chip 12a and the contact patterns 35-1 to 35-8 and the mechanical holding of the IC chip 12a by the electrode base 32 are completed.
The IC module 11a thus mounted is sealed with the mold resin 38 as shown in FIG. 2C, and is mounted on the plastic case of the IC card with a hot melt adhesive as in FIG.
[0048]
The power supply source 6a supplies power to the breakdown circuit 2, the breakdown capacitor 3, the control circuit or element 4a, and the voltage change detection circuits 5-1 to 5-n, and is a semiconductor excluding the breakdown circuit 2. Electric power is supplied to the integrated circuit 1 from the outside via the power supply terminal of the external connection electrode pad 7.
[0049]
A third party who intends to tamper with the IC chip 12a first removes the IC module 11a from the plastic case, and then removes the mold resin 38 using a chemical. Then, in order to perform observation from the back surface of the IC chip 12a, it is necessary to remove the power supply source 6a mounted on the back surface of the IC chip 12a. In the present embodiment, the power supply source 6a and the IC chip 12a are separated from each other. Are connected to the positive and negative electrode n pairs of connection leads 28 by the electrode pad 10, and when any one of these connections is removed, the voltage change detection circuits 5-1 to 5- The voltage change is detected by any of n.
[0050]
When voltage change detection circuits 5-1 to 5-n detect a voltage change and output a detection signal, this detection signal is applied to the control input of switch 30 via OR logic circuit 29. As a result, the switch 30 switches to the side where the destruction capacitor 3 and the destruction circuit 2 are connected, and the electric power of the destruction capacitor 3 is applied to the destruction circuit 2.
Thus, the self-destruction mechanism is activated and the memory information of the semiconductor integrated circuit 1 is destroyed.
[0051]
The level of memory destruction is determined by cutting a fuse or antifuse built in a signal wiring path in an integrated circuit from a level at which memory information is simply erased according to the voltage of the power supply source 6a. There is a possibility of destroying 1 itself.
[0052]
For example, if one thin lithium primary battery is assumed as the power supply source 6a, the output voltage due to the electric charge accumulated in the breakdown capacitor 3 is about 3.6 V at most, and the breakdown circuit 2 executes only one. It is only about erasing the partial memory information. In this case, since the important confidential information is erased, the bit information of the memory is not leaked to a third party. However, the IC chip 12a that can operate normally remains. The IC chip 12a can be reused if the necessary bit information is obtained by another type of fraud and newly written.
[0053]
In order to avoid reuse of the IC chip 12a, it is necessary to surely destroy the semiconductor integrated circuit 1 to be tampered with.
In this case, a plurality of thin lithium primary batteries are connected in series and used as the power supply source 6a, so that the output voltage due to the electric charge accumulated in the breakdown capacitor 3 is increased by 3.6V × the number of stages of the battery. By causing a current to flow through a destruction circuit 2 including a fuse and an antifuse portion provided in the integrated circuit 1, a part of signal wiring of the semiconductor integrated circuit 1 is irreversibly destroyed, so that the IC chip 12a Avoid reuse.
[0054]
When the current lithium primary battery is used as the power supply source 6a, the thickness of the IC chip 12 is 0.05 mm and the battery thickness is 0.1 mm, so that the thickness of the IC card 13a does not exceed 0.76 mm. Therefore, even if five layers of lithium secondary batteries (3.6 × 5 = 18V) are stacked as the power supply source 6a, it can be accommodated in a total of about 0.55 mm (= 0.1 mm × 5 + 0.05 mm). It is.
[0055]
[Embodiment 2]
FIG. 4 is a bottom view showing an arrangement configuration example of the self-destructive semiconductor device according to the second embodiment of the present invention, FIG. 4B is a sectional view of the self-destructive semiconductor device, and FIG. 5 is flip-chip mounting. FIG. 4 is a diagram showing the state of FIG. 1, and the same components as those in FIGS. FIG. 4A shows a state before flip chip mounting.
[0056]
Also in this embodiment, the circuit block configuration of the self-destructive semiconductor device is the same as that in FIG.
Similarly to the first embodiment, the external connection electrode pads 62 corresponding to the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are provided on the IC chip mounting surface of the electrode base 32a of the present embodiment. -1 to 62-8 are formed, and the electrode pads 62-1 to 62-8 are connected to the contact patterns 35-1 to 35-8 through through holes or the like, respectively.
[0057]
Further, on the IC chip mounting surface of the electrode base 32a, 2n (n for positive and negative electrodes) power supply source connection electrodes corresponding to 2n power supply source connection electrode pads 10 of the IC chip 12a. The pads 63 are formed, and 2n power supply source connection electrode pads 64 corresponding to the 2n connection leads 28 of the power supply source 6b (n for the positive and negative leads) are formed.
Each electrode pad 63 is connected to a corresponding electrode pad 64 by wiring.
[0058]
Here, the mounting method of the present embodiment will be briefly described. In order to perform the flip chip mounting, the anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of the electrode base 32a as in the first embodiment.
[0059]
Subsequently, as shown in FIG. 5, the element surface of the IC chip 12a and the IC chip mounting surface of the electrode base 32a face each other, and the electrode pads 7-1 to 7-8 of the IC chip 12a and the electrode pads of the electrode base 32a 62-1 to 62-8 are connected to each other so that the electrode pads 10 of the IC chip 12a and the electrode pads 63 of the electrode base 32a are connected, and pressure is applied from the back surface of the IC chip 12a. I do.
[0060]
Next, in the state where pressure is applied, the anisotropic conductive adhesive resin 61 is cured as in the first embodiment, and when the curing of the resin 61 is completed, the pressurization is stopped.
In this way, the flip-chip mounting of the IC chip 12a and the electrode base 32a is performed using all four sides of the IC chip 12a.
[0061]
Next, the power supply source 6b is bonded to the back surface of the IC chip 12a flip-chip mounted on the electrode substrate 32a with the adhesive film 20.
The connection lead 28 of the power supply source 6b and the power supply source connection electrode pad 64 of the electrode base 32a are connected by a bump (not shown).
[0062]
Thus, the mounting method in the present embodiment is the same as that of the first embodiment except that the mounting order is different.
In the first embodiment, when a third party for the purpose of falsification of the IC chip 12a first removes the flip chip mounting interface side between the electrode base 32 and the IC chip 12a, the above self-destruction mechanism is not activated. The semiconductor integrated circuit may remain operable and important information may be analyzed.
[0063]
On the other hand, according to the present embodiment, the first problem of the embodiment can be avoided. That is, a third party for the purpose of falsifying the IC chip 12a cannot observe the back surface of the IC chip 12a unless the power supply source 6b is removed, and the third party of the IC chip 12a cannot be observed unless the electrode base 32a is removed. The element surface cannot be observed.
[0064]
In order to remove the power supply source 6b, it is necessary to remove the 2n connection leads 28 from the electrode base 32a. When any one of these connections is removed, the same as in the first embodiment. The self-destruction mechanism is activated and the memory information of the semiconductor integrated circuit 1 is destroyed.
[0065]
On the other hand, since the power supply source 6b is connected to the IC chip 12a via the electrode pads 63 and 64 of the electrode base 32a, removing the electrode base 32a is electrically the same as removing the power supply 6b. Thus, the self-destruction mechanism is activated and the memory information of the semiconductor integrated circuit 1 is destroyed.
That is, in this embodiment, the self-destruction mechanism is activated regardless of whether the power supply source 6b or the electrode base 32a is removed.
[0066]
[Embodiment 3]
In the first and second embodiments, the configuration shown in FIG. 1 is used as the circuit block configuration of the self-destructive semiconductor device, but another configuration may be used.
FIG. 6 is a circuit block configuration diagram of a self-destructive semiconductor device showing a third embodiment of the present invention. Components identical to those in FIG.
[0067]
In this embodiment, compared with 1 or 2 of the embodiment, the connection leads 28 for the positive electrode and the negative electrode of the power supply source 6a or 6b are respectively increased by one, and similarly, electrode pads for the positive electrode and the negative electrode 10 is increased by 1 each.
[0068]
For example, a voltage dividing circuit 8 in which two capacitors are connected in series is connected to the newly increased pair of electrode pads 10.
The voltage change detection circuits 5-1 to 5-n are provided for each positive electrode pad 10 to which the voltage dividing circuit 8 is not connected, and the voltage change detection circuits 5- (n + 1) to 5-2n are divided. The circuit 8 is provided for each negative electrode pad 10 not connected.
[0069]
One input of each voltage change detection circuit 5-1 to 5-2 n is connected to the output terminal of the voltage dividing circuit 8.
The control circuit or element 4b includes an OR logic circuit 29a that takes the logical sum of the detection signals output from the voltage change detection circuits 5-1 to 5-2n, and 2n circuits that use the output of the OR logic circuit 29a as a control input. Switch 30.
[0070]
Other configurations are the same as those in FIG. In the present embodiment, by connecting the power supply source 6b to the voltage dividing circuit 8, the ground potential is internally set to a potential different from that of the power supply source 6b, and this ground potential (the output of the voltage dividing circuit 8) is set. The voltage between the terminal potential) and the 2n electrode pads 10 can be individually detected by the capacitive coupling voltage change detection circuits 5-1 to 5-2n.
[0071]
Thus, the same effect as that of the first embodiment can be obtained. Although the present embodiment and the first embodiment are functionally the same, when considering the manufacturing process, for example, in the case of making a CMOS, it is easier to make a configuration like this embodiment. There is an effect.
[0072]
[Embodiment 4]
In the third embodiment, the number of connection leads 28 and electrode pads 10 is increased compared to the first and second embodiments, but the same number as the first embodiment may be used.
In this case, as shown in FIG. 7, the voltage dividing circuit 8 may be connected to any one of the positive electrode pads 10 and any one of the negative electrode pads 10.
[0073]
[Embodiment 5]
Next, a fifth embodiment of the present invention will be described with reference to FIG. In the present invention, the output voltages of the power supply sources 6a and 6b must be constantly monitored by the voltage change detection circuits 5-1 to 5-2n.
However, when a thin lithium battery is mounted as the power supply sources 6a and 6b, the capacity density is 1.5 mAh / cm.²Since it is as small as (single-stage cell, 0.1 mm), the battery life is extremely shortened in a circuit configuration in which a large current is constantly passed.
[0074]
Therefore, it is essential for the voltage change detection circuits 5-1 to 5-2n to have a capacitive coupling circuit configuration that does not match the leakage path with the current path related to the operation.
FIG. 8 shows an example of such a capacitively coupled voltage change detection circuit. In this embodiment, a MOS field effect transistor is used as the voltage change detection element.
[0075]
  The output voltage of the power supply sources 6a and 6b is a voltage dividing capacitor C₁, C₂And resistance R₁Is divided by the voltage dividing capacitor C.₁, C₂To the gate of the voltage change detecting transistor 31.
  Since the power consumption of the voltage change detection transistor 31 is very small,BreakThe voltage accumulated in the large-capacity driving capacitor provided separately from the destruction capacitor 3The driving voltage can be used.
[0076]
When a third party for the purpose of falsifying the IC card disconnects the power supply source 6a or 6b, the voltage divided by the capacity set near the threshold voltage of the transistor 31 fluctuates. Operates on.
In response to this, a current flows between the source and drain of the transistor 31, and the resistance R₂A voltage drop occurs between the two terminals. This voltage drop is output as a detection signal to the control circuit or the elements 4a and 4b via the post-stage amplifier circuit 33.
[0077]
[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described with reference to FIG. Since the capacity of the thin power supply sources 6a and 6b to be mounted is limited, it is desirable that the switch 30 in the control circuit or the elements 4a and 4b has as little power consumption as possible.
Normally, the switch 30 is generally a semiconductor switch configured by combining transistors, but in this case, it is a big problem to reduce power consumption due to subthreshold current leakage at the time of OFF.
[0078]
In the present invention, as such a low power consumption switch 30, it is also possible to use a micromechanical switch which is a kind of micro mechanical element having a movable part and which opens and closes contacts using electrostatic attraction.
FIG. 9 shows an example of a micromechanical switch that opens and closes a contact with such an electrostatic attractive force. In the figure, (a) is a sectional view and (b) is a plan view. FIG. 9 shows one switch 30.
[0079]
As shown in FIG. 9A, in the micromechanical switch, the movable suction electrode 47 is installed through the support beam 48 and the connection electrode 49a. When no voltage is applied to the fixed suction electrode 50, the movable contact electrode 51 is pressed against the fixed contact electrodes 52b and 52c by the elastic force (upward) of the support beam 48.
[0080]
As a result, the COMM input terminal 53 is electrically connected to the output 2 terminal 54b. The fixed contact electrodes 52b and 52c are supported by the contact electrode support portion 55, and are electrically connected to the COMM input terminal 53 and the output 2 terminal 54b through the connection electrodes 49b and 49c, respectively.
The movable contact electrode 51 is electrically insulated from the support beam 48 by the insulating film 57 and is mechanically fixed to the support beam 48.
[0081]
When a voltage is applied from the movable contact operating power supply terminal 56 to the fixed suction electrode 50, the support beam 48 is lowered by the electrostatic attractive force acting between the fixed suction electrode 50 and the movable suction electrode 47. Then, the movable contact electrode 51 is separated from the fixed contact electrodes 52b and 52c, and is pressed against the opposite fixed contact electrodes 52a and 52d.
As a result, the COMM input terminal 53 is electrically connected to the output 1 terminal 54a via the movable contact electrode 51.
[0082]
When the voltage application to the fixed suction electrode 50 is stopped, the movable contact electrode 51 moves upward by the elastic force of the support beam 48.
As a result, the movable contact electrode 51 is pressed again toward the fixed contact electrodes 52b and 52c, and the COMM input terminal 53 is electrically connected to the output 2 terminal 54b.
In this way, the current path is switched by the micromechanical switch.
[0083]
Although the OR logic circuit 29 is not shown in FIG. 9, the OR logic circuit 29 can be composed of a CMOS or the like, and its output may be connected to the movable contact operation power supply terminal 56.
Further, one end of the destruction capacitor 3 may be connected to the COMM input terminal 53, one end of the destruction circuit 2 may be connected to the output 1 terminal 54a, and the electrode pad 10 may be connected to the output 2 terminal 54b.
[0084]
[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described with reference to FIG. In the present invention, the configuration of the destruction circuit 2 is important for avoiding reuse of the IC chip 12a.
In the present invention, the function of the integrated circuit is surely destroyed by destroying a partial circuit including a fuse or an antifuse using the electric power stored in the destruction capacitor 3.
[0085]
As a circuit to be destroyed, as shown in FIG. 10, a ROM boot circuit reading circuit most important in the operation of the IC chip 12a is considered as an example. In FIG. 10A, the decoder input / output line portion of the address signal of the readout circuit, for example, the signal line C_A0, C_A1, C_A2, C_A3, R_A0, R_A1, R_A2, R_A3An anti-fuse 39 is provided in a part of this to constitute the destruction circuit 2.
[0086]
FIG. 10B shows a plane pattern diagram of the cell configuration in each cell portion.
The input / output of the row decoder 40 is performed via a polysilicon word line constituting the gate electrode of the cell transistor constituting each of the cells 100 to 133, and the bit line formed by the first layer Al is perpendicular to this. 43 (B₀, B₁, B₂, B_Three) Is running.
Here, the gate G of the row decoder 40_R1Signal I / O line R_A1The antifuse 39 (marked with “X” in the figure) made of a thin oxide film is provided in the portion.
[0087]
11A and 11B show the structure of the antifuse, where FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along line A-A ′.
As shown in FIG. 11B, normally, a polysilicon word line 42 runs on a P-type Si semiconductor substrate while being insulated by an element isolation insulating film (LOCOS) 46. The antifuse 39 does not form part of the element isolation insulating film 46, and after forming a thin gate oxide film 39a there, an N + diffusion layer 45 is provided by implanting phosphorus at a high concentration, and this is used as a ground. .
[0088]
When a voltage is applied to the polysilicon word line 42 running on the N + diffusion layer 45 insulated by the gate oxide film 39a from the large-capacity destructive capacitor 3 in which charges from the power supply source 6 are accumulated, the gate oxide film 39a is broken down, and the word line 42 is short-circuited with the substrate.
As a result, all the cells (cells 101, 111, 121, 131) addressed by the row decoder 40 using the word line 42 become unreadable, and reading of the ROM is reliably prevented.
[0089]
Note that when 8 nm is used as the thickness of the gate oxide film 39a, a high electric field of 20 MV / cm is required for the dielectric melt breakdown.
In this case, the voltage required for destruction is 16 V, and when a thin lithium secondary battery is used as the power supply source 6, 3.6 V × 5 stages = 18 V, so 4 to 5 stages are connected in series. By storing this power in the large-capacity destruction capacitor 3, sufficient destruction power can be obtained.
[0090]
Alternatively, signal input / output line R_A1As a part of the polysilicon word line 42 operating as a thin line, the part can be used as a fuse.
That is, a large current is supplied to the signal line from the large-capacity destruction capacitor 3 in which charges are accumulated, and the thinned portion of the polysilicon wiring is scattered by heat melting.
Thus, the signal input / output line R_A1By disconnecting the fuse portion provided in the middle of the circuit, the read circuit of the ROM boot circuit can be destroyed.
[0091]
In the above embodiment, an IC card is used as an example of a semiconductor device. However, when the present invention is applied to other than an IC card, for example, when an IC chip is arranged in a computer, the electrode bases 32 and 32a. Needless to say, it becomes a printed wiring board.
[0092]
In the above embodiment, the number of power supply source connection electrode pads 10, 63, 64 and the number of connection leads 28 is the same for the positive electrode and the negative electrode. However, the present invention is not limited to this. The number of positive electrodes and negative electrodes may be changed by providing electrode pads.
[0093]
【The invention's effect】
According to the present invention, as described in claims 1 to 3, since the power supply source and the semiconductor integrated circuit are connected by a plurality of pairs of connection leads and connection terminals for positive and negative electrodes, these If any one of the connections is removed, the voltage change is detected by any one of the plurality of voltage change detection circuits. Moreover, since the back surface of the semiconductor integrated circuit is optically shielded by the power supply source, optical observation of the back surface can be avoided. In particular, it is necessary to remove the power supply source used for shielding from the semiconductor integrated circuit for backside observation, but if a third party intended to tamper with the semiconductor integrated circuit attempts to remove the power supply source Thus, the destruction of the memory contents of the semiconductor integrated circuit can be surely prevented by the destruction of the memory information and the partial breakage of the signal wiring.
[0094]
According to a fourth aspect of the present invention, the back surface of the semiconductor integrated circuit is mounted by flip-chip mounting the semiconductor substrate (semiconductor integrated circuit) on the electrode base so that the element surface of the semiconductor substrate faces the electrode base. In addition, the element surface of the semiconductor integrated circuit can be optically shielded. In addition, since the power supply source is provided with connection leads at the ends in a plurality of directions including at least both ends facing each other, the connection leads are connected to the power supply sources arranged in a plurality of directions including at least both ends of the semiconductor substrate. Connected to the terminal. This makes it difficult to expose the back surface of the semiconductor integrated circuit without disconnecting the power supply source, so that the back surface observation of the semiconductor integrated circuit can be reliably prevented.
[0095]
Further, as described in claim 5, the back surface of the semiconductor integrated circuit is mounted by flip-chip mounting the semiconductor substrate (semiconductor integrated circuit) on the electrode substrate so that the element surface of the semiconductor substrate faces the electrode substrate. In addition, the element surface of the semiconductor integrated circuit can be optically shielded. In addition, since the power supply source is provided with connection leads at the ends in a plurality of directions including at least both ends facing each other, the connection leads are connected to the power supply sources arranged in a plurality of directions including at least both ends of the electrode substrate. Connected to the terminal. This makes it difficult to expose the back surface of the semiconductor integrated circuit without disconnecting the power supply source, so that the back surface observation of the semiconductor integrated circuit can be reliably prevented. In addition, since the power supply source is connected to the semiconductor substrate via the power supply source connection terminal of the electrode base, the self-destruction mechanism can be activated when either the power supply source or the electrode base is removed. , Security can be further improved.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of a self-destructive semiconductor device showing a first embodiment of the present invention.
2 is a bottom view, a cross-sectional view, and a side view showing an arrangement configuration example of the self-destructive semiconductor device of FIG. 1. FIG.
FIG. 3 is a diagram showing a state of flip chip mounting in the first embodiment of the present invention.
FIGS. 4A and 4B are a bottom view and a cross-sectional view showing an arrangement configuration example of a self-destructive semiconductor device showing a second embodiment of the present invention. FIGS.
FIG. 5 is a diagram showing a state of flip chip mounting according to a second embodiment of the present invention.
FIG. 6 is a circuit block diagram of a self-destructive semiconductor device showing a third embodiment of the present invention.
FIG. 7 is a circuit block diagram of a self-destructive semiconductor device showing a fourth embodiment of the present invention.
FIG. 8 is a circuit diagram illustrating a configuration example of a voltage change detection circuit according to a fifth embodiment of the present invention.
FIGS. 9A and 9B are a cross-sectional view and a plan view illustrating a configuration example of a control circuit or an element according to a sixth embodiment of the present invention. FIGS.
FIG. 10 is an explanatory diagram showing a configuration example of a destruction circuit using an antifuse according to a seventh embodiment of the present invention.
FIG. 11 is an explanatory diagram showing a configuration example of an antifuse.
FIG. 12 is an explanatory diagram showing a configuration example of a general IC card.
FIG. 13 is a circuit block diagram of a conventional self-destructive semiconductor device.
14 is a plan view and a cross-sectional view illustrating an arrangement configuration example of the self-destructive semiconductor device of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Destruction circuit, 3 ... Destruction capacitor, 4a, 4b ... Control circuit thru | or element, 5-1 to 5-2n ... Voltage change detection circuit, 6a, 6b ... Power supply source, 7-1 7-8 ... External connection electrode pads, 8 ... Voltage divider circuit, 9a, 9b ... Semiconductor substrate, 10 ... Power supply source connection electrode pads, 11a ... IC module, 12a, 12b ... IC chip, 14 ... Data memory 15 ... peripheral circuit, 16 ... program memory, 17 ... central processing unit, 18 ... random access memory, 19 ... authentication microprocessor, 20 ... adhesive film, 21 ... positive electrode current collector / terminal plate, 22 ... positive electrode, DESCRIPTION OF SYMBOLS 23 ... Solid electrolyte, 24 ... Negative electrode, 25 ... Negative electrode collector and terminal board, 26 ... Sealing material, 27 ... Bump, 28 ... Connection lead, 29, 29a ... OR logic circuit, 30 ... Switch, 32, 32 ... Electrode substrate, 35-1 to 35-8 ... Contact pattern, 38 ... Mold resin, 61 ... Anisotropic conductive adhesive resin, 62-1 to 62-8 ... External connection electrode pad, 63, 64 ... Power supply source Electrode pad for connection.

Claims (7)

In a semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate,
A power supply source having a plurality of connection leads for positive and negative electrodes, respectively,
A destruction circuit that self-destructs by destroying at least a part of memory information of the semiconductor integrated circuit or disconnecting at least a part of signal wiring; and
A destructive capacitor for storing charges for self-destruct by this destructive circuit;
A plurality of power supply source connection terminals provided for each of the positive and negative electrodes of the power supply source for accumulating electric charge in the destruction capacitor;
A plurality of voltage change detection circuits which are provided for each pair of the power supply source connection terminals for the positive electrode and the negative electrode, monitor the voltage between the terminals of the terminal pair and output a detection signal according to the voltage drop;
During normal operation connects the broken capacitor and the power supply source via the terminal the power supply connection, when the detection signal from at least one of the voltage change detecting circuit is output, block the connection having a control circuit to elements for connecting the fracture circuit and the breakdown capacitor in each said semiconductor substrate,
The back surface of the semiconductor integrated circuit is optically shielded , and when removing the optical shield, it is necessary to remove the connection lead of the power supply source from the power supply source connection terminal. self-destroying semiconductor device comprising placing a semiconductor integrated circuit wherein the power supply to the back side of the element surface of the semiconductor substrate which is formed. In a semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate,
A power supply source having a plurality of connection leads for positive and negative electrodes, respectively,
A destruction circuit that self-destructs by destroying at least a part of memory information of the semiconductor integrated circuit or disconnecting at least a part of signal wiring; and
A destructive capacitor for storing charges for self-destruct by this destructive circuit;
A plurality of power supply source connection terminals provided for each of the positive and negative electrodes of the power supply source for accumulating electric charge in the destruction capacitor;
Of these power sources connection terminal, a dividing circuit for dividing a voltage between the power supply connection terminal of each respective one for positive and negative electrodes,
Together provided to the power supply for each connection terminal for the positive electrode is provided to the power supply for each connection terminal for the negative electrode, the output terminal of the power supply connection terminal for the positive electrode and the voltage dividing circuit terminal and between the voltage or the power supply connection terminal for a negative electrode to monitor the terminal voltage of said divider output terminal, a plurality of the voltage change detecting circuit for outputting a detection signal in response to the voltage drop,
During normal operation connects the broken capacitor and the power supply source via the terminal the power supply connection, when the detection signal from at least one of the voltage change detecting circuit is output, block the connection having a control circuit to elements for connecting the fracture circuit and the breakdown capacitor in each said semiconductor substrate,
The back surface of the semiconductor integrated circuit is optically shielded , and when removing the optical shield, it is necessary to remove the connection lead of the power supply source from the power supply source connection terminal. self-destroying semiconductor device comprising placing a semiconductor integrated circuit wherein the power supply to the back side of the element surface of the semiconductor substrate which is formed. In a semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate,
A power supply source having a plurality of connection leads for positive and negative electrodes, respectively,
A destruction circuit that self-destructs by destroying at least a part of memory information of the semiconductor integrated circuit or disconnecting at least a part of signal wiring; and
A destructive capacitor for storing charges for self-destruct by this destructive circuit;
A plurality of power supply source connection terminals provided for each of the positive and negative electrodes of the power supply source for accumulating electric charge in the destruction capacitor;
Of these power supply source connection terminals, a voltage dividing circuit that divides the voltage between the first power supply source connection terminals, one for the positive electrode and one for the negative electrode,
The fraction with one of the positive electrode and the power supply connection terminals provided by a plurality respectively for the negative electrode, provided on the second power supply each connection terminal for the positive electrode, wherein the voltage dividing circuit is not connected pressure circuit is provided for each second terminal for power supply connection for the negative electrode which is not connected, the terminal voltage of the output terminal of the second power supply connection terminal for the positive electrode and the voltage dividing circuit or the second terminal voltage of the output terminal of said divider circuit and the power supply connection terminal for the negative electrode monitoring, a plurality of the voltage change detecting circuit for outputting a detection signal in response to the voltage drop,
During normal operation connects the broken capacitor and the power supply source via the second power supply connection terminal, when the detection signal from at least one of the voltage change detecting circuit is output, the and a control circuit to elements for connecting the fracture circuit and the breakdown capacitor blocks the connection has to each of the semiconductor substrate,
The back surface of the semiconductor integrated circuit is optically shielded , and when removing the optical shield, it is necessary to remove the connection lead of the power supply source from the first and second power supply source connection terminals. become such, the self-destroying semiconductor device, characterized by disposing the power supply on the back side of the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed. The self-destructive semiconductor device according to claim 1 or 2 ,
Furthermore, it has an electrode base for mounting the semiconductor substrate on which the first external connection terminal is formed,
The semiconductor substrate has a second external connection terminal formed on the element surface side,
Wherein the power source comprises the connecting lead to the end of the plurality of directions including at least the opposite ends, the connection leads are formed so as to go around the edge of the semiconductor substrate on the element surface side of the semiconductor substrate Connected to the power supply source connection terminal,
Wherein as the element surface of the semiconductor substrate and said electrode substrate is opposed, and characterized by connecting the first external connection terminal of the second external connection terminal and the electrode substrate of the semiconductor substrate Self-destructive semiconductor device. The self-destructive semiconductor device according to claim 1 or 2 ,
Furthermore, a first external connection terminal, a plurality of third power supply source connection terminals for positive and negative electrodes, and a positive electrode and a negative electrode connected to each of these third power supply source connection terminals A plurality of fourth power supply source connection terminals each having an electrode base for mounting the semiconductor substrate;
The semiconductor substrate has a second external connection terminal formed on the element surface side,
Wherein as the element surface of the semiconductor substrate and said electrode substrate are opposed together connecting the first external connection terminal of the second external connection terminal and the electrode substrate of the semiconductor substrate, the semiconductor and connecting the third terminals for power supply connection of the power supply connection terminal and the electrode substrate which is formed on the element surface side of the substrate,
Wherein the power source comprises the connecting lead to the end of the plurality of directions including at least the opposite ends, the connection lead to be connected to the fourth power supply connection terminal of the electrode substrate A self-destructive semiconductor device. The self-destructive semiconductor device according to claim 3,
Furthermore, it has an electrode base for mounting the semiconductor substrate on which the first external connection terminal is formed,
The semiconductor substrate has a second external connection terminal formed on the element surface side,
The power supply source includes the connection leads at end portions in a plurality of directions including at least opposite ends, and the connection leads are formed on the element surface side of the semiconductor substrate so as to go around the end of the semiconductor substrate. Connected to the first and second power supply source connection terminals,
The second external connection terminal of the semiconductor substrate and the first external connection terminal of the electrode base are connected so that the element surface of the semiconductor substrate faces the electrode base. A self-destructive semiconductor device. The self-destructive semiconductor device according to claim 3,
Furthermore, a first external connection terminal, a plurality of third power supply source connection terminals for positive and negative electrodes, and a positive electrode and a negative electrode connected to each of these third power supply source connection terminals A plurality of fourth power supply source connection terminals each having an electrode base for mounting the semiconductor substrate;
The semiconductor substrate has a second external connection terminal formed on the element surface side,
The second external connection terminal of the semiconductor substrate and the first external connection terminal of the electrode substrate are connected so that the element surface of the semiconductor substrate faces the electrode substrate, and the semiconductor Connecting the first and second power supply source connecting terminals formed on the element surface side of the substrate and the third power supply source connecting terminal of the electrode base;
The power supply source includes the connection lead at a plurality of end portions including at least opposite end portions, and the connection lead is connected to the fourth power supply source connection terminal of the electrode base. A self-destructive semiconductor device.

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