JP2000077521A - Multi-layer interconnection structure body and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure in which a first metal interconnection is not exposed in an etch-back process for an SOG film, in a process for manufacturing a multi-layer interconnection structure body. SOLUTION: A first metal interconnection 2 is formed selectively on an insulating film 1 where a surface made of a step 13, and a titanic oxide film 3 which is a metal insulating film is formed on the first metal interconnection 2. On the exposed surface, a first P-TEOS film 4 is formed. An SOG film 5 is formed on the surface of the first P-TEOS film 4 except directly above the titanic oxide film 3, and a second P-TEOS film 6 is formed on the titanic oxide film 3 and the SOG film 5. Finally, a second metal interconnection 7 is formed on the second P-TEOS film 6 to complete a multi-layer interconnection structure body. Here the metal interconnections 2 and 7 for 2 layers are taken as an example, however, each film may be laminated likewise even when it is a multi- layer interconnection structure body.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multi-layer wiring structure having a step in a semiconductor device such as an IC and a method of manufacturing the same.

[0002]

2. Description of the Related Art Large-scale integrated circuits (hereinafter referred to as LSIs)
In this case, a plasma silicon oxide film (hereinafter, referred to as a P-TEOS film) is used as an interlayer insulating film of a metal layer wiring.
tetraethyl orthosilicate)
/ Coated glass film (hereinafter referred to as SOG film. Spino
n glass) / a three-layer insulating film of a P-TEOS film is used. Here, the P-TEOS film is made of tetraethyl orthosilicate (tetraethyl orthosilicate).
plasma CVD (chemical vapor depot) using orthosilicate as a source
It is a silicon oxide film formed by the position method.

FIG. 3 is a sectional view of a main part of a conventional multilayer wiring structure. This multilayer wiring structure has the above-mentioned three-layer structure interlayer insulating film. The interlayer insulating film having the three-layer structure has a first structure.
After forming the metal wiring 12 of the first layer, the first P-TE
An OS film 14 is formed to a thickness of about 0.3 μm, and then the second layer S
The OG film 15 is spin-coated, and the SOG film 15 is etched back to be flattened. And the second P-TE of the third layer
The OS film 16 is formed by forming a film of about 0.5 μm.

The SOG film 15 is a material based on an organic material such as an alkylalkoxysilane or an organic siloxane, and has a thickness of about 500 nm in a flat portion.
The thickness of the SOG film 15 after the spin coating is large at the low elevation portion 22 and the wide portion of the first metal wiring 12. If the post-processing such as the curing process at the time of forming the SOG film 15 is insufficient, there is a problem that the degassing generated from the SOG film 15 causes separation at the interface between the SOG film 15 and the first P-TEOS film 14. Occurs. Further, the thickness of the SOG film 15 at the high altitude portion 21 tends to be small,
In the etch-back process of the G film 15, the first P-TEOS film 14 is almost completely removed, and the surface of the first metal wiring formed at the high altitude portion (the thick portion of the insulating film) may be exposed. Occurs.

[0005]

In particular, when manufacturing a semiconductor device having a large step 23 and fine wiring, the thickness of the SOG film 15 on the first metal wiring 12 at the high altitude 21 is reduced. Therefore, the SOG film 15 is removed at an early stage of the etch back of the SOG film 15, and
P-TEOS film continues to be etched.

In the case of a fine metal wiring having a thickness of 0.8 μm or less, when the wiring is exposed, the wiring is exposed to plasma in the etch back process of the SOG film 15 and is charged up. Due to the charge-up of the wiring, characteristics of the semiconductor element may be deteriorated. As shown in FIG. 4, before the SOG film 15 is formed, an insulating film 13 (P− (TEOS film). The insulating film 13 serves as a margin in the etch-back process, and prevents the first metal wiring 12 from being exposed at a high altitude portion 21. This method is described in, for example, Japanese Patent Application Laid-Open No. 9-2463.
No. 74 discloses this.

However, in this method, the first metal wiring 1
After forming 2, the step of covering the insulating film 13 for obtaining a margin and the step of etching for processing the insulating film 13 are additionally required, and the number of steps is increased.
An object of the present invention is to solve the above-mentioned problems, and to provide a multilayer wiring structure having a structure in which the number of steps is small and a first metal wiring is not exposed in an SOG film etch-back step, and a method of manufacturing the same. It is in.

[0008]

In order to achieve the above object, in a multilayer wiring structure formed on a first insulating film having a step on the surface, the multilayer wiring structure is formed on the first insulating film. A first metal wiring, a metal-based insulating film formed on an upper surface of the first metal wiring, and an exposed surface of each of the metal-based insulating film, the first metal wiring, and the first insulating film. The structure includes a second insulating film to be formed and a second metal wiring formed over the second insulating film.

Further, in a multilayer wiring structure formed on a first insulating film having a step on the surface, a first metal wiring formed on the first insulating film, and a first metal wiring formed on the first insulating film. A metal-based insulating film formed on the upper surface of the semiconductor device, a first plasma silicon oxide film formed on an exposed surface of each of the metal-based insulating film, the first metal wiring, and the first insulating film; A coated glass film formed on the first plasma silicon oxide film except immediately above the first metal wiring formed at a high step portion of the first insulating film; The second plasma silicon oxide film is formed on the plasma silicon oxide film, and the second metal wiring is formed on the second plasma silicon oxide film.

In a method of manufacturing a multilayer wiring structure formed on a first insulating film having a step on a surface, a step of forming a first metal wiring on the first insulating film; Forming a metal-based insulating film on the upper surface of the metal wiring, forming a second insulating film on each surface of the metal-based insulating film, the first metal wiring, and the first insulating film; Forming a second metal wiring on the second insulating film.

In a method for manufacturing a multilayer wiring structure formed on a first insulating film having a step on a surface, a step of forming a first metal wiring on the first insulating film; Forming a metal-based insulating film on the upper surface of the first metal wiring, and forming a first plasma silicon oxide film on each surface of the metal-based insulating film, the first metal wiring, and the first insulating film Forming a coated glass film on the first plasma silicon oxide film; and forming the coated glass film on the first metal wiring at a low elevation until reaching the surface of the first plasma silicon oxide film. Removing (etchback step), forming a second plasma silicon oxide film on the first plasma silicon oxide film immediately above the metal-based insulating film and on the coated glass film, The plasm A production process comprising the step of forming a second metal interconnection on the silicon oxide film.

It is preferable that the metal-based insulating film is made of titanium oxide. As described above, by forming the metal-based insulating film on the upper surface of the first metal wiring, it serves as an etch-back stopper (stops etching) in the etch-back step of flattening the SOG film. When this metal-based insulating film is, for example, a TiO ₂ film, W.I. Y. Ya
ngel. Is J. Jour. Appl. Phys. Vo
l. 23 pp. 1560 (1984), the binding energy value is 458.2 eV and the Si
It is larger than 103.5 eV of O ₂ , and is hardly chemically etched. This indicates that the TiO ₂ film is an effective etching stopper.

[0013]

FIG. 1 is a sectional view of a main part of a multilayer wiring structure according to a first embodiment of the present invention. A first metal wiring 2 is selectively formed on an insulating film 1 having a step 23 on the surface (corresponding to a first insulating film shown in claims), and a first metal wiring 2 is formed on the first metal wiring 2. A titanium oxide film 3 made of titanium oxide, which is a metal-based insulating film, is formed. The first on the exposed surface
Of the P-TEOS film 4 is formed. The SOG film 5 is formed on the surface of the first P-TEOS film 4 except immediately above the titanium oxide film 3. Next, the SOG film 5 is flattened by an etch-back method, and a second P-type film is formed on the titanium oxide film 3 and the SOG film 5.
A TEOS film 6 is formed. Finally, a second metal wiring 7 is formed on the second P-TEOS film 6, and a multilayer wiring structure is completed. Here, the two-layer metal wirings 2 and 7 have been described as an example, but a multilayer wiring structure can be manufactured by similarly stacking the respective films. In this embodiment, the first P-
The TEOS film 4 and the second P-TEOS film 6 correspond to a second insulating film described in the claims.

The first metal wiring 2 is formed by sequentially laminating a Ti film, a TiN film and an AlSiCu film (not shown) from the lower layer, and serves as an etch-back stopper when the SOG film 5 is etched back. Oxide film 3
To form In this way, by coating the titanium oxide film 3 on the first metal wiring 2, the surface of the first metal wiring 2 formed at the high altitude location 21 (the location where the surface is high) is formed. However, the SOG film 5 is not exposed by the back etching for flattening the SOG film 5. Next, a method for manufacturing the multilayer wiring structure will be described.

FIGS. 2A to 2C are cross-sectional views of a main part of a multi-layer wiring structure according to a second embodiment of the present invention. As shown in FIG. 1A, an insulating film 1 having a step 23 on its surface is formed by, for example, boron phosphorus glass (BPSG: Bor) by a normal process.
o-Phospho silica Glass
Is formed, a metal film is deposited by a sputtering method and patterned to form a first metal wiring 2. Although not shown, the metal film of the first metal wiring 2 is, for example, 20 nm in thickness.
Ti film, 100 nm TiN film, 700 nm AlS
It is formed by laminating iCu films in order from the lower layer. A titanium oxide film 3 serving as a stopper at the time of etching back the SOG film 5 is formed thereon with a thickness of 100 nm. If there is irregular reflection from the underlying AlSiCu film in patterning when forming the first metal wiring 2 thereon, TiN serving as an anti-reflection film (not shown)
A film is formed with a thickness of 30 nm. However, if there is no irregular reflection, the TiN film serving as the antireflection film may not be provided. These films are formed on the insulating film 1 having a step 23 on the surface. Further, the TiN film constituting the first metal wiring 2 on the side in contact with the insulating film 1 serves as a barrier metal, and the Ti film is required to make the contact with the silicon substrate an ohmic contact. is there. The AlSiCu film (not shown) constituting the main part of the first metal wiring 2 has a Si content of about 1% and a C content of about 1%.
It is formed when the content of u is about 0.3% to 0.5%.

The TiN film serving as a barrier metal is
N_TwoReactive sputtering method in Ar atmosphere containing gas
Is formed. Further, the titanium oxide film 3 has the above-mentioned reflection property.
Before forming an overlying TiN film serving as a barrier film, O
_TwoReactive sputtering method in Ar atmosphere containing gas
Formed. Therefore, the Ti film used to form the Ti film
O in the chamber with the target_TwoFollow the gas line
It only needs to be installed, and the equipment requires only simple modification.
In addition, a chamber with Ti target and TiN film formed
With Ti target and N _TwoWith gas line
Chamber and chamber with AlSiCu target
-Multi-chamber consisting of three chambers
Using a sputtering device, Ti film / TiN film / AlSiC
a first metal wiring 2 having a multilayer structure of a u film, and a first metal
A multi-layer structure having a TiN film as an anti-reflection film coated on the wiring 2
When forming a layer wiring structure, a TiN film is formed twice.
Therefore, the first wafer (semiconductor substrate) is the upper layer
During the process of forming the TiN film of FIG.
The second wafer to be formed is waiting in another chamber
Becomes

For this reason, O _{2 is} added to the TiN film forming chamber.
Installing additional gas lines further lengthens the standby state. Therefore, if a chamber for forming a titanium oxide film is used as a chamber for forming a titanium oxide film and an O ₂ gas line is additionally installed in this chamber, the processing time is shorter. Thus, by additionally providing an O ₂ gas line in the chamber for forming a Ti film, it is possible to continuously form a film from a lower Ti film to an upper titanium oxide film or a TiN film.

After processing the first metal wiring 2 including the upper TiN film and the TiO 2 film by patterning and etching steps, a lower first P-TEOS film 4 is formed by a plasma CVD method. , SOG is spin-coated with a spin coater (rotary coating device). After the SOG is applied, the SOG film 5 is formed by curing (baking and hardening), volatilization of the solvent and a polymerization reaction. The curing conditions are divided into two stages in order to prevent cracks in the SOG film 5 during curing. The first stage is performed at 300 ° C. in an N ₂ atmosphere for 30 minutes, and the second stage is performed at 420 minutes.
C. in an N ₂ atmosphere for 60 minutes.

Next, as shown in FIG.
The film 5 is etched back until the film 5 reaches the surface of the first P-TEOS film 4 at the low altitude portion 22. At this time, the SOG film 5 at the high altitude location 21 is completely removed by etching. Further, when the first P-TEOS film 4 is also removed by etching, the titanium oxide film 3 is etched back.
Since this serves as a stopper, the surface of the first metal wiring 2 formed at the high altitude portion 21 is not exposed by this etch back. Then, the second P-TEO in the upper layer
An S film 6 is formed. Thereafter, in order to open a via contact hole (not shown) (a connection hole between the first metal wiring 2 and the second metal wiring 7 shown in FIG. 4C), the titanium oxide film 4, the first and second Patterning and etching are performed on the P-TEOS films 4 and 6 of FIG.

Next, as shown in FIG. 1C, an Al alloy film or the like is deposited and processed by a sputtering method to form a second metal wiring 7, thereby completing a multilayer wiring structure.

[0021]

According to the present invention, for example, a metal-based insulating film such as a titanium oxide film, which serves as an etch-back stopper in the SOG film etch-back step, is formed on the upper surface of the first metal wiring. In addition, when the SOG film is etched back, the surface of the first metal wiring formed at a high altitude location can be prevented from being exposed. In addition, by using a titanium oxide film as the metal-based insulating film, a film can be formed continuously after the first metal wiring is formed, and a film forming process can be performed as compared with the conventional case where a margin insulating film is formed. Time can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a multilayer wiring structure according to a first embodiment of the present invention;

FIGS. 2A to 2C are cross-sectional views of main steps in the order of steps in the manufacturing process of the multilayer wiring structure according to the second embodiment of the present invention; FIGS.

FIG. 3 is a cross-sectional view of a main part of a conventional multilayer wiring structure.

FIG. 4 is a cross-sectional view of a main part of another conventional multilayer wiring structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating film 2 1st metal wiring 3 Titanium oxide film 4 1st P-TEOS film 5 SOG film 6 2nd P-TEOS film 7 2nd metal wiring 11 Insulating film 12 1st metal wiring 13 Margin 14 Insulating film 14 First P-TEOS film 15 SOG film 16 Second P-TEOS film 17 Second metal wiring 21 High altitude location 22 Low altitude location 23 Step

Claims (6)

[Claims] In a multilayer wiring structure formed on a first insulating film having a step on a surface, a first metal wiring formed on the first insulating film; and a first metal wiring formed on the first insulating film. A second insulating film formed on an exposed surface of each of the metal-based insulating film, the first metal wiring, and the first insulating film; And a second metal wiring formed on the insulating film. 2. A multilayer wiring structure formed on a first insulating film having a step on a surface, wherein a first metal wiring formed on the first insulating film, and a first metal wiring formed on the first insulating film. A metal-based insulating film formed on the upper surface of the semiconductor device, a first plasma silicon oxide film formed on an exposed surface of each of the metal-based insulating film, the first metal wiring, and the first insulating film; The first insulating film is formed at a high step in the first insulating film.
A coated glass film formed on the first plasma silicon oxide film except immediately above the metal wiring, and a second plasma silicon oxide film formed on the coated glass film and the first plasma silicon oxide film. And a second metal wiring formed on the second plasma silicon oxide film. 3. The multilayer wiring structure according to claim 2, wherein said metal-based insulating film is a titanium oxide. 4. A method of manufacturing a multilayer wiring structure formed on a first insulating film having a step on a surface, wherein a step of forming a first metal wiring on the first insulating film; Forming a metal-based insulating film on the upper surface of the first metal wiring, and forming a second insulating film on each surface of the metal-based insulating film, the first metal wiring, and the first insulating film; And a step of forming a second metal wiring on the second insulating film. 5. A method of manufacturing a multilayer wiring structure formed on a first insulating film having a step on a surface, wherein a step of forming a first metal wiring on the first insulating film; Forming a metal-based insulating film on the upper surface of the first metal wiring, and forming a first plasma silicon oxide film on each surface of the metal-based insulating film, the first metal wiring, and the first insulating film Forming a coated glass film on the first plasma silicon oxide film; and forming the coated glass film on the first metal wiring at a low elevation until reaching the surface of the first plasma silicon oxide film. Removing, a step of forming a second plasma silicon oxide film on the first plasma silicon oxide film immediately above the metal-based insulating film, and a step of forming a second plasma silicon oxide film on the coated glass film; Second on Method for manufacturing a multilayer wiring structure which comprises a step of forming a genus wiring. 6. The method according to claim 5, wherein the metal-based insulating film is a titanium oxide.