JP2000076859A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor storage for reducing a layout area by reducing the influence of the feedthrough current of a sense amplifier in writing and the coupling between bit lines. SOLUTION: Sensing amplifiers in a plurality of memory bands are grouped, for example sense amplifiers SA00 and SAn0 and the like are grouped and sense amplifiers SA03 and SAn3 and the like are grouped, the sense amplifiers in each group are connected to a power supply voltage Vpp and common potential Vss via each common switching transistor, each switching transistor is turned on and off by each enable signal, a sense amplifier group that is connected to a non-selection memory cell is activated out of a plurality of memory cells that are connected to a selection word line in writing, and a sense amplifier group that is connected to a selection bit line is activated after the potential of the selection bit line is set according to writing data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
For example, a DRAM and a field memory (FMEM) having substantially the same configuration as the DRAM and capable of simultaneously writing and reading a plurality of bits of data.
And the like.

[0002]

2. Description of the Related Art In a conventional field memory, a memory cell array is formed by arranging a plurality of memory cells each composed of one transistor and one capacitor in a matrix, almost in the same manner as a DRAM. The memory cells in each row are connected to the same word line, and the memory cells in each column are connected to the same bit line. FIG. 1 illustrates one configuration example of the field memory. As shown in the figure, there are a plurality of field memories, for example, n (n is a natural number) memory banks BK.
a0,..., BKan. Each memory bank has a plurality of memory cells arranged in a matrix. In FIG. 1, for simplicity of display, four memory cells MC0, MC1, MC2, MC3
And a word line W connected to these memory cells
Only L0 is shown.

The gates of the transistors of each memory cell on the same row are connected to the same word line. For example, as shown, the memory cells MC0, MC1, MC2, MC
3 have their gates connected to the same word line WL0. The drain diffusion region of the transistor constituting each memory cell is connected to a bit line, and the source diffusion region is connected to a capacitor. A plurality of bit lines are wired in parallel with the word lines. In addition,
One bit line pair is composed of two bit lines, and each bit line pair is a sense amplifier SA0, SA1, SA2, S
It is connected to A3. Hereinafter, of the two bit lines forming one bit line pair, one is called a bit line and the other is called a bit supplementary line. In FIG. 1, four memory cells M
Since only C0, MC1, MC2 and MC3 are shown,
Only four sense amplifiers connected to four bit line pairs are shown.

[0004] Each bit line pair is connected to a data line DL or an auxiliary data line DLB via a block selection transistor. The data line DL and the data supplement line DLB are
It is connected to the write buffer WBUF. At the time of writing, the data line D is output by the write buffer WBUF.
L and the data supplement line DLB are set to levels according to the write data, respectively. For example, the selected memory cell M
When data "0" is written to C0, the data line DL is set to a high level and the data auxiliary line DLB is set to a low level. Conversely, when data "1" is written to the selected memory cell MC0, the data line DL is set to a low level. , Data supplementary line D
LB is set to a high level.

In FIG. 1, memory banks other than memory bank BKa0 have the same configuration as memory bank BKa0. Therefore, FIG. 1 shows only the configuration of memory bank BKa0. In field memory, normal DR
It has almost the same configuration as the AM, but differs from a normal DRAM in that data of a plurality of bits can be read or written at the same time.

As shown in FIG. 1, all sense amplifiers in one memory bank are connected to one enable signal S.
Activated by AE. At the time of writing or refreshing, all the sense amplifiers are operated by setting the enable signal SAE to the active state. FIG. 2 is a timing chart showing an example of a write operation of a memory bank, that is, a so-called direct write method. Hereinafter, an operation when data “1” is written to the memory cell MC0 will be described with reference to FIGS.

[0007] Word line WL0 at time t ₀ is selected and activated. That is, as shown in FIG.
L0 is set from low level to high level. In addition,
Each word line is connected to a row decoder (not shown).
r), one of a plurality of word lines is selected and activated by the row decoder.

Slightly after the activation of word line WL0,
Sense amplifier enable signal SAE becomes active at time t _1. That is, the enable signal SAE is set from a low level to a high level. In the standby state, each bit line and each bit complement forming each bit line pair are precharged to a predetermined intermediate level. After the word line WL0 rises, the level of each bit line or bit auxiliary line forming the bit line pair slightly changes according to the storage data of the memory cell connected thereto.

For example, the memory cells MC0, MC1, MC
Assuming that data "0" is stored in memory cells MC2 and MC3, bit line WLB0 connected to selected memory cell MC0 and other memory cells MC1, MC2 and MC3 connected to selected memory cell MC0 after word line WL0 rises. The level of each of the connected bit supplementary lines BLB1 to BLB1 slightly decreases. If at time t ₁ the sense amplifier enable signal SAE is activated state, the sense amplifiers SA0, SA1, SA2, SA3 is operated initially, the potential difference between the bit line pair connected to each of which is amplified. Therefore, for example, the level of the bit line BL0 connected to the selected memory cell MC0 increases, and the level of the bit auxiliary line BLB0 decreases.

[0010] When the potential difference between the bit line pair is somewhat amplified, block select signal BS0 is active state corresponding to the selected memory cell MC0 in the time t _2, i.e.,
Set to high level. Accordingly, the data line DL
In addition, the level of bit line BL0 and bit auxiliary line BLB0 is forcibly set according to the set level of data auxiliary line DLB. Here, for example, when writing data “1” different from the original storage data “0” to the memory cell MC0,
The data line DL is set to a low level and the data auxiliary line DLB is set to a high level. Therefore, when the block selection signal BS0 is switched to the high level, the bit line BL0 is set to the low level and the bit auxiliary line BLB0 is set to the high level according to the storage data "0" of the memory cell MC0. The state of the amplifier SA0 is repeated.

When data is being written to the selected memory cell MC0, the other memory cells MC1, MC2 and MC3 connected to the same selected word line WL0 are refreshed. In this case, the bit lines BL1 to BL1 correspond to the storage data of these unselected memory cells.
When the level of the bit line BL3 and the bit auxiliary lines BLB1 to BLB3 changes and the sense amplifier enable signal SAE is activated, the sense amplifiers SA1 to SA3 operate and the voltage between the bit line and the bit auxiliary line connected to each other. Are amplified, the levels of the bit lines BL1 to BL3 and the bit auxiliary lines BLB1 to BLB3 are determined, and the memory cells MC1 to MC3 are rewritten.

[0012]

In the above-mentioned conventional semiconductor memory device, all sense amplifiers in each memory bank are activated by a common enable signal SAE. There is a disadvantage that the sense amplifiers connected to the non-selected memory cells start operating at the same timing, which causes a problem such as coupling between bit lines. For example,
In the above-described direct write method, the sense amplifier starts to be activated before writing to the selected memory cell. This is to avoid the influence of the coupling between the pre-sense and the bit line. However, this means that when the original storage data of the memory cell does not match the write data, the sense amplifier that has begun to tilt is forcibly repeated by the write buffer WBUF.
Time interval t ₁ and t ₂ in FIG. 2, i.e., the enable signal SAE is activated state, the purpose described above from the beginning the sense amplifier operates block selecting signal BS0 is the longer time interval until the active state Although it can be surely achieved, the sense amplifier is inverted after the state is determined to some extent, and the state inversion is further aggressive.

For this reason, during the state inversion of the sense amplifier, that is, for a while after time t ₂ in FIG.
A through current flows between the write buffer WBUF and the sense amplifier SA0 and to the sense amplifier SA0. In the case of a field memory, since a large number of memory cells write simultaneously, the write buffer WBUF is required to have a current supply capability of supplying a large write current, and the direct write method is generally not preferable.

Further, in order to repeat the activated sense amplifier, complementary data is required for the bit line and the bit auxiliary line, and the data line DL and the data auxiliary line are required for one-bit write data. It is necessary to provide both DLBs, which is disadvantageous on the layout.

As a countermeasure, there is a method of adopting a charge transfer type writing method instead of the direct writing method.
However, in recent years, as the voltage has been reduced, the threshold voltage of the sense amplifier, particularly the threshold voltage of the nMOS transistor forming the sense amplifier, has become much lower than in the past. ing.

Up to now, in a normal DRAM, the number of memory cells to be written simultaneously is as small as 16 or 32, and the number of memory cells to be written is extremely smaller than the number of memory cells to be refreshed. There were almost no problems described above. However, as the bit width of the data bus increases, the number of memory cells to which data is written simultaneously in a normal DRAM is 64, 128 or 2
There is a tendency to increase to 56. In this case, the normal DRA
M also has the same problem as the field memory in the above-described direct writing method, and an effective solution is desired.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the conventional direct writing method to improve the effect of the through current of the sense amplifier and the coupling between bit lines during writing. It is an object of the present invention to provide a semiconductor memory device which can reduce the layout area and can reduce the layout area.

[0018]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of word lines, a plurality of bit line pairs comprising bit lines and bit supplementary lines, and a plurality of word lines. A plurality of memory cells provided at intersections of a line and the plurality of bit line pairs, a word line driving circuit for activating a word line selected according to an address signal, and a plurality of bit line pairs. A plurality of sense amplifiers electrically connected to each other, a sense amplifier driving circuit for controlling the operation of the plurality of sense amplifiers, and a plurality of sense amplifiers connected between the plurality of bit line pairs and the data input / output lines, respectively. A plurality of switching means, a write data supply circuit for supplying write data to the data input / output line, and a switching means connected to a bit line pair selected according to an address signal When writing data to a memory cell, a selected word line is activated by the word line driving circuit and connected to a non-selected bit line pair by the sense amplifier driving circuit. The sense amplifier that has been activated is activated, the switching means connected to the selected bit line pair is activated by the switching means driving circuit, and after a predetermined time, the sense amplifier driving circuit connects to the selected bit line pair. The activated sense amplifier is activated.

In the present invention, preferably, the plurality of switching means are constituted by MOS transistors, and electrically connect the data input / output line to the bit line or the bit auxiliary line.

[0020]

FIG. 3 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device of the present embodiment is, for example, a field memory or a DRAM capable of simultaneously writing multiple bits. As shown, the semiconductor memory device of the present embodiment is configured by a plurality of memory banks BK0,..., BKn.
Since each memory bank has almost the same configuration, FIG.
Shows only the memory bank BK0.

In the memory bank BK0, a plurality of memory cells are arranged in a matrix. Note that FIG. 3 shows only four memory cells MC0, MC1, MC2, and MC3 arranged in one row for convenience.
Each memory cell has the structure of a normal DRAM memory cell. That is, it is composed of one transistor and one capacitor. In each memory cell, the gate of the transistor is connected to a word line, one of a drain and a source diffusion region is connected to a bit line, and the other is connected to a capacitor. Each memory cell arranged in the same row is connected to the same word line, and each memory cell arranged in the same column is connected to the same bit line.

One bit line pair is constituted by two bit lines. Each bit line pair is connected to a sense amplifier. As shown, the bit line BL0 and the auxiliary bit line BLB0 are connected to the sense amplifier SA0, and the bit line BL3 and the auxiliary bit line BLB3 are connected to the sense amplifier SA.
3 is connected. In the present embodiment, each of the sense amplifiers SA0, SA1, SA2, and SA3 has a different sense amplifier enable signal SAE0, SAE1, and S3.
Activated by AE2 and SAE3. That is, in the present embodiment, at the time of writing, it is possible to activate the sense amplifier connected to the selected memory cell and the sense amplifier connected to the non-selected memory cell at different timings.

In the bit line pair connected to each sense amplifier, the bit line is connected to the data line DL via a block select transistor. Block select signals BS0, BS are connected to the gates of the block select transistors.
When 1, BS2 and BS3 are applied, the block selection transistor turns on, and one bit line selected by this is connected to the data line DL.

Although each memory bank is provided with a sense amplifier corresponding to the number of bit line pairs, FIG. 3 shows only four sense amplifiers SA0, SA1, SA2 and SA3. These sense amplifiers all have the same configuration. FIG. 4 shows an example of the sense amplifier.

As shown in FIG. 4, the sense amplifier is composed of a flip-flop composed of two CMOS inverters whose inputs and outputs are connected alternately at A. For example, an inverter is formed by the pMOS transistor P1 and the nMOS transistor N1, a connection point between the gates of the transistor P1 and the transistor N1 forms an input terminal of the inverter, and a connection point between the drains of these transistors, that is, the node ND1 Constitute the inverter output terminal. Similarly, an inverter is constituted by the pMOS transistor P2 and the nMOS transistor N2, and a connection point between the gates of the transistor P2 and the transistor N2 constitutes an input terminal of the inverter;
The connection point between the drains of these transistors, that is,
The node ND2 forms the inverter output terminal.

The sources of the transistors P1 and P2 are pMO
The drain of the S transistor P3 is connected, the source of the transistor P3 is connected to the power supply voltage V _PP , and the gate is connected to the signal line of the sense amplifier enable signal SAE-P. The sources of the transistors N1 and N2 are nM
It is connected to the drain of the OS transistor N3, the source of the transistor N3 is connected to the common potential V _SS, and its gate connected to the signal line of the sense amplifier enable signal SAE-N.

Node ND1 is connected to bit line BL,
Node ND2 is connected to bit auxiliary line BLB. Here, as an example, the memory cell MC is connected to the bit line BL, and the gate of the transistor forming the memory cell is connected to the word line WL.

Normally, the enable signal SAE-P is held at a high level, for example, the power supply voltage V _PP , and the enable signal SAE-N is held at a low level, for example, at the common potential V _SS. Turns off,
The sense amplifier does not operate. Enable signal SAE-P
Are set to a low level and the enable signal SAE-N is set to a high level, the transistors P3 and N3 are turned on, and the sense amplifier is activated. At this time, the potential difference between the bit line BL and the bit auxiliary line BLB is amplified by the sense amplifier.

For example, when the bit line BL is replaced by the bit auxiliary line BLB
When the voltage is slightly higher, transistor N2 is strongly turned on, which causes bit complement line BLB to become
2 and its potential drops. Along with this,
The transistor P1 is turned on, and the bit line BL is connected to the power supply voltage V
It is charged by _PP and its potential rises. That is, when the sense amplifier is activated, a slight potential difference between the bit line BL and the auxiliary bit line BLB is quickly amplified, and the potential of the bit line BL and the auxiliary bit line BLB is determined.

The enable signals SAE-N and SAE-P can be activated simultaneously or sequentially with a predetermined time difference. 5A and 5B show potential changes of the bit line BL and the bit auxiliary line BLB due to activation of the enable signals SAE-N and SAE-P, respectively.

FIG. 5 shows enable signals SAE-N and SA
The potential changes of the bit line BL and the bit auxiliary line BLB when EP are simultaneously activated are shown. As shown, at time t ₀ , the word line WL is activated. Thereby, the bit line B according to the storage data of the memory cell connected to the bit line BL or the bit auxiliary line BLB
The level of L or bit auxiliary line BLB slightly changes, and a potential difference occurs between them.

[0032] Then, at time t _1, the sense amplifier enable signal SAE-N and SAE-P are simultaneously activated. That is, the enable signal SAE-P is switched from the high level to the low level at the same time when the enable signal SAE-N is switched from the low level to the high level. Along with this, the sense amplifier starts to operate, a small potential difference between the bit line BL and the bit auxiliary line BLB is amplified, for example, the bit line BL is held at the power supply voltage V _PP ,
Since the auxiliary bit line BLB is held to the common potential V _SS, the potential of the bit line BL and auxiliary bit line BLB is determined.

FIG. 6 shows enable signals SAE-N and SAE.
A potential change of the bit line BL and the bit auxiliary line BLB when −P is sequentially activated is shown. As shown,
First, the word line WL is activated at time t _0.
As a result, the level of the bit line BL or the bit auxiliary line BLB slightly changes according to the storage data of the memory cell connected to the bit line BL or the bit auxiliary line BLB,
A potential difference occurs between them.

Next, the time t₁At the enable signal
SAE-N is activated. That is, from low level to high
Switch to level. Thereby, the sensor shown in FIG.
In the amplifier, either transistor N1 or N2
Turns on strongly. According to the data stored in the selected memory cell
Either the bit line BL or the bit supplementary line BLB
Discharge through the passing transistor N1 or N2,
Potential drops. For example, as shown in FIG.
The potential of the auxiliary line BLB decreases and finally the common potential V _SSHold on
Is done.

After a predetermined delay time from time t ₁ , enable signal SAE-P is activated at time t ₂ . That is, the enable signal SAE-P is switched from the high level to the low level. In response, one of the transistors P1 and P2 of the sense amplifier shown in FIG. 4 strongly turns on, and accordingly, the bit line BL and the bit auxiliary line B
The level of LB is set to the power supply voltage V _PP . For example, when the transistor P1 is strongly turned on, the potential of the bit line BL increases as shown in FIG. 6 and is maintained at the power supply voltage V _PP .

As shown in FIG. 6, the enable signal SAE
-N and SAE-P are sequentially activated at a predetermined time interval, so that the nMOS transistor having high sensing sensitivity is operated first, and the low level of the bit line BL and the bit auxiliary line BLB is set according to the data stored in the selected memory cell. After determining the side to be set to the level, the pMOS transistor is operated, and the other side is held at the high level. Thereby, highly accurate sensing can be realized, and the influence of noise can be avoided.

FIG. 7 shows an example of a sense amplifier circuit constituted by a plurality of sense amplifiers. Here, as an example, four sense amplifiers SA0, SA1, SA
2 and SA3. Note that these sense amplifiers have a flip-flop configuration composed of two CMOS inverters as shown in FIG.

As shown, the p-channel side of the sense amplifier SA0 is connected to the power supply voltage V _PP via the pMOS transistor PT0, and the n-channel side is connected to the common potential V _SS via the nMOS transistor NT0. Other sense amplifiers SA1 to SA3 have almost the same configuration. For example, the p-channel side of the sense amplifier SA3 is connected to the power supply voltage V _PP via the pMOS transistor PT3, and the n-channel side is connected to the common potential V _SS via the nMOS transistor NT3.

The ON / OFF of the pMOS transistor PT0 is controlled by an enable signal SAE-P0 applied to its gate, and the pMOS transistor PT1 is turned on / off.
Is the enable signal SAE applied to its gate
-P1 is turned on / off, and the pMOS transistor PT2 is turned on / off by an enable signal SAE-P2 applied to its gate, and the pMO transistor PT2 is turned on / off.
ON / OFF of the S transistor PT3 is controlled by an enable signal SAE-P3 applied to its gate. The nMOS transistor NT0 is turned on / off by an enable signal SAE-N0 applied to its gate.
The turning off of the nMOS transistor NT1 is controlled by the enable signal SAE-N1 applied to the gate of the nMOS transistor NT1.
2 is an enable signal SA applied to its gate
ON / OFF is controlled by E-N2, and ON / OFF of nMOS transistor NT3 is controlled by enable signal SAE-N3 applied to its gate.

Enable signals SAE-P0 and SAE-N
0 is a pair of control signals, and the normal enable signal SA
E-P0 is held at a high level and SAE-N0 is held at a low level. When the sense amplifier SA0 is activated, the enable signal SAE-N0 is switched from the low level to the high level, and the enable signal SAE-P0 is at the high level. To low level. The timing of switching between the two enable signals is set, for example, simultaneously. The same applies to other enable signals. For example, the enable signal SAE-P
3 and SAE-N3 constitute a pair of control signals, and enable signal SAE when activating sense amplifier SA3.
−N3 is switched from low level to high level, and the enable signal SAE-P3 is switched from high level to low level.

Although only four sense amplifiers are illustrated in FIG. 7, the actual sense amplifier circuit is not limited to this. For example, when there are eight sense amplifiers, each sense amplifier is Since each pair of enable signals is activated, eight pairs of enable signals are supplied from outside. Alternatively, the configuration may be such that the two groups are divided into four groups, and eight sense amplifiers are controlled by four pairs of enable signals.

FIG. 8 shows another configuration example of the sense amplifier circuit. As shown, in the sense amplifier circuit of the present example, for example, four sense amplifiers SA0, SA1, SA2, S
A3 is provided. However, in this example, the p-channel side of each sense amplifier is commonly connected to the power supply voltage V _PP via the pMOS transistor PTC. The pM
The OS transistor PTC is connected to the enable signal SAE-P
ON / OFF is controlled by C. The n-channel side of each sense amplifier is connected to enable signals SAE-N0 and SAE-N, as in the sense amplifier circuit shown in FIG.
Transistors NT0, NT1, NT2, NT whose on / off are controlled by N1, SAE-N2, and SAE-N3
3 to the common potential V _SS .

Normally, in each sense amplifier, the n-channel side is activated earlier than the p-channel side. That is, in the sense amplifier circuit of FIG. 8, the enable signal SAE-N
0, SAE-N1, SAE-N2 and SAE-N3 are activated in a predetermined order, and then the enable signal SAE-P
C is activated. Therefore, the change in signal level at the time of activation in each sense amplifier can be represented by the timing chart shown in FIG.

FIG. 9 shows a control method for activating the sense amplifier in the semiconductor memory device of the present invention. In FIG. 9, sense amplifiers SA00, SA01, SA02, S
A03 is, for example, a sense amplifier in the memory bank BK0 shown in FIG. 3, and sense amplifiers SAn0 and SAn.
1, SAn2 and SAn3 are sense amplifiers in the memory bank BKn.

Sense amplifier SA00 and sense amplifier SA
The p channel side such as n0 is a pMOS transistor PT
0 through the supply voltage V_PPIt is connected to the. Similarly,
Channel of sense amplifier SA01 and sense amplifier SAn1
Is connected to the power supply voltage via the pMOS transistor PT1.
V_PPConnected to the sense amplifier SA02 and the sense amplifier
The p-channel side of SAn2 is a pMOS transistor PT
2 via the power supply voltage V _PPConnected to the sense amplifier SA
03 and the p channel side of the sense amplifier SAn3 are pMO
Power supply voltage V via S transistor PT3_PPConnected to
ing. Sense amplifier SA00 and sense amplifier SAn0
Through the nMOS transistor NT0
And the common potential V_SSIt is connected to the. Similarly, Sensean
And the n-channel side of the sense amplifier SAn1
The common potential V via the nMOS transistor NT1_SSContact
Then, the sense amplifier SA02 and the sense amplifier SAn2
Through the nMOS transistor NT2
And the common potential V_SSConnected to the sense amplifier SA03.
The n-channel side of the sense amplifier SAn3 is connected to an nMOS transistor.
The common potential V through the transistor NT3_SSIt is connected to the.

PMOS transistors PT0, PT1, P
T2 and PT3 are the enable signals SAE-P, respectively.
0, SAE-P1, SAE-P2, and SAE-P3, the on / off of which is controlled by the nMOS transistors NT0, NT0,
NT1, NT2, and NT3 each have an enable signal S
AE-N0, SAE-N1, SAE-N2, SAE-N
3 controls on / off.

That is, the sense amplifiers in each memory bank are divided into a plurality (four in the example of FIG. 9) of groups.
Each group of sense amplifiers is activated by a common enable signal. For example, the memory bank BK
0, the sense amplifier SA00 of the memory bank BKn, and the sense amplifiers SAn0 of the memory bank BKn.
Activated by E-N0. Similarly, for example, the sense amplifier SA03 of the memory bank BK0 and the memory bank B
All sense amplifiers in other groups, including Kn sense amplifiers SAn3 and the like, enable signal SAE-P3
And activated by SAE-N3. The number of sense amplifiers in each group is, for example, equal to the number of memory banks.

As shown in FIG. 9, the sense amplifiers are divided into a plurality of groups, and the sense amplifiers in each group are activated by a common enable signal, so that each memory bank is connected to a selected memory cell at the time of writing. Activated sense amplifiers and sense amplifiers connected to unselected memory cells can be activated at different timings. Therefore, the write operation of the selected memory cell and the refresh operation of the unselected memory cell are performed at different timings, respectively, and the write buffer WB
The occurrence of through current of the UF and the sense amplifier can be suppressed,
Noise generated by coupling between bit lines can be reduced.

FIG. 10 is a timing chart showing signal changes during a write operation in the grouped sense amplifiers shown in FIG. Hereinafter, the write operation of the semiconductor memory device of the present invention will be described with reference to FIGS. FIG. 10 shows a case where data “1” is written into a memory cell connected to, for example, the word line WL0 and the bit line pair BL0, BLB0, for example, the memory cell MC0 shown in FIG.
It is assumed that data “0” is stored in memory cell MC0 before writing.

As shown in FIG. 10, at time t ₀ , the selected word line WL0 is activated and rises from a low level to a high level. In response to this, the level of each bit line and bit auxiliary line slightly changes according to the storage data of the memory cell connected to each bit line. For example, the memory cell M connected to the bit complement line BLB0
Since data "0" is stored in C0, the level of bit auxiliary line BLB0 drops slightly in response to this, and a potential difference occurs between bit line BL0 and bit auxiliary line BLB0. Other bit lines BL1 to BL3 and bit auxiliary line BL
Similarly, in B1 to BLB3, a potential difference is generated between the bit line and the bit auxiliary line forming each bit line pair according to the storage data of the memory cells MC1 to MC3 connected to the respective cells.

At time t ₁ , unselected memory cell MC1
To the sense amplifiers SA1 to SA3 connected to MC3
Is activated first. That is, the enable signal SAE-N
1 to SAE-N3 rise. FIG. 10 shows the enable signal SAE-N on the n-channel side of the sense amplifier.
Only 0 to SAE-N3 are shown, and the p-channel enable signals SAE-P0 to SAE-P3 are omitted. p
The channel-side enable signal is paired with the n-channel enable signal, and is activated, for example, simultaneously with the n-channel enable signal. That is, as shown in FIG. 10, the enable signal S at time t ₁
At the same time that AE-N1 to SAE-N3 are activated, the enable signals SAE-P1 to SAE-P3 are also activated and switched from high level to low level.

Activated sense amplifiers SA1 to SA3
As a result, the bit lines BL1 to BL3 and the bit auxiliary line BLB1
To BLB3 are amplified respectively. Bit lines BL1 to BL3 and bit auxiliary lines BLB1 are stored in memory cells MC1 to MC3 in accordance with stored data.
To BLB3 are determined.

Bit lines BL1 to BL3 and bit auxiliary lines BLB corresponding to unselected memory cells MC1 to MC3
When the potentials of 1 to BLB3 are almost fixed, that is, FIG.
Block select signals BS0 is activated at time t ₂ shown in. Before the block selection signal BS0 is activated, for example, the write buffer WBUF shown in FIG.
, The data line DL is set to a level corresponding to the write data. For example, in this example, the selected memory cell M
Since data “1” is written to C0, the data line DL is set to, for example, a low level according to the write data.

When the block selection signal BS0 is activated, the bit line BL connected to the data line DL is
0 is set to the low level similarly to the data line DL. At this time, since the sense amplifier SA0 is not activated, the signal level of the bit auxiliary line BLB0 does not change.
It remains set slightly lower according to the storage data of the memory cell MC0 connected to it.

[0055] After the potential of the bit line BL0 and auxiliary bit line BLB is inverted, for example, at time t ₃ when the potential is lower than the complementary bit line BLB0 bit line BL0, the enable signal SAE-N0 is activated. Although not shown, for example, the enable signal SAE-P0 is activated simultaneously with the activation of the enable signal SAE-N0. Activated sense amplifier SA0 amplifies the potential difference between bit line BL0 and bit auxiliary line BLB0, for example, holds bit auxiliary line BLB0 at power supply voltage V _PP ,
Bit line BL0 is held at common potential V _SS .

As shown in FIG. 10, the sense amplifier SA0
Is activated, the potential difference between the bit line BL0 and the complementary bit line BLB0 has already been correctly set in accordance with the write data, so that the state of the sense amplifier SA0 is changed to the write buffer WB as in the conventional semiconductor memory device.
UF will not force you to repeat. The sense amplifier SA0 amplifies the potential difference between the bit line BL0 and the bit auxiliary line BLB0 as it is, and only determines the bit line BL0 and the bit auxiliary line BLB0 to predetermined potentials. Therefore, generation of a through current between the write buffer WBUF and the sense amplifier SA0 or in the sense amplifier SA0 is suppressed.

After the sense amplifier SA0 is activated,
Since it is not necessary to repeat the sense amplifier SA0 by the data line DL, as shown in FIG.
Immediately before A0 is activated, the block selection signal BS0 can be reset.

FIG. 11 shows another control method of the grouped sense amplifiers. As shown in the figure, the sense amplifiers SA00, S of each memory bank BK0,.
A01, SA02, SA03 and SAn0, SAn
1, SAn2 and SAn3 are grouped in the same manner as in FIG. The n-channel sides of the sense amplifiers in each group are connected to nMOS transistors NT0, NT1, N
It is connected to the common potential V _SS via T2 and NT3.
These transistors have enable signals SAE-N0, SAE-N1, and SAE-N0 applied to their respective gates.
ON / OFF is controlled by N2 and SAE-N3. However, unlike FIG. 9, the p-channel side of each sense amplifier is connected to the power supply voltage V _PP via the pMOS transistor PTC. The pMOS transistor PTC
Is the enable signal SAE-P applied to its gate
ON / OFF is controlled by C.

That is, the n-channel sides of the sense amplifiers in each group are connected to enable signals SAE-N0, SAE, respectively.
The activation timing is controlled by E-N1, SAE-N2, and SAE-N3.
The channel side is simultaneously activated by the common enable signal SAE-PC.

FIG. 12 is a timing chart showing one example of activation control of the grouped sense amplifiers shown in FIG. 11, and showing changes in respective signals due to activation of the sense amplifiers. As shown in FIG. 12, in this example, the word line WL0, the block selection signal BS0, and the enable signals SAE-N0 to SAE- on the n-channel side of the sense amplifier.
The change timing of N3 is almost the same as the timing chart shown in FIG. As shown, the enable signal SAE-PC on the p-channel side of the sense amplifier SAE-N
It is activated at the same timing as 0. Therefore, in the sense amplifiers SA1 to SA3, the enable signal SAE
After the n-channel side is activated by -N1 to SAE-N3 and before the p-channel side is activated by the enable signal SAE-PC, the bit lines BL1 to BL3
And among the complementary bit line BLB1～BLB3, should be set to the low level is held firstly to the common potential V _SS by each sense amplifier SA1 to SA3. And time t ₃
After the enable signal SAE-PC is activated, the power supply voltage V _PP keeps the signal to be set to the high level.

As shown in FIG. 12, the sense amplifier SA0 connected to the selected memory cell is slightly delayed from the sense amplifiers SA1 to SA3 connected to other unselected memory cells, and the block selection signal BS0 is activated. Is activated after the write operation, the data stored in the selected memory cell MC0 is written in a bit line B
After the potential levels of L0 and bit auxiliary line BLB0 are correctly set according to the write data, sense amplifier SA0 is activated. Therefore, the sense amplifier SA0
Can be avoided without forcibly repeating the process described above. Further, noise generated by coupling between adjacent bit lines and bit supplementary lines can be reduced.

In FIG. 12, the activation timing of the common enable signal SAE-PC on the p-channel side of the sense amplifier is not limited to the enable signal SAE-N0.
Need not be at the same time as the enable signal SA, for example.
It is also possible to activate slightly later than E-N0.
In such a case, in addition to the sense amplifiers SA1 to SA3, also in the sense amplifier SA0, since the n-channel side having high sensing sensitivity operates and then the p-channel side operates, noise reduction in the sense amplifier can be realized.

In the semiconductor memory device of the present invention,
When writing data different from the original storage data to the selected memory cell, only the data line DL is driven by the write buffer WBUF as shown in FIG. 3 without repeating the state of the sense amplifier connected thereto. It is not necessary to drive a pair of signal lines including the data line DL and the data auxiliary line DLB as in the conventional semiconductor memory device. Therefore, in the present invention, the number of data lines can be reduced, so that the layout area of the semiconductor memory device can be reduced.

[0064]

As described above, according to the semiconductor memory device of the present invention, it is possible to suppress the generation of through current in the write buffer and the sense amplifier at the time of writing, and to reduce the influence of noise generated by coupling between bit lines. Can be reduced. Further, the current driving capability of the write buffer can be reduced as compared with the conventional case, the configuration can be simplified, and the number of data lines can be reduced, so that there is an advantage that the layout area can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a conventional semiconductor memory device.

FIG. 2 is a timing chart showing a write operation of the semiconductor memory device of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a sense amplifier.

FIG. 5 is a timing chart showing an operation example of a sense amplifier.

FIG. 6 is a timing chart showing another operation example of the sense amplifier.

FIG. 7 is a circuit diagram illustrating an example of a sense amplifier circuit.

FIG. 8 is a circuit diagram showing another example of the sense amplifier circuit.

FIG. 9 is a circuit diagram showing an activation control method for grouped sense amplifiers.

FIG. 10 is a timing chart showing an operation at the time of writing in FIG. 9;

FIG. 11 is a circuit diagram illustrating another activation control method of the grouped sense amplifiers.

FIG. 12 is a timing chart showing an operation at the time of writing in FIG. 11;

[Explanation of symbols]

BL0, BL1, BL2. BL3: bit line, BLB
0, BLB1, BLB2. BLB3: bit line, MC
0, MC1, MC2, MC3 ... memory cells, SA0, S
A1, SA2, SA3 ... sense amplifier, WL, WL0 ...
Word line, WBUF: write buffer, V _PP : power supply voltage, V _SS : common potential.

Claims (2)

[Claims] A plurality of word lines; a plurality of bit line pairs comprising bit lines and bit supplementary lines; and a plurality of bit lines provided at intersections of the plurality of word lines and the plurality of bit line pairs. A memory cell; a word line drive circuit for activating a word line selected in accordance with an address signal; a plurality of sense amplifiers electrically connected to the plurality of bit line pairs; and a plurality of sense amplifiers , A plurality of switching means respectively connected between the plurality of bit line pairs and the data input / output lines, and a write supply circuit for supplying write data to the data input / output lines. And a switching means driving circuit for activating switching means connected to a bit line pair selected in accordance with an address signal. If to write data, the selected word line by the word line drive circuit is activated,
The sense amplifier driving circuit activates the sense amplifier connected to the non-selected bit line pair, the switching means driving circuit activates the switching means connected to the selected bit line pair, and thereafter, for a predetermined period of time. A semiconductor memory device in which a sense amplifier connected to a selected bit line pair is activated by the sense amplifier drive circuit after a lapse. 2. The semiconductor memory device according to claim 1, wherein said plurality of switching means are constituted by MOS transistors, and electrically connect said data input / output line to said bit line or said bit auxiliary line.