KR100838390B1 - Pseudo sram - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and in particular to pseudo SRAM design. The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a pseudo SRAM capable of preventing an increase in access time due to refresh. In the present invention, the unit memory cell of the pseudo SRAM is implemented with two transistors and one capacitor (2T1C structure). One transistor is for refresh cycle operation and the other transistor is for normal cycle operation. The pseudo SRAM of the present invention allows the refresh cycle operation and the normal cycle operation to be performed in parallel with the conventional pseudo SRAM in which the refresh cycle operation and the normal cycle operation are separated into separate sections. Therefore, the operation speed of the pseudo SRAM accompanying the refresh can be prevented.

Pseudo esram, 2T1C cell, normal cycle, refresh cycle, access time

Description

Pseudo SRAM {PSEUDO SRAM}

1 illustrates a cell array (folded bit line structure) and sensing related circuit of a pseudo SRAM according to the prior art.

2 is a circuit diagram of a typical bitline sense amplifier block.

3 is an operation timing diagram for the circuit of FIGS. 1 and 2.

4 is an operation timing diagram of a pseudo SRAM according to the prior art.

5 is a diagram illustrating a configuration of unit memory cells of a pseudo SRAM according to an embodiment of the present invention.

FIG. 6 is a layout of a memory cell of the pseudo SRAM of FIG. 5; FIG.

7 illustrates a cell array (open bitline structure) and sensing related circuit of a pseudo SRAM according to an embodiment of the present invention.

8 is an operation timing diagram of a pseudo SRAM according to an embodiment of the present invention.

9 is a view showing an operation in the case of performing a normal cycle before the refresh cycle.

10 is a view showing an operation in the case of performing a normal cycle after a refresh cycle.

* Explanation of symbols for the main parts of the drawings

C: cell capacitor

WL0_N: Word line for normal access

WL0_R: Word line for refresh access

BL0_N: Bit line for normal access

BL0_R: Bit line for refresh access

T_N: NMOS transistor for normal access

T_R: NMOS transistor for refresh access

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and in particular to pseudo SRAM design.

Random Access Memory (RAM) is a semiconductor memory that stores input data in an array of individually addressable elements (memory cells). RAM is largely classified into static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM cells have a static latching structure that does not destroy data while power is applied, and consists of four or six transistors (commonly referred to as 4T or 6T structures). On the other hand, a DRAM cell is composed of one transistor and one capacitor (commonly referred to as a 1T1C structure). Therefore, the conventional SRAM cell requires about 10 times larger area than the DRAM cell, and this disadvantage in terms of integration results in the DRAM market leadership despite the many advantages of SRAM. It has been a factor that causes.

In order to take advantage of SRAM, cell structure changes have been sought to alleviate the shortcomings in terms of density, and while adopting dynamic cells such as DRAM's 1T1C cells, the interface is fully compatible with SRAM, making it functionally like a SRAM. Pseudo SRAM (SRAM) has been proposed.

Since the pseudo SRAM employs a dynamic cell, a refresh operation is required. However, since the SRAM does not have a refresh operation, it is necessary to add a circuit capable of performing the refresh operation by itself.

Self refresh is an operation mode that refreshes memory cells at a constant refresh time period.When a refresh request signal is generated at regular intervals with a refresh timing counter circuit inside the chip, the refresh is used to add a refresh cycle in normal operation. Will perform the action.

That is, in the conventional pseudo SRAM, a refresh cycle and a normal cycle, which is a normal operation cycle, are sequentially performed. By adding the refresh cycle before the normal cycle, the normal operation time is doubled compared to the case without the refresh cycle.

1 is a diagram illustrating a cell array (folded bit line structure) and sensing related circuit of a pseudo SRAM according to the related art.

Referring to FIG. 1, a unit memory cell of a pseudo SRAM according to the related art is composed of one NMOS transistor and one capacitor controlled by word lines WL0, WL1,..., WL5. The drain of the NMOS transistor is connected to the bit line BL, and the source is connected to the storage node SN, which is one electrode of the capacitor. Meanwhile, the plate line PL, which is the other electrode of the capacitor, is typically connected to the common cell plate and the cell plate voltage VCP is applied. In general, the VCP voltage is defined as one half level of the power supply voltage, that is, half VDD.

On the other hand, the bit line sense amplifiers S / A are connected to the bit line pairs BL and / BL. When the word line WL0 is activated and cell data is transmitted to the positive bit line BL, a reference voltage REF is applied to the sub bit line /BL.The word bit WL2 is activated and a positive bit is transmitted to the sub bit line / BL. The reference voltage REF is applied to the line BL. The data input / output of the bit line sense amplifiers S / A is performed through differential local data buses LDB and LDBB.

2 is a circuit diagram of a typical bit line sense amplifier block.

Referring to FIG. 2, the bit line sense amplifier S / A is implemented in various forms, but typically includes two PMOS transistors connected between a pull-up power line (RTO line) and a bit line pair BL and / BL. It is implemented by two NMOS transistors connected between a pull-down power line (Sb line) and a bit line pair (BL, / BL).

On the other hand, the bit line sense amplifier S / A is shared between the cell array 0 block disposed above and the cell array 1 block disposed below the bit line sense amplifier S / A, and between the bit line sense amplifier S / A and the memory cell array. A bit line separator, a bit line equalizer, a bit line precharge unit, a column selector, and the like are disposed.

First, between the bit line sense amplifier BLSA and the cell array 0 block, the upper bit line pair BLU and / BLU and the bit line sense amplifier BLSA are connected / disconnected under the control of the upper bit line separation signal BISH. Under control of the NMOS transistors m1 and m2 and the bit line equalization signal BLEQ, the bit line pairs BL and / BL are precharged to the bit line precharge voltage VBLP (usually at the VDD / 2 level). The NMOS transistors m3 and m4 and the NMOS transistors m0 for equalizing the upper bit line pairs BLU and / BLU are controlled by the bit line equalization signal BLEQ.

Also, between the bit line sense amplifier BLSA and the cell array 1 block, the lower bit line pair signal BISL is connected to and disconnects the lower bit line pairs BLD and / BLD and the bit line sense amplifier BLSA. NMOS transistors m5 and m6 for control, an NMOS transistor m7 for equalizing the lower bit line pairs BLD and / BLD under the control of the bit line equalization signal BLEQ, and a column select signal YI. Two NMOS transistors m8 and m9 are provided to selectively connect bit line pairs BL and / BL and differential local data buses LDB and LDBB.

3 is an operation timing diagram for the circuit of FIGS. 1 and 2.

FIG. 3 assumes that data '1' is stored in the storage node SN of the memory cell. First, in the precharge period (BLEQ is logic level high), the pull-up and pull-down power lines RTO and Sb of the bit line pairs BL and / BL and the bit line sense amplifiers S / A are connected to the bit line precharge voltage. (VBLP) is precharged.

Subsequently, when the active command is applied and the word line WL is activated at the high potential voltage Vpp level, the charges charged in the storage node SN of the memory cell connected to the word line WL share charge with the bit line. As a result, the potential of the positive bit line BL is slightly increased (BLEQ is logic level low).

Next, when the bit line sense amplifier S / A is enabled and power is applied to the pull-up and pull-down power lines RTO and Sb, the potentials of the positive bit line BL and the negative bit line BL are reversed. Amplify to VDD level and ground voltage level, where ground voltage becomes reference voltage REF, respectively.

Thereafter, the potentials of the amplified positive bit line BL and the negative bit line / BL are restored to the storage node SN of the memory cell, and then returned to the precharge state.

4 is an operation timing diagram of a pseudo SRAM according to the prior art.

Referring to FIG. 4, first, when the refresh cycle request signal is activated during the previous (N-1) operation cycle (T0 section), the (N) operation cycle starts and the refresh cycle signal is activated to activate the refresh cycle ( section t1). Subsequently, after the refresh cycle is completed, the normal cycle (t2 period) is performed to substantially access the memory cell.

Therefore, one normal cycle requires t1 + t2 to run, which means that the actual access time t _ac is equal to the refresh cycle time t1 than the access time t _acwr in the normal cycle excluding the refresh cycle. Means more. Therefore, the conventional pseudo SRAM has a problem in that operating characteristics are degraded as the read / write cycle time is increased.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a pseudo SRAM capable of preventing an increase in access time due to refresh.

According to an aspect of the present invention for achieving the above technical problem, a plurality of normal access bit lines and refresh access bit lines arranged in pairs, a plurality of normal access word lines and refresh arranged in pairs A memory cell array block having a matrix structure of an access word line, a cell capacitor, a normal access transistor for selectively connecting the cell capacitor and the normal access bit line under the control of the normal access word line, A unit memory cell composed of a refresh access transistor under the control of a refresh access word line for selectively connecting the cell capacitor and the refresh access bit line; A sense amplifier array block for normal access disposed on one side of a column of the memory cell array block and connected to the normal access bit line; A refresh access sense amplifier array block disposed on the other side in the column direction of the memory cell array block and connected to the refresh access bit line; A local data bus for normal access connected to the sense amplifier array block for normal access; And a refresh access local data bus connected to the refresh access sense amplifier array block, wherein the two memory cells are selected within an active memory cell array block, and the normal access sense amplifier array block and the refresh are selected. A pseudo SRAM is provided wherein an access sense amplifier array block performs independent sense and amplification operations simultaneously.

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Preferably, an NMOS transistor is used as the normal access transistor and the refresh access transistor, respectively.

Refresh counting means for internally generating a refresh address; Address comparison means for comparing the normal address applied from the outside with the refresh address in response to the refresh cycle request signal; First switching means for selectively connecting said normal access local data bus and a global data bus in response to an output signal of said address comparing means; And second switching means for selectively connecting said refresh access local data bus and said global data bus in response to an output signal of said address comparing means.

The memory cell array block may be arranged on one side in a row direction, and the normal access sub word line driver array block for driving the normal access word line, and may be disposed on one side in a row direction of the memory cell array block. It is preferable to further include a refresh access sub wordline driver array block for driving the refresh access wordline.

Here, when the refresh cycle request signal transitions from an inactive state to an active state, if the normal address and the refresh address match, disable the refresh access word line corresponding to the refresh address, and set the refresh address. Increment by 1, maintain the turn-on state of the first switching means, and maintain the turn-off state of the second switching means.

On the other hand, when a new normal address is applied while the refresh cycle request signal is active, if the normal address and the refresh address match, the normal access word line corresponding to the normal address is disabled, and the refresh is performed. The refresh access word line corresponding to the address is enabled, the first switching means is turned off, and the second switching means is turned on.

In the present invention, the unit memory cell of the pseudo SRAM is implemented with two transistors and one capacitor (2T1C structure). One transistor is for refresh cycle operation and the other transistor is for normal cycle operation. The pseudo SRAM of the present invention allows the refresh cycle operation and the normal cycle operation to be performed in parallel with the conventional pseudo SRAM in which the refresh cycle operation and the normal cycle operation are separated into separate sections. Therefore, the operation speed of the pseudo SRAM accompanying the refresh can be prevented.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

5 is a diagram illustrating a configuration of a unit memory cell of a pseudo SRAM according to an embodiment of the present invention.

Referring to FIG. 5, in the unit memory cell of the pseudo SRAM according to the present embodiment, a cell capacitor C, a gate thereof is connected to a normal access word line WL0_N, and a drain thereof is a normal access bit line BL0_N. NMOS transistor T_N connected to the storage node SN of the cell capacitor C, the gate thereof is connected to the refresh access word line WL0_R, and the drain thereof is a refresh access. The refresh access NMOS transistor T_R is connected to the bit line BL0_R and its source is connected to the storage node SN of the cell capacitor C.

That is, the unit memory cell of the pseudo SRAM according to the present embodiment is composed of two access transistors and one cell capacitor (2T1C structure).

Here, the storage node SN of the cell capacitor C is commonly connected to the sources of the two NMOS transistors T_N and T_R, and the plate line PL receives the cell plate voltage VCP, typically VDD / 2.

On the other hand, the normal access word line WL0_N and the normal access bit line BL0_N are activated at the time of access by the normal address (external address), and the refresh access word line WL0_R and the refresh access bit line BL0_R ) Is activated upon access by the refresh counter address.

FIG. 6 is a diagram illustrating a layout of memory cells of the pseudo SRAM of FIG. 5. Two 2T1C cells are shown in the figure.

Referring to FIG. 6, the active regions for the NMOS transistors T_N and T_R are linearly arranged in the column direction, and the word lines WL0_N and WL0_R are disposed perpendicular to the active region, and the bit lines BL0_N and BL0_R are spaced apart from the active region in parallel. To be placed. However, the bit lines BL0_N and BL0_R include bit line contacts for electrical connection with the drains of the NMOS transistors T_N and T_R.

Here, memory cells adjacent in the vertical direction share the bit lines BL0_N and BL0_R, and have a symmetrical structure in the vertical direction.

When the unit memory cells are arranged in this manner, the interval (horizontal direction) of the active patterns is 2F, and the interval (vertical direction) of the two word lines WL0_N and WL0_R is 4F (F is the minimum line width). Therefore, the cell size of the 2T1C structure is 8F ² . The cell size of 8F ² is a structure that has been applied to a general DRAM, and it can be seen that although one transistor is increased as compared to a conventional pseudo SRAM cell, the size of the memory cell is hardly increased. On the other hand, if the line and the space are not the same, there is a possibility that the cell size can be further reduced.

FIG. 7 is a diagram illustrating a cell array (open bitline structure) and sensing related circuit of a pseudo SRAM according to an embodiment of the present invention.

Referring to FIG. 7, the pseudo SRAM according to the present exemplary embodiment includes a cell array in which the 2T1C cells of FIG. 5 are arranged in an open bit line manner.

The normal access sense amplifier array S / A_N connected to the normal access bit lines BL0_N, BL1_N, ... is disposed at one side of the sub-cell array block, and the refresh access connected to the refresh access bit line is disposed at the other side. The sense amplifier array S / A_R is disposed. The normal access sense amplifier array S / A_N and the refresh access sense amplifier array S / A_R are shared with up and down adjacent subcell array blocks.

On the other hand, each normal access sense amplifier is connected to the differential local data buses (LDB_N, LDBB_N) for normal access, and the differential local data buses (LDB_N, LDBB_N) and differential global data buses (GDB, GDBB) are connected to the global switch GSW_N. Is optionally connected via. In addition, each refresh access sense amplifier is connected to the differential access local data buses (LDB_R, LDBB_R) for refresh access, and the differential local data buses (LDB_R, LDBB_R) and differential global data buses (GDB, GDBB) support the global switch GSW_R. Is optionally connected via. That is, two global switches GSW_N and GSW_R are not turned on at the same time and either one is selectively turned on. M / A represents the main amplifier connected to the differential global data buses (GDB, GDBB).

The sub word line driver array SWD_N for driving the normal access word lines WL0_N, WL1_N, ... is disposed at one horizontal direction of the sub cell array block, and the refresh access word lines WL0_R are disposed at the other side. A sub word line driver array SWD_R for driving, WL1_R, ... is disposed.

8 is an operation timing diagram of a pseudo SRAM according to an embodiment of the present invention.

As described above, since the pseudo SRAM according to the present embodiment has two access paths to one memory cell (the normal access path and the refresh access path), the normal cycle by the external address and the refresh cycle by the internal refresh counter address are reduced. Each will work independently. That is, the refresh cycle may proceed even during the normal cycle, and conversely, the normal cycle may proceed even while the refresh cycle is in progress.

However, when the external address and the refresh counter address are the same, the normal access word line and the refresh access word line corresponding to one memory cell may be activated at the same time, so processing for the same address case is necessary.

First, as in the case of the address comparison point A, when the refresh cycle request signal is activated while the normal cycle N is in progress, and the refresh cycle M is enabled, the external address and refresh of the normal cycle N are refreshed. The counter addresses are compared. If the addresses do not match, the refresh cycle signal is activated to proceed with the refresh cycle M. If the addresses match, the refresh cycle M is skipped. Of course, the normal cycle N continues regardless of whether the addresses match. Here, the refresh cycle M is skipped, meaning that the refresh access word line WL_R on the cell array is inactivated.

On the other hand, as in the case of the address comparison point B, when a new external address is applied during the refresh cycle M and the next normal cycle N + 1 is enabled, the newly applied external address and refresh counter address are enabled. If the addresses do not match, the normal cycle N + 1 is advanced, and if the addresses match, the normal cycle N + 1 is skipped. Of course, since the normal cycle and the refresh cycle are independently performed, the refresh cycle M continues regardless of the address comparison result. In this case, the skip of the normal cycle N + 1 means that the word line WL_N for normal access on the cell array is inactivated. In this case, access to the normal cycle N + 1 must be made. Therefore, access to the access target memory cell in the normal cycle N + 1 is performed by using the refresh access bit line BL_R and the refresh access global switch GSW_R.

The above operation process is illustrated in detail in FIGS. 9 and 10.

First, FIG. 9 is a diagram illustrating an operation when the normal cycle is performed before the refresh cycle.

Referring to FIG. 9, when the refresh cycle request signal is activated while the normal cycle N is in progress, the external address N corresponding to the corresponding normal cycle N and the current refresh counter address M in the address comparison circuit. ) To determine if the two addresses match.

If the two addresses match, that is, the external address N and the refresh counter address M are the same, the refresh cycle M is skipped and the refresh counter address is increased by one (M + 1). At this time, the normal access global switch GSW_N is normally turned on, and the refresh access global switch GSW_R is also turned off. In other words, in this case, the normal cycle N replaces the refresh cycle M. FIG.

On the other hand, in most cases where the two addresses do not match, the refresh cycle M corresponding to the refresh counter address is normally performed, and the refresh counter address is increased by one (M + 1). At this time, the normal access global switch GSW_N is normally turned on, and the refresh access global switch GSW_R is also turned off. In other words, in this case, the normal cycle N and the refresh cycle M are parallel to each other.

Next, FIG. 10 is a diagram illustrating an operation when the normal cycle is performed after the refresh cycle.

Referring to FIG. 10, when a new external address N + 1 is applied and a request for a new normal cycle N + 1 is made, when the activation state of the refresh request signal corresponding to the refresh cycle M is valid, The address comparison circuit compares the external address N + 1 with the refresh counter address M to determine whether the two addresses match.

If the two addresses match, that is, the external address N + 1 and the refresh counter address M are the same, the corresponding normal cycle N + 1 is skipped, and the refresh access path corresponding to the refresh cycle M is skipped. Open to replace the access corresponding to that normal cycle (N + 1). That is, the normal access global switch GSW_N is turned off and the refresh access global switch GSW_R is turned on.

On the other hand, in most cases where the two addresses do not coincide, the normal cycle N + 1 corresponding to the external address N + 1 may proceed normally. At this time, the normal access global switch GSW_N is normally turned on, and the refresh access global switch GSW_R is also turned off. In other words, in this case, the normal cycle N + 1 and the refresh cycle M are parallel to each other.

As described above, the pseudo SRAM according to the present exemplary embodiment may provide a normal access path and a refresh access path to one memory cell by introducing a memory cell having a 2T1C structure. Therefore, the normal cycle by the external address and the refresh cycle by the internal refresh counter address can be performed independently of each other, which means that an increase in access time due to refresh can be suppressed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, in the case of implementing a unit memory cell of a pseudo SRAM, a case in which a normal access transistor and a refresh access transistor are implemented as an NMOS transistor has been described as an example. The present invention also applies in case of replacement with.

In addition, in the above-described embodiment, the case of arranging the cell array of the pseudo SRAM in the form of an open bit line has been described as an example. This does not mean that the application of the 2T1C cell to the folded bit line scheme is excluded.

In addition, in the above-described embodiment, the case where the local data bus and the global data bus are implemented as differential types has been described as an example, but the shape of the data bus is not directly related to the technical spirit of the present invention.

The present invention described above has an effect of improving the operation speed of the pseudo SRAM by preventing an increase in access time accompanying the refresh of the pseudo SRAM. On the other hand, since the 2T1C cell can be implemented in a size similar to that of the existing 1T1C cell, the burden on the degree of integration is not great and mass productivity can be secured.

Claims (8)

delete delete delete delete delete delete A memory cell array block having a matrix structure consisting of a plurality of normal access bit lines and refresh access bit lines arranged in pairs, and a plurality of normal access word lines and refresh access word lines arranged in pairs. And a normal access transistor for selectively connecting the cell capacitor and the normal access bit line under control of the normal access word line, and a control of the cell capacitor and the refresh access under control of the refresh access word line. A unit memory cell consisting of refresh access transistors for selectively connecting bit lines; A sense amplifier array block for normal access disposed on one side of a column of the memory cell array block and connected to the normal access bit line; A refresh access sense amplifier array block disposed on the other side in the column direction of the memory cell array block and connected to the refresh access bit line; A local data bus for normal access connected to the sense amplifier array block for normal access; A local data bus for refresh access coupled to the sense amplifier array block for refresh access; Refresh counting means for internally generating a refresh address; Address comparison means for comparing the refresh address with an external address applied from outside in response to a refresh cycle request signal; First switching means for selectively connecting said normal access local data bus and a global data bus in response to an output signal of said address comparing means; And Second switching means for selectively connecting said refresh access local data bus and said global data bus in response to an output signal of said address comparing means, Selecting two memory cells in one active memory cell array block and simultaneously detecting and amplifying the normal access sense amplifier array block and the refresh access sense amplifier array block independently; When the refresh cycle request signal transitions from an inactive state to an active state, When the normal address and the refresh address coincide, the refresh access word line corresponding to the refresh address is disabled, the refresh address is increased by 1, the turn-on state of the first switching means is maintained, and A pseudo SRAM characterized by maintaining a turn off state of a second switching means. A memory cell array block having a matrix structure consisting of a plurality of normal access bit lines and refresh access bit lines arranged in pairs, and a plurality of normal access word lines and refresh access word lines arranged in pairs. And a normal access transistor for selectively connecting the cell capacitor and the normal access bit line under control of the normal access word line, and a control of the cell capacitor and the refresh access under control of the refresh access word line. A unit memory cell consisting of refresh access transistors for selectively connecting bit lines; A sense amplifier array block for normal access disposed on one side of a column of the memory cell array block and connected to the normal access bit line; A refresh access sense amplifier array block disposed on the other side in the column direction of the memory cell array block and connected to the refresh access bit line; A local data bus for normal access connected to the sense amplifier array block for normal access; A local data bus for refresh access coupled to the sense amplifier array block for refresh access; Refresh counting means for internally generating a refresh address; Address comparison means for comparing the refresh address with an external address applied from outside in response to a refresh cycle request signal; First switching means for selectively connecting said normal access local data bus and a global data bus in response to an output signal of said address comparing means; And Second switching means for selectively connecting said refresh access local data bus and said global data bus in response to an output signal of said address comparing means, Selecting two memory cells in one active memory cell array block and simultaneously detecting and amplifying the normal access sense amplifier array block and the refresh access sense amplifier array block independently; When a new normal address is applied while the refresh cycle request signal is active, If the normal address and the refresh address match, the normal access word line corresponding to the normal address is disabled, the refresh access word line corresponding to the refresh address is enabled, and the first switching means. Turning off the second switching means.

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