JP2000076145A - Fault detecting method for storage device, and storage control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the error of a single bit of data in a storage device or a single error of an address indication bit by using a code generating method for one of odd parity codes and even parity codes according to information generated from addresses. SOLUTION: A parity generator 60 for read addresses generates read address odd parity bits 61 for a read address 16 and a read parity converter 70 converts the read parity bits 52 to read data odd parity bits 71 with read address odd parity bits 61. A read parity inspection device 80 inspects the read address 51 and read data odd parity bits 71 on an odd parity basis. In case of an odd parity inspection inequality, a single code error of the data or a single error of the address indication codes is recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a failure in a storage device and a storage control device, and more particularly to a failure detection method and a storage control device suitable for detecting an address failure in a storage device using an error detection code. .

[0002]

2. Description of the Related Art Conventionally, as a method of detecting an address failure in a storage device, address information is allocated to a redundant portion of an error correction code having an error position indicating capability, and encoding / coding is performed together with data.
There is known a method of detecting an address mismatch between writing and reading by decoding. For example, Japanese Patent Laying-Open No. 2-206855 discloses a method using a parity check matrix to which information generated from an address is assigned.

[0003]

The above prior art uses a method of allocating address information to a plurality of redundant bits, and is excellent in an address failure detecting function. However, a plurality of redundant bits are stored in units of write addresses. It is necessary to provide a storage element for that purpose.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a storage system having a parity check code having a function of checking both data and address without increasing the number of bits of the parity check code for only data provided in a write address unit. It is to provide a detection method and a storage control device.

[0005]

According to the present invention, there is provided a method for detecting a failure in a storage device, comprising the steps of: using a parity code capable of detecting a single-bit error in a byte composed of a plurality of bits; Based on the write address or the information generated from the address, a single bit error of the data in the storage device can be achieved by using one of two types of codes, an odd parity code and an even parity code. Or detecting a single error in the address designating bit.

Further, the storage device of the present invention converts a parity code capable of detecting a single-bit error in a byte composed of a plurality of bits into an odd parity based on a write address or information generated from the address. Means for generating using any one of two kinds of codes, a code and an even parity code, and writing the generated parity code together with write data into a portion specified by a write address of a storage device. Means, means for reading data and a parity code from a portion designated by the read address of the storage device, and two kinds of codes of an odd parity code and an even parity code based on the read address or information generated from the address. Means for selecting any one of the code check methods, and the selected parity code check for the read data and the parity code. If an error is detected by law, characterized by having a single error, and recognizes means of a single-bit error or address indication bits, the data.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows an embodiment of a storage control device according to the present invention. A parity generator 20 for write data, a parity generator 30 for a write address, a generated parity converter 40, a storage device 50, a parity for a read address are shown. It comprises a generator 60, a read parity converter 70, and a read parity checker 80.

The operation of FIG. 1 is as follows. When writing,
When the storage target data 11 and the write address 15 are given, the write data parity generator 20 generates a write data odd parity bit 21 for the storage target data 11, and the write address parity generator 30 A write address odd parity bit 31 is generated for the address 15, and in the generated parity converter 40, the write data odd parity bit 21 is converted into a write parity bit 41 by the write address odd parity bit 31, and the converted parity bit is converted. The write parity bit 41 and the write data 11 are written to a location specified by the write address 15 in the storage device 50.

At the time of reading, when a read address 16 is given, the storage device 5 designated by the read address 16 is read.
The read data 51 and the read parity bit 52 are read from the 0 position. In the read address parity generator 60, a read address odd parity bit 61 is generated for the read address 16, and in the read parity converter 70, the read parity bit 52 is read by the read address odd parity bit 61. The data is converted to odd parity bits 71. In the read parity checker 80, the read data 51 and the read data odd parity bit 71
Are odd parity checked. If the odd parity check does not match, it is recognized as a single code error in the data or a single error in the address designating code.

In this embodiment, an odd parity code for the write data is generated in advance, and the parity code is subjected to an exclusive OR operation with the odd parity code for the write address. A case is shown in which generation of an even-number parity code is selected, and read data is decoded in a similar manner. Even if the parity code generated in advance is an even parity, the same effect can be obtained by using the same method on the reading side.

Also, the case where an odd parity code of each address is used as the information based on the write address and the read address is shown. However, if the method is based on the same rule between the write address and the read address, The same effect can be obtained. Further, the parity code and the read parity code to be written into the storage device can be generated and checked at once with the write and read data together with the address-based information without using a converter as in the present embodiment.

[0013]

As is apparent from the above description, according to the present invention, not only data errors but also address errors can be detected without increasing the number of bits of the parity code.

[Brief description of the drawings]

FIG. 1 is a block diagram of a failure detection unit of a storage device according to an embodiment of the present invention.

[Explanation of symbols]

11: Data to be stored, 15: Write address, 1
6 read address, 20 write data parity generator, 21 write data odd parity bit, 30
Parity of the write address, 31: odd parity bit of the write address, 40: generated parity converter,
41: Write parity bit, 50: Storage device, 51: Read data, 52: Read parity, 60: Parity generator of read address, 61
... Read address odd parity bit, 70 read parity converter, 71 read data odd parity bit, 80 read parity checker.

Claims (3)

[Claims] A method for detecting a failure in a storage device using a parity code capable of detecting a single-bit error in a byte composed of a plurality of bits, the method comprising: detecting a write address or information generated from the address; Based on the parity code, any one of two kinds of codes, an odd parity code and an even parity code, is used to generate a single bit error in the data of the storage device or a single bit in the address indication bit. A failure detection method for a storage device, comprising detecting an error. 2. The storage device fault detection method according to claim 1, wherein at the time of writing, an odd parity code or an even parity code is applied to the write data based on the write address or information generated from the address. Write any parity code to the storage device,
At the time of reading, the data read from the storage device and the parity code are converted into the read address,
Alternatively, based on information generated from the address, a check is performed for either an odd parity code or an even parity code, and if there is an error, a single bit error in the data in the storage device or a single bit in the address indication bit is detected. A failure detection method for a storage device, characterized in that the failure is recognized as an error. 3. A storage control device for controlling writing and reading of a storage device, wherein a parity code capable of detecting a single-bit error in a byte composed of a plurality of bits is generated from a write address or the write address. Means for generating the parity code using one of two kinds of codes, an odd parity code and an even parity code, based on the information, and specifying the generated parity code together with the write data by a write address of a storage device. Means for writing to a specified part, means for reading data and a parity code from a part specified by a read address of the storage device, and a read address or information generated from the address,
A means for selecting one of two kinds of codes, an odd parity code and an even parity code, and a method for detecting the error between the read data and the parity code by the selected parity code checking method. A storage control device comprising means for recognizing a single bit error or a single error of an address indication bit.